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arch/xtensa/esp32s2: Update E-Fuse driver
Updates E-Fuse driver for ESP32S2, sharing a common implementation for Xtensa devices. Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
This commit is contained in:
Filipe Cavalcanti
committed by
Tiago Medicci Serrano
Tiago Medicci Serrano
parent
13e24e0c78
commit
8d6dcd61ed
@@ -369,10 +369,8 @@ config ESP32S2_SPIRAM
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default n
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default n
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config ESP32S2_EFUSE
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config ESP32S2_EFUSE
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bool "EFUSE support"
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bool
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default n
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select ESPRESSIF_EFUSE
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---help---
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Enable ESP32-S2 efuse support.
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config ESP32S2_TIMER0
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config ESP32S2_TIMER0
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bool "64-bit Timer 0 (Group 0 Timer 0)"
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bool "64-bit Timer 0 (Group 0 Timer 0)"
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@@ -43,12 +43,6 @@ ifeq ($(CONFIG_ESP32S2_UART),y)
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CHIP_CSRCS += esp32s2_serial.c
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CHIP_CSRCS += esp32s2_serial.c
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endif
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endif
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ifeq ($(CONFIG_ESP32S2_EFUSE),y)
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CHIP_CSRCS += esp32s2_efuse.c
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CHIP_CSRCS += esp32s2_efuse_table.c
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CHIP_CSRCS += esp32s2_efuse_lowerhalf.c
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endif
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ifeq ($(CONFIG_ESP32S2_RNG),y)
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ifeq ($(CONFIG_ESP32S2_RNG),y)
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CHIP_CSRCS += esp32s2_rng.c
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CHIP_CSRCS += esp32s2_rng.c
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endif
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endif
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@@ -139,7 +133,7 @@ endif
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ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
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ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
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ifndef ESP_HAL_3RDPARTY_VERSION
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ifndef ESP_HAL_3RDPARTY_VERSION
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ESP_HAL_3RDPARTY_VERSION = e9a78c811578545e2bc673862d885a15bd6cbf67
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ESP_HAL_3RDPARTY_VERSION = 96185c5348c747d2e15baef639d0b2a842ecd504
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endif
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endif
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ifndef ESP_HAL_3RDPARTY_URL
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ifndef ESP_HAL_3RDPARTY_URL
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File diff suppressed because it is too large
Load Diff
@@ -1,189 +0,0 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s2/esp32s2_efuse.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_EFUSE_H
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#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_EFUSE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/efuse/efuse.h>
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* Type of eFuse blocks for ESP32S2 */
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typedef enum
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{
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EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */
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EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
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EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
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EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */
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EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */
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EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */
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EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */
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EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */
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EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */
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EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */
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EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */
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EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */
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EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */
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EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */
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EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */
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EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */
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EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */
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EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */
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EFUSE_BLK_KEY_MAX = 10,
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EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
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EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */
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EFUSE_BLK_MAX
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} esp_efuse_block_t;
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/****************************************************************************
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* Name: efuse_func_proc_t
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*
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* Description:
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* This is type of function that will handle the efuse field register.
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*
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* Input Parameters:
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* num_reg - The register number in the block.
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* bit_start - Start bit in the register.
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* bit_count - The number of bits used in the register.
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* arr - A pointer to an array or variable.
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* bits_counter - Counter bits.
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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typedef int (*efuse_func_proc_t) (uint32_t num_reg,
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int bit_start,
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int bit_count,
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void *arr, int *bits_counter);
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: esp32s2_efuse_read_field
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*
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* Description:
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* Read value from EFUSE, writing it into an array.
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*
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* Input Parameters:
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* field - A pointer to describing the fields of efuse
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* dst - A pointer to array that contains the data for reading
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* dst_size_bits - The number of bits required to read
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s2_efuse_read_field(const efuse_desc_t *field[], void *dst,
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size_t dst_size_bits);
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/****************************************************************************
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* Name: esp32s2_efuse_write_field
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*
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* Description:
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* Write array to EFUSE.
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*
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* Input Parameters:
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* field - A pointer to describing the fields of efuse
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* src - A pointer to array that contains the data for writing
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* src_size_bits - The number of bits required to write
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s2_efuse_write_field(const efuse_desc_t *field[],
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const void *src, size_t src_size_bits);
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/****************************************************************************
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* Name: esp32s2_efuse_burn_efuses
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*
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* Description:
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* Burn values written to the efuse write registers.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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void esp32s2_efuse_burn_efuses(void);
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/****************************************************************************
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* Name: esp32s2_efuse_initialize
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*
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* Description:
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* Initialize the efuse driver. The efuse is initialized
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* and registered as 'devpath'.
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*
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* Input Parameters:
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* devpath - The full path to the efuse device.
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* This should be of the form /dev/efuse
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s2_efuse_initialize(const char *devpath);
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#ifdef __cplusplus
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}
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#endif
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#undef EXTERN
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_EFUSE_H */
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@@ -1,241 +0,0 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s2/esp32s2_efuse_lowerhalf.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <stdlib.h>
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#include <debug.h>
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#include <assert.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/efuse/efuse.h>
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#include "hardware/esp32s2_soc.h"
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#include "esp32s2_efuse.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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struct esp32s2_efuse_lowerhalf_s
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{
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const struct efuse_ops_s *ops; /* Lower half operations */
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void *upper; /* Pointer to efuse_upperhalf_s */
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};
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/****************************************************************************
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* Private Functions Prototypes
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****************************************************************************/
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/* "Lower half" driver methods */
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static int esp32s2_efuse_lowerhalf_read(struct efuse_lowerhalf_s *lower,
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const efuse_desc_t *field[],
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uint8_t *data, size_t bits_len);
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static int esp32s2_efuse_lowerhalf_write(struct efuse_lowerhalf_s *lower,
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const efuse_desc_t *field[],
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const uint8_t *data,
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size_t bits_len);
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static int esp32s2_efuse_lowerhalf_ioctl(struct efuse_lowerhalf_s *lower,
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int cmd, unsigned long arg);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* "Lower half" driver methods */
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static const struct efuse_ops_s g_esp32s2_efuse_ops =
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{
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.read_field = esp32s2_efuse_lowerhalf_read,
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.write_field = esp32s2_efuse_lowerhalf_write,
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.ioctl = esp32s2_efuse_lowerhalf_ioctl,
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};
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/* EFUSE lower-half */
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static struct esp32s2_efuse_lowerhalf_s g_esp32s2_efuse_lowerhalf =
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{
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.ops = &g_esp32s2_efuse_ops,
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.upper = NULL,
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};
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/****************************************************************************
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* Private functions
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****************************************************************************/
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/****************************************************************************
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* Name: esp32s2_efuse_lowerhalf_read
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*
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* Description:
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* Read value from EFUSE, writing it into an array.
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of
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* the "lower-half" driver state structure
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* field - A pointer to describing the fields of efuse
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* dst - A pointer to array that contains the data for reading
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* bits_len - The number of bits required to read
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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static int esp32s2_efuse_lowerhalf_read(struct efuse_lowerhalf_s *lower,
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const efuse_desc_t *field[],
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uint8_t *data, size_t bits_len)
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{
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int ret = OK;
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/* Read the requested field */
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ret = esp32s2_efuse_read_field(field, data, bits_len);
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return ret;
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}
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/****************************************************************************
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* Name: esp32s2_efuse_lowerhalf_write
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*
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* Description:
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* Write array to EFUSE.
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*
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* Input Parameters:
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* lower - A pointer the publicly visible representation of
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* the "lower-half" driver state structure
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* field - A pointer to describing the fields of efuse
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* data - A pointer to array that contains the data for writing
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* bits_len - The number of bits required to write
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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static int esp32s2_efuse_lowerhalf_write(struct efuse_lowerhalf_s *lower,
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const efuse_desc_t *field[],
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const uint8_t *data,
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size_t bits_len)
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{
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irqstate_t flags;
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int ret = OK;
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flags = enter_critical_section();
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/* Write the blob data to the field */
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ret = esp32s2_efuse_write_field(field, data, bits_len);
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/* Burn the EFUSEs */
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esp32s2_efuse_burn_efuses();
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leave_critical_section(flags);
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return ret;
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}
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/****************************************************************************
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* Name: esp32s2_efuse_lowerhalf_ioctl
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*
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* Description:
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|
||||||
* Initialize the efuse driver. The efuse is initialized
|
|
||||||
* and registered as 'devpath'.
|
|
||||||
*
|
|
||||||
* Input Parameters:
|
|
||||||
* lower - A pointer the publicly visible representation of
|
|
||||||
* the "lower-half" driver state structure
|
|
||||||
* cmd - The ioctl command value
|
|
||||||
* arg - The optional argument that accompanies the 'cmd'
|
|
||||||
*
|
|
||||||
* Returned Value:
|
|
||||||
* Zero (OK) is returned on success. Otherwise -1 (ERROR).
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
static int esp32s2_efuse_lowerhalf_ioctl(struct efuse_lowerhalf_s *lower,
|
|
||||||
int cmd, unsigned long arg)
|
|
||||||
{
|
|
||||||
int ret = OK;
|
|
||||||
|
|
||||||
switch (cmd)
|
|
||||||
{
|
|
||||||
/* We don't have proprietary EFUSE ioctls */
|
|
||||||
|
|
||||||
default:
|
|
||||||
{
|
|
||||||
minfo("Unrecognized cmd: %d\n", cmd);
|
|
||||||
ret = -ENOTTY;
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Public Functions
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
/****************************************************************************
|
|
||||||
* Name: esp32s2_efuse_initialize
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Initialize the efuse driver. The efuse is initialized
|
|
||||||
* and registered as 'devpath'.
|
|
||||||
*
|
|
||||||
* Input Parameters:
|
|
||||||
* devpath - The full path to the efuse device.
|
|
||||||
* This should be of the form /dev/efuse
|
|
||||||
*
|
|
||||||
* Returned Value:
|
|
||||||
* Zero (OK) is returned on success. Otherwise -1 (ERROR).
|
|
||||||
*
|
|
||||||
****************************************************************************/
|
|
||||||
|
|
||||||
int esp32s2_efuse_initialize(const char *devpath)
|
|
||||||
{
|
|
||||||
struct esp32s2_efuse_lowerhalf_s *lower = NULL;
|
|
||||||
int ret = OK;
|
|
||||||
|
|
||||||
DEBUGASSERT(devpath != NULL);
|
|
||||||
|
|
||||||
lower = &g_esp32s2_efuse_lowerhalf;
|
|
||||||
|
|
||||||
/* Register the efuse upper driver */
|
|
||||||
|
|
||||||
lower->upper = efuse_register(devpath,
|
|
||||||
(struct efuse_lowerhalf_s *)lower);
|
|
||||||
|
|
||||||
if (lower->upper == NULL)
|
|
||||||
{
|
|
||||||
/* The actual cause of the failure may have been a failure to allocate
|
|
||||||
* perhaps a failure to register the efuser driver (such as if the
|
|
||||||
* 'devpath' were not unique). We know here but we return EEXIST to
|
|
||||||
* indicate the failure (implying the non-unique devpath).
|
|
||||||
*/
|
|
||||||
|
|
||||||
ret = -EEXIST;
|
|
||||||
}
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -98,12 +98,16 @@ ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)
|
|||||||
|
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)adc_cali.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)adc_cali.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_cali_line_fitting.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_cali_line_fitting.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c
|
||||||
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_startup.c
|
||||||
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_calib.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_calib.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_table.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_table.c
|
||||||
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c
|
||||||
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)esp_app_desc.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)esp_app_desc.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c
|
||||||
@@ -211,9 +215,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
|
|||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
|
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c
|
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c
|
|
||||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c
|
|
||||||
|
|
||||||
LDFLAGS += --wrap=bootloader_print_banner
|
LDFLAGS += --wrap=bootloader_print_banner
|
||||||
endif
|
endif
|
||||||
|
|||||||
@@ -62,8 +62,8 @@
|
|||||||
# include "esp32s2_rt_timer.h"
|
# include "esp32s2_rt_timer.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ESP32S2_EFUSE
|
#ifdef CONFIG_ESPRESSIF_EFUSE
|
||||||
# include "esp32s2_efuse.h"
|
# include "espressif/esp_efuse.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_ESPRESSIF_LEDC
|
#ifdef CONFIG_ESPRESSIF_LEDC
|
||||||
@@ -170,8 +170,8 @@ int esp32s2_bringup(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_ESP32S2_EFUSE)
|
#if defined(CONFIG_ESPRESSIF_EFUSE)
|
||||||
ret = esp32s2_efuse_initialize("/dev/efuse");
|
ret = esp_efuse_initialize("/dev/efuse");
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
{
|
{
|
||||||
syslog(LOG_ERR, "ERROR: Failed to init EFUSE: %d\n", ret);
|
syslog(LOG_ERR, "ERROR: Failed to init EFUSE: %d\n", ret);
|
||||||
|
|||||||
Reference in New Issue
Block a user