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drivers/net, include/nuttx/net: Add AR8031 PHY
Summary: - This commit adds AR8031 PHY definitions Impact: - None Testing: - Tested with sabre-6quad:netnsh_ar8031 (will be added later) Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
committed by
Xiang Xiao
parent
dc914f43ea
commit
8c89052fb3
@@ -414,6 +414,9 @@ config ETH0_PHY_NONE
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config ETH0_PHY_AM79C874
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config ETH0_PHY_AM79C874
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bool "AMD Am79C874 PHY"
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bool "AMD Am79C874 PHY"
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config ETH0_PHY_AR8031
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bool "Atheros AR8031 PHY"
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config ETH0_PHY_KS8721
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config ETH0_PHY_KS8721
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bool "Micrel KS8721 PHY"
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bool "Micrel KS8721 PHY"
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@@ -59,6 +59,10 @@
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* abilities
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* abilities
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*/
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*/
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/* AR8031: */
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#define MII_AR8031_PSSR 0x11 /* Phy-Specific Status Register */
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/* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f
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/* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f
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* reserved
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* reserved
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*/
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*/
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@@ -841,6 +845,17 @@
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#define MII_DP83848C_FHF_INT_EN (1 << 1) /* Enable Interrupt on False Carrier Counter Register half-full event. */
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#define MII_DP83848C_FHF_INT_EN (1 << 1) /* Enable Interrupt on False Carrier Counter Register half-full event. */
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#define MII_DP83848C_RHF_INT_EN (1 << 0) /* Enable Interrupt on Receive Error Counter Register half-full event. */
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#define MII_DP83848C_RHF_INT_EN (1 << 0) /* Enable Interrupt on Receive Error Counter Register half-full event. */
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/* Atheros AR8031 MII ID1/2 register bits */
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#define MII_PHYID1_AR8031 0x004d /* ID1 value for AR8031 */
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#define MII_PHYID2_AR8031 0xd074 /* ID2 value for AR8031 */
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#define MII_AR8031_PSSR_SPEEDMASK (3 << 14) /* Bit 14-15: Speed */
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#define MII_AR8031_PSSR_10MBPS (0 << 14)
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#define MII_AR8031_PSSR_100MBPS (1 << 14)
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#define MII_AR8031_PSSR_1000MBPS (2 << 14)
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#define MII_AR8031_PSSR_DUPLEX (1 << 13) /* Bit 13: Full duplex mode */
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/****************************************************************************
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/****************************************************************************
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* Type Definitions
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* Type Definitions
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****************************************************************************/
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****************************************************************************/
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