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arch/arm/src/stm32h7/hardware/stm32_tim.h: Fix ATIM_BDTR_BK2P define

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arch/arm/src/stm32h7/hardware/stm32_tim.h: Fix ATIM_AF2 bitfields wrongly allocated to ATIM_AF1
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h: Fix ATIM_AF2 bitfields wrongly allocated to ATIM_AF1
arch/arm/src/stm32h7/stm32_tim.c: Fix some copy'n'paste errors on defines
This commit is contained in:
Daniel Pereira Volpato
2019-10-07 21:59:28 -06:00
committed by Gregory Nutt
parent 626c28dc30
commit 8c62600cc1
3 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
+3 -3
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@@ -737,9 +737,9 @@
/* Alternate function option register 2 (TIMx_AF2) */ /* Alternate function option register 2 (TIMx_AF2) */
#define ATIM_AF1_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ #define ATIM_AF2_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */
#define ATIM_AF1_BK2DFBKE (1 << 8) /* Bit 8: BRK2 DFSDM_BREAK enable */ #define ATIM_AF2_BK2DFBKE (1 << 8) /* Bit 8: BRK2 DFSDM_BREAK enable */
#define ATIM_AF1_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */ #define ATIM_AF2_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */
/* Break and dead-time register */ /* Break and dead-time register */
arch/arm/src/stm32h7/hardware/stm32_tim.h
+4 -4
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@@ -750,9 +750,9 @@
/* Alternate function option register 2 (TIMx_AF2) */ /* Alternate function option register 2 (TIMx_AF2) */
#define ATIM_AF1_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */ #define ATIM_AF2_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */
#define ATIM_AF1_BK2DFBKE (1 << 8) /* Bit 8: BRK2 DFSDM_BREAK enable */ #define ATIM_AF2_BK2DFBKE (1 << 8) /* Bit 8: BRK2 DFSDM_BREAK enable */
#define ATIM_AF1_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */ #define ATIM_AF2_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN2 input polarity */
/* Break and dead-time register */ /* Break and dead-time register */
@@ -807,7 +807,7 @@
# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */ # define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */ # define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
#define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ #define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */
#define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */ #define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */
/* DMA control register */ /* DMA control register */
arch/arm/src/stm32h7/stm32_tim.c
+3 -3
View File
@@ -203,7 +203,7 @@
#if defined(CONFIG_STM32H7_TIM8) #if defined(CONFIG_STM32H7_TIM8)
# if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\
defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\
defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT)
# define HAVE_TIM8_GPIOCONFIG 1 # define HAVE_TIM8_GPIOCONFIG 1
# endif # endif
#endif #endif
@@ -1344,13 +1344,13 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
#endif #endif
#ifdef CONFIG_STM32H7_TIM13 #ifdef CONFIG_STM32H7_TIM13
case 13: case 13:
dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN);
break; break;
#endif #endif
#ifdef CONFIG_STM32H7_TIM14 #ifdef CONFIG_STM32H7_TIM14
case 14: case 14:
dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv;
modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN);
break; break;
#endif #endif