diff --git a/arch/risc-v/src/common/espressif/esp_rtc_gpio.c b/arch/risc-v/src/common/espressif/esp_rtc_gpio.c
index 53d613cab10..f572801e22a 100644
--- a/arch/risc-v/src/common/espressif/esp_rtc_gpio.c
+++ b/arch/risc-v/src/common/espressif/esp_rtc_gpio.c
@@ -43,7 +43,7 @@
 #include "hal/rtc_io_hal.h"
 #include "soc/rtc_cntl_periph.h"
 #include "soc/periph_defs.h"
-#ifdef CONFIG_ARCH_CHIP_ESP32C6
+#if defined(CONFIG_ARCH_CHIP_ESP32C6) || defined(CONFIG_ARCH_CHIP_ESP32P4)
 #include "driver/rtc_io.h"
 #include "hal/rtc_io_ll.h"
 #include "hal/rtc_io_hal.h"
@@ -384,7 +384,7 @@ void esp_rtcioirqdisable(int irq)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_ARCH_CHIP_ESP32C6
+#if defined(CONFIG_ARCH_CHIP_ESP32C6) || defined(CONFIG_ARCH_CHIP_ESP32P4)
 int esp_rtcio_config_gpio(int pin, enum esp_rtc_gpio_mode_e mode)
 {
   int ret = rtc_gpio_init(pin);
@@ -436,4 +436,4 @@ void esp_rtcio_write(int pin, bool value)
 {
   rtc_gpio_set_level(pin, value);
 }
-#endif /* CONFIG_ARCH_CHIP_ESP32C6 */
+#endif /* CONFIG_ARCH_CHIP_ESP32C6 || CONFIG_ARCH_CHIP_ESP32P4 */
diff --git a/arch/risc-v/src/common/espressif/esp_rtc_gpio.h b/arch/risc-v/src/common/espressif/esp_rtc_gpio.h
index 1ca6f732726..33732d93f11 100644
--- a/arch/risc-v/src/common/espressif/esp_rtc_gpio.h
+++ b/arch/risc-v/src/common/espressif/esp_rtc_gpio.h
@@ -165,7 +165,7 @@ void esp_rtcioirqdisable(int irq);
 #  define esp_rtcioirqdisable(irq)
 #endif
 
-#ifdef CONFIG_ARCH_CHIP_ESP32C6
+#if defined(CONFIG_ARCH_CHIP_ESP32C6) || defined(CONFIG_ARCH_CHIP_ESP32P4)
 /****************************************************************************
  * Name: esp_rtcio_config_gpio
  *
@@ -215,7 +215,7 @@ int esp_rtcio_read(int pin);
  ****************************************************************************/
 
 void esp_rtcio_write(int pin, bool value);
-#endif /* CONFIG_ARCH_CHIP_ESP32C6 */
+#endif /* CONFIG_ARCH_CHIP_ESP32C6 || CONFIG_ARCH_CHIP_ESP32P4 */
 
 #endif /* __ASSEMBLY__ */
 #endif /* __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RTC_GPIO_H */
diff --git a/arch/risc-v/src/esp32p4/hal_esp32p4.mk b/arch/risc-v/src/esp32p4/hal_esp32p4.mk
index eeed9682622..38c595dd28d 100644
--- a/arch/risc-v/src/esp32p4/hal_esp32p4.mk
+++ b/arch/risc-v/src/esp32p4/hal_esp32p4.mk
@@ -199,7 +199,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)gpio_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)rtc_io_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)sdm_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)spi_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal_iram.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal.c
@@ -247,6 +249,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)io_mux.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)peripheral_domain_pd.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c