diff --git a/arch/arm/src/stm32f7/stm32_fmc.h b/arch/arm/src/stm32f7/stm32_fmc.h new file mode 100644 index 00000000000..3dfd505c0fa --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_fmc.h @@ -0,0 +1,143 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/stm32_fmc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32F7_FMC_H +#define __ARCH_ARM_SRC_STM32_STM32F7_FMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */ +#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */ + +#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */ +#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */ + +#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */ +#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */ +#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */ + +/* Register Addresses ***************************************************************/ + +#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET) +#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET) + +#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET) +#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET) + +#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET) +#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET) +#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +#define FMC_SDRAM_CR_COLBITS_8 0x00000000 +#define FMC_SDRAM_CR_COLBITS_9 0x00000001 +#define FMC_SDRAM_CR_COLBITS_10 0x00000002 +#define FMC_SDRAM_CR_COLBITS_11 0x00000003 + +#define FMC_SDRAM_CR_ROWBITS_11 0x00000000 +#define FMC_SDRAM_CR_ROWBITS_12 0x00000004 +#define FMC_SDRAM_CR_ROWBITS_13 0x00000008 + +#define FMC_SDRAM_CR_WIDTH_8 0x00000000 +#define FMC_SDRAM_CR_WIDTH_16 0x00000010 +#define FMC_SDRAM_CR_WIDTH_32 0x00000020 + +#define FMC_SDRAM_CR_BANKS_2 0x00000000 +#define FMC_SDRAM_CR_BANKS_4 0x00000040 + +#define FMC_SDRAM_CR_CASLAT_1 0x00000080 +#define FMC_SDRAM_CR_CASLAT_2 0x00000100 +#define FMC_SDRAM_CR_CASLAT_3 0x00000180 + +#define FMC_SDRAM_CR_WRITE_PROT 0x00000200 + +#define FMC_SDRAM_CR_SDCLK_DISABLE 0x00000000 +#define FMC_SDRAM_CR_SDCLK_2X 0x00000800 +#define FMC_SDRAM_CR_SDCLK_3X 0x00000C00 + +#define FMC_SDRAM_CR_BURST_READ 0x00001000 + +#define FMC_SDRAM_CR_RPIPE_0 0x00000000 +#define FMC_SDRAM_CR_RPIPE_1 0x00002000 +#define FMC_SDRAM_CR_RPIPE_2 0x00004000 + +#define FMC_SDRAM_TR_TMRD_SHIFT 0 +#define FMC_SDRAM_TR_TXSR_SHIFT 4 +#define FMC_SDRAM_TR_TRAS_SHIFT 8 +#define FMC_SDRAM_TR_TRC_SHIFT 12 +#define FMC_SDRAM_TR_TWR_SHIFT 16 +#define FMC_SDRAM_TR_TRP_SHIFT 20 +#define FMC_SDRAM_TR_TRCD_SHIFT 24 + +#define FMC_SDRAM_MODE_CMD_NORMAL 0 +#define FMC_SDRAM_MODE_CMD_CLK_ENABLE 1 +#define FMC_SDRAM_MODE_CMD_PALL 2 +#define FMC_SDRAM_MODE_CMD_AUTO_REFRESH 3 +#define FMC_SDRAM_MODE_CMD_LOAD_MODE 4 +#define FMC_SDRAM_MODE_CMD_SELF_REFRESH 5 +#define FMC_SDRAM_MODE_CMD_POWER_DOWN 6 + +#define FMC_SDRAM_CMD_BANK_1 0x00000010 +#define FMC_SDRAM_CMD_BANK_2 0x00000008 + +#define FMC_SDRAM_AUTO_REFRESH_SHIFT 5 +#define FMC_SDRAM_MODEREG_SHIFT 9 + +#define FMC_SDRAM_MODEREG_BURST_LENGTH_1 (0x0000 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_BURST_LENGTH_2 (0x0001 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_BURST_LENGTH_4 (0x0002 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_BURST_LENGTH_8 (0x0004 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_CAS_LATENCY_2 (0x0020 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_CAS_LATENCY_3 (0x0030 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FMC_SDRAM_MODEREG_SHIFT) +#define FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200 << FMC_SDRAM_MODEREG_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32_STM32F7_FMC_H */ diff --git a/configs/stm32f746g-disco/fb/README.txt b/configs/stm32f746g-disco/fb/README.txt index fe2a675d83f..ae58cf4deb7 100644 --- a/configs/stm32f746g-disco/fb/README.txt +++ b/configs/stm32f746g-disco/fb/README.txt @@ -3,49 +3,6 @@ README.txt STM32F746G-DISCO LTDC Framebuffer demo example -Preparation ------------ - -As of writing this text, SDRAM support is not implemented for this board. -Therefore to make this demo work following changes are required to heap -management function: - - -diff --git a/stm32_allocateheap.c b/stm32_allocateheap.c ---- a/stm32_allocateheap.c -+++ b/stm32_allocateheap.c -@@ -93,7 +93,7 @@ - /* Set the start and end of SRAM1 and SRAM2 */ - - #define SRAM1_START STM32_SRAM1_BASE --#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE) -+#define SRAM1_END (SRAM1_START + 131072) - - #define SRAM2_START STM32_SRAM2_BASE - #define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) -@@ -385,17 +385,17 @@ void up_addregion(void) - - /* Allow user-mode access to the STM32F20xxx/STM32F40xxx SRAM2 heap */ - -- stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START); -+/* stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END-SRAM2_START); */ - - #endif - - /* Colorize the heap for debug */ - -- up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); -+/* up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); */ - - /* Add the STM32F20xxx/STM32F40xxx SRAM2 user heap region. */ - -- kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); -+/* kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START); */ - - #ifdef HAVE_DTCM - #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) - - Configure and build ------------------- @@ -57,7 +14,7 @@ Configuration ------------ This configuration provides 1 LTDC with -8pp CLUT pixel format and a resolution of 480x272. +16bpp pixel format and a resolution of 480x272. Loading @@ -70,7 +27,8 @@ Executing --------- The ltdc is initialized during boot up. Interaction with NSH is via the serial -console at 115200 8N1 baud. From the nsh comandline execute the fb example: +console provided by ST-LINK USB at 115200 8N1 baud. +From the nsh comandline execute the fb example: nsh> fb diff --git a/configs/stm32f746g-disco/fb/defconfig b/configs/stm32f746g-disco/fb/defconfig index cd9d9a3be9a..3b3f55d8a30 100644 --- a/configs/stm32f746g-disco/fb/defconfig +++ b/configs/stm32f746g-disco/fb/defconfig @@ -1,6 +1,7 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32F7_FB_CMAP is not set # CONFIG_STM32F7_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" @@ -17,6 +18,7 @@ CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y CONFIG_BOARD_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DISABLE_POLL=y CONFIG_DRIVERS_VIDEO=y @@ -50,11 +52,10 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 +CONFIG_STM32F7_FMC=y CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0x20030000 -CONFIG_STM32F7_LTDC_FB_SIZE=130560 -CONFIG_STM32F7_LTDC_INTERFACE=y -CONFIG_STM32F7_LTDC_L1_L8=y +CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32F7_LTDC_FB_SIZE=261120 CONFIG_STM32F7_USART1=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/configs/stm32f746g-disco/src/Makefile b/configs/stm32f746g-disco/src/Makefile index f782d07111e..777d05f68d1 100644 --- a/configs/stm32f746g-disco/src/Makefile +++ b/configs/stm32f746g-disco/src/Makefile @@ -68,4 +68,8 @@ ifeq ($(CONFIG_STM32F7_LTDC),y) CSRCS += stm32_lcd.c endif +ifeq ($(CONFIG_STM32F7_FMC),y) +CSRCS += stm32_extmem.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/stm32f746g-disco/src/stm32_boot.c b/configs/stm32f746g-disco/src/stm32_boot.c index bc83e2c5fcc..efa12d3bda1 100644 --- a/configs/stm32f746g-disco/src/stm32_boot.c +++ b/configs/stm32f746g-disco/src/stm32_boot.c @@ -89,6 +89,10 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif + +#ifdef CONFIG_STM32F7_FMC + stm32_enablefmc(); +#endif } /************************************************************************************ diff --git a/configs/stm32f746g-disco/src/stm32_extmem.c b/configs/stm32f746g-disco/src/stm32_extmem.c new file mode 100644 index 00000000000..4f79de44d2b --- /dev/null +++ b/configs/stm32f746g-disco/src/stm32_extmem.c @@ -0,0 +1,249 @@ +/************************************************************************************ + * configs/stm32f746g-disco/src/stm32_extmem.c + * + * Copyright (C) 2018 Marcin Wyrwas. All rights reserved. + * Author: Marcin Wyrwas + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" + +#include "stm32_fmc.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32f746g-disco.h" + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef CONFIG_STM32F7_FMC +# warning "FMC is not enabled" +#endif + +#if STM32F7_NGPIO < 7 +# error "Required GPIO ports not enabled" +#endif + +#define STM32_FMC_NADDRCONFIGS 22 +#define STM32_FMC_NDATACONFIGS 16 + +#define STM32_SDRAM_CLKEN FMC_SDRAM_MODE_CMD_CLK_ENABLE | FMC_SDRAM_CMD_BANK_1 +#define STM32_SDRAM_PALL FMC_SDRAM_MODE_CMD_PALL | FMC_SDRAM_CMD_BANK_1 +#define STM32_SDRAM_REFRESH FMC_SDRAM_MODE_CMD_AUTO_REFRESH | FMC_SDRAM_CMD_BANK_1 |\ + (7 << FMC_SDRAM_AUTO_REFRESH_SHIFT) +#define STM32_SDRAM_MODEREG FMC_SDRAM_MODE_CMD_LOAD_MODE | FMC_SDRAM_CMD_BANK_1 |\ + FMC_SDRAM_MODEREG_BURST_LENGTH_1 | \ + FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ + FMC_SDRAM_MODEREG_CAS_LATENCY_3 |\ + FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE + + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/* GPIO configurations common to most external memories */ + +static const uint32_t g_addressconfig[STM32_FMC_NADDRCONFIGS] = +{ + GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, GPIO_FMC_A4 , GPIO_FMC_A5, + GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, + + GPIO_FMC_SDCKE0_1, GPIO_FMC_SDNE0_3, GPIO_FMC_SDNWE_3, GPIO_FMC_NBL0, + GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1, + GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS +}; + +static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] = +{ + GPIO_FMC_D0, GPIO_FMC_D1 , GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4 , GPIO_FMC_D5, + GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, + GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15 +}; + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_extmemgpios + * + * Description: + * Initialize GPIOs for external memory usage + * + ************************************************************************************/ + +static void stm32_extmemgpios(const uint32_t *gpios, int ngpios) +{ + int i; + + /* Configure GPIOs */ + + for (i = 0; i < ngpios; i++) + { + stm32_configgpio(gpios[i]); + } +} + +/************************************************************************************ + * Name: stm32_sdramcommand + * + * Description: + * Initialize data line GPIOs for external memory access + * + ************************************************************************************/ + +static void stm32_sdramcommand(uint32_t command) +{ + uint32_t regval; + volatile uint32_t timeout = 0xFFFF; + + regval = getreg32( STM32_FMC_SDSR ) & 0x00000020; + while ((regval != 0) && timeout-- > 0) + { + regval = getreg32( STM32_FMC_SDSR ) & 0x00000020; + } + putreg32(command, STM32_FMC_SDCMR); + timeout = 0xFFFF; + regval = getreg32( STM32_FMC_SDSR ) & 0x00000020; + while ((regval != 0) && timeout-- > 0) + { + regval = getreg32( STM32_FMC_SDSR ) & 0x00000020; + } +} + +/************************************************************************************ + * Name: stm32_enablefmc + * + * Description: + * enable clocking to the FMC module + * + ************************************************************************************/ + +void stm32_enablefmc(void) +{ + uint32_t regval; + volatile int count; + + /* Enable GPIOs as FMC / memory pins */ + + stm32_extmemgpios(g_addressconfig, STM32_FMC_NADDRCONFIGS); + stm32_extmemgpios(g_dataconfig, STM32_FMC_NDATACONFIGS); + + /* Enable AHB clocking to the FMC */ + + regval = getreg32( STM32_RCC_AHB3ENR); + regval |= RCC_AHB3ENR_FMCEN; + putreg32(regval, STM32_RCC_AHB3ENR); + + /* Configure and enable the SDRAM bank1 + * + * FMC clock = 216MHz/2 = 108MHz + * 108MHz = 9,26 ns + * All timings from the datasheet for Speedgrade -6A (=6ns) + */ + + putreg32(FMC_SDRAM_CR_RPIPE_0 | + FMC_SDRAM_CR_BURST_READ | + FMC_SDRAM_CR_SDCLK_2X | + FMC_SDRAM_CR_CASLAT_3 | + FMC_SDRAM_CR_BANKS_4 | + FMC_SDRAM_CR_WIDTH_16 | + FMC_SDRAM_CR_ROWBITS_12 | + FMC_SDRAM_CR_COLBITS_8, + STM32_FMC_SDCR1); + + putreg32((1 << FMC_SDRAM_TR_TRCD_SHIFT) | /* tRCD min = 18ns */ + (1 << FMC_SDRAM_TR_TRP_SHIFT) | /* tRP min = 18ns */ + (1 << FMC_SDRAM_TR_TWR_SHIFT) | /* tWR = 2CLK */ + (6 << FMC_SDRAM_TR_TRC_SHIFT) | /* tRC min = 64ns */ + (4 << FMC_SDRAM_TR_TRAS_SHIFT) | /* tRAS min = 46ns */ + (7 << FMC_SDRAM_TR_TXSR_SHIFT) | /* tXSR min = 74ns */ + (1 << FMC_SDRAM_TR_TMRD_SHIFT), /* tMRD = 2CLK */ + STM32_FMC_SDTR1); + + /* SDRAM Initialization sequence */ + + stm32_sdramcommand(STM32_SDRAM_CLKEN); /* Clock enable command */ + for (count = 0; count < 10000; count++) ; /* Delay */ + stm32_sdramcommand(STM32_SDRAM_PALL); /* Precharge ALL command */ + stm32_sdramcommand(STM32_SDRAM_REFRESH); /* Auto refresh command */ + stm32_sdramcommand(STM32_SDRAM_MODEREG); /* Mode Register program */ + + /* Set refresh count + * + * FMC_CLK = 108MHz + * Refresh_Rate = 64ms / 4096 rows = 15.63us + * Counter = (FMC_CLK * Refresh_Rate) - 20 + */ + + putreg32(1668 << 1, STM32_FMC_SDRTR); +} + +/************************************************************************************ + * Name: stm32_disablefmc + * + * Description: + * enable clocking to the FMC module + * + ************************************************************************************/ + +void stm32_disablefmc(void) +{ + uint32_t regval; + + /* Disable AHB clocking to the FMC */ + + regval = getreg32(STM32_RCC_AHB3ENR); + regval &= ~(uint32_t)RCC_AHB3ENR_FMCEN; + putreg32(regval, STM32_RCC_AHB3ENR); +} diff --git a/configs/stm32f746g-disco/src/stm32f746g-disco.h b/configs/stm32f746g-disco/src/stm32f746g-disco.h index 21c658f1104..cc858f0c26b 100644 --- a/configs/stm32f746g-disco/src/stm32f746g-disco.h +++ b/configs/stm32f746g-disco/src/stm32f746g-disco.h @@ -159,6 +159,32 @@ void weak_function stm32_spidev_initialize(void); void arch_sporadic_initialize(void); #endif +/**************************************************************************** + + * Name: stm32_enablefmc + * + * Description: + * enable clocking to the FMC module + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_FMC +void stm32_enablefmc(void); +#endif + +/**************************************************************************** + + * Name: stm32_disablefmc + * + * Description: + * disable clocking to the FMC module + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_FMC +void stm32_disablefmc(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_STM32F746G_DISCO_SRC_STM32F746G_DISCO_H */