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Updated SAMA5 SFR header file for the SAMA5D4

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This commit is contained in:
Gregory Nutt
2014-06-08 07:48:36 -06:00
parent 24af2deb30
commit 895851314f
3 changed files with 12 additions and 18 deletions
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configs/sama5d3-xplained/src/sam_sdram.c
+4 -6
View File
@@ -206,10 +206,10 @@ void sam_sdram_config(void)
regval |= MPDDRC_HS_AUTOREFRESH_CAL; regval |= MPDDRC_HS_AUTOREFRESH_CAL;
putreg32(regval, SAM_MPDDRC_HS); putreg32(regval, SAM_MPDDRC_HS);
/* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */ /* Force DDR_DQ and DDR_DQS input buffer always on */
regval = getreg32(SAM_SFR_DDRCFG); regval = getreg32(SAM_SFR_DDRCFG);
regval |= SFR_DDRCFG_DRQON; regval |= SFR_FDQIEN | SFR_FDQSIEN;
putreg32(regval, SAM_SFR_DDRCFG); putreg32(regval, SAM_SFR_DDRCFG);
/* Configure the slave offset register */ /* Configure the slave offset register */
@@ -235,11 +235,9 @@ void sam_sdram_config(void)
regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3));
putreg32(regval, SAM_MPDDRC_IO_CALIBR); putreg32(regval, SAM_MPDDRC_IO_CALIBR);
/* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits /* Force DDR_DQ and DDR_DQS input buffer always on */
* (undocumented)
*/
putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG); putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG);
/* Step 1: Program the memory device type /* Step 1: Program the memory device type
* *
configs/sama5d3x-ek/src/sam_sdram.c
+4 -6
View File
@@ -205,10 +205,10 @@ void sam_sdram_config(void)
regval |= MPDDRC_HS_AUTOREFRESH_CAL; regval |= MPDDRC_HS_AUTOREFRESH_CAL;
putreg32(regval, SAM_MPDDRC_HS); putreg32(regval, SAM_MPDDRC_HS);
/* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */ /* Force DDR_DQ and DDR_DQS input buffer always on */
regval = getreg32(SAM_SFR_DDRCFG); regval = getreg32(SAM_SFR_DDRCFG);
regval |= SFR_DDRCFG_DRQON; regval |= SFR_FDQIEN | SFR_FDQSIEN;
putreg32(regval, SAM_SFR_DDRCFG); putreg32(regval, SAM_SFR_DDRCFG);
/* Configure the slave offset register */ /* Configure the slave offset register */
@@ -234,11 +234,9 @@ void sam_sdram_config(void)
regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3));
putreg32(regval, SAM_MPDDRC_IO_CALIBR); putreg32(regval, SAM_MPDDRC_IO_CALIBR);
/* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits /* Force DDR_DQ and DDR_DQS input buffer always on */
* (undocumented)
*/
putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG); putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG);
/* Step 1: Program the memory device type /* Step 1: Program the memory device type
* *
configs/sama5d4-ek/src/sam_sdram.c
+4 -6
View File
@@ -206,10 +206,10 @@ void sam_sdram_config(void)
regval |= MPDDRC_HS_AUTOREFRESH_CAL; regval |= MPDDRC_HS_AUTOREFRESH_CAL;
putreg32(regval, SAM_MPDDRC_HS); putreg32(regval, SAM_MPDDRC_HS);
/* Force DDR_DQ and DDR_DQS input buffer always on (undocumented) */ /* Force DDR_DQ and DDR_DQS input buffer always on */
regval = getreg32(SAM_SFR_DDRCFG); regval = getreg32(SAM_SFR_DDRCFG);
regval |= SFR_DDRCFG_DRQON; regval |= SFR_FDQIEN | SFR_FDQSIEN;
putreg32(regval, SAM_SFR_DDRCFG); putreg32(regval, SAM_SFR_DDRCFG);
/* Configure the slave offset register */ /* Configure the slave offset register */
@@ -235,11 +235,9 @@ void sam_sdram_config(void)
regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3)); regval |= (MPDDRC_IO_CALIBR_RZQ48_40 | MPDDRC_IO_CALIBR_TZQIO(3));
putreg32(regval, SAM_MPDDRC_IO_CALIBR); putreg32(regval, SAM_MPDDRC_IO_CALIBR);
/* Force DDR_DQ and DDR_DQS input buffer always on, clearing other bits /* Force DDR_DQ and DDR_DQS input buffer always on */
* (undocumented)
*/
putreg32(SFR_DDRCFG_DRQON, SAM_SFR_DDRCFG); putreg32(SFR_FDQIEN | SFR_FDQSIEN, SAM_SFR_DDRCFG);
/* Step 1: Program the memory device type /* Step 1: Program the memory device type
* *