diff --git a/arch/arm/src/sam34/chip/sam3x_memorymap.h b/arch/arm/src/sam34/chip/sam3x_memorymap.h
index 47ce5d83105..4cad06dc067 100644
--- a/arch/arm/src/sam34/chip/sam3x_memorymap.h
+++ b/arch/arm/src/sam34/chip/sam3x_memorymap.h
@@ -65,7 +65,7 @@
 /* Internal SRAM memory region */
 
 #define SAM_INTSRAM0_BASE      0x20000000 /* 0x20000000-0x2007ffff: Internal SRAM 0 */
-#define SAM_INTSRAM1_BASE      0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 0 */
+#define SAM_INTSRAM1_BASE      0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */
 #define SAM_NFCSRAM_BASE       0x20100000 /* 0x20100000-0x2017ffff: NAND FLASH controller (SRAM) */
 #define SAM_UOTGHSRAM_BASE     0x20180000 /* 0x20100000-0x201fffff: UOTGHS controller (DMA) */
                                           /* 0x20200000-0x201fffff: Undefined */
diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c
index 763a9ba1984..93fae363db2 100644
--- a/arch/arm/src/sam34/sam_allocateheap.c
+++ b/arch/arm/src/sam34/sam_allocateheap.c
@@ -53,6 +53,7 @@
 
 #include "chip.h"
 #include "sam_mpuinit.h"
+#include "sam_periphclks.h"
 
 /****************************************************************************
  * Private Definitions
@@ -317,6 +318,15 @@ void up_addregion(void)
 #endif /* HAVE_SRAM1_REGION */
 
 #ifdef HAVE_NFCSRAM_REGION
+#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
+  /* In the 3X/3A family I note that clocking must appled to the SMC module
+   * in order for the NFCS SRAM to be functional.  I don't recall such an
+   * issue with the 3U.
+   */
+
+  sam_smc_enableclk();
+#endif
+
   /* Allow user access to the heap memory */
 
   sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE);