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sched/sleep: replace all Signal-based sleep implement to Scheduled sleep

Browse Source 
Nuttx currently has 2 types of sleep interfaces:

1. Signal-scheduled sleep: nxsig_sleep() / nxsig_usleep() / nxsig_nanosleep()
Weaknesses:
a. Signal-dependent: The signal-scheduled sleep method is bound to the signal framework, while some driver sleep operations do not depend on signals.
b. Timespec conversion: Signal-scheduled sleep involves timespec conversion, which has a significant impact on performance.

2. Busy sleep: up_mdelay() / up_udelay()
Weaknesses:
a. Does not actively trigger scheduling, occupy the CPU loading.

3. New interfaces: Scheduled sleep: nxsched_sleep() / nxsched_usleep() / nxsched_msleep() / nxsched_ticksleep()
Strengths:
a. Does not depend on the signal framework.
b. Tick-based, without additional computational overhead.

Currently, the Nuttx driver framework extensively uses nxsig_* interfaces. However, the driver does not need to rely on signals or timespec conversion.
Therefore, a new set of APIs is added to reduce dependencies on other modules.

(This PR also aims to make signals optional, further reducing the code size of Nuttx.)

Signed-off-by: chao an <anchao.archer@bytedance.com>
This commit is contained in:
chao an
2025-10-16 10:34:39 +08:00
committed by Xiang Xiao
parent 7297ecc02e
commit 87f134cfaa
273 changed files with 574 additions and 588 deletions
Download Patch File Download Diff File Expand all files Collapse all files
boards/arm/cxd56xx/common/src/cxd56_audio.c
+2 -2
View File
@@ -292,13 +292,13 @@ int board_external_amp_mute_control(bool en)
/* Mute ON */
ret = board_power_control(POWER_AUDIO_MUTE, false);
nxsig_usleep(MUTE_ON_DELAY);
nxsched_usleep(MUTE_ON_DELAY);
}
else
{
/* Mute OFF */
nxsig_usleep(MUTE_OFF_DELAY);
nxsched_usleep(MUTE_OFF_DELAY);
ret = board_power_control(POWER_AUDIO_MUTE, true);
}
boards/arm/cxd56xx/common/src/cxd56_bcm20706.c
+2 -2
View File
@@ -119,9 +119,9 @@ int board_bluetooth_uart_pin_cfg(void)
void board_bluetooth_reset(void)
{
cxd56_gpio_write(BCM20707_RST_N, false);
nxsig_usleep(BCM20707_RST_DELAY);
nxsched_usleep(BCM20707_RST_DELAY);
cxd56_gpio_write(BCM20707_RST_N, true);
nxsig_usleep(BCM20707_RST_DELAY);
nxsched_usleep(BCM20707_RST_DELAY);
}
/****************************************************************************
boards/arm/cxd56xx/common/src/cxd56_emmcdev.c
+1 -1
View File
@@ -78,7 +78,7 @@ int board_emmc_initialize(void)
{
/* Wait time until eMMC device is turned power on */
nxsig_usleep(EMMC_POWER_ON_WAIT_MSEC * USEC_PER_MSEC);
nxsched_usleep(EMMC_POWER_ON_WAIT_MSEC * USEC_PER_MSEC);
}
/* Initialize the eMMC device */
boards/arm/cxd56xx/common/src/cxd56_isx012.c
+6 -6
View File
@@ -91,7 +91,7 @@ int board_isx012_power_on(void)
{
/* Need to wait for a while after power-on */
nxsig_usleep(POWER_CHECK_TIME);
nxsched_usleep(POWER_CHECK_TIME);
if (true == board_power_monitor(POWER_IMAGE_SENSOR))
{
@@ -117,7 +117,7 @@ int board_isx012_power_off(void)
/* Need to wait for power-off to be reflected */
nxsig_usleep(POWER_OFF_TIME);
nxsched_usleep(POWER_OFF_TIME);
ret = -ETIMEDOUT;
for (i = 0; i < POWER_CHECK_RETRY; i++)
@@ -128,7 +128,7 @@ int board_isx012_power_off(void)
break;
}
nxsig_usleep(POWER_CHECK_TIME);
nxsched_usleep(POWER_CHECK_TIME);
}
return ret;
@@ -151,20 +151,20 @@ void board_isx012_set_sleep(int kind)
{
/* PowerON -> sleep */
nxsig_usleep(DEVICE_STARTUP_TIME);
nxsched_usleep(DEVICE_STARTUP_TIME);
}
else
{
/* active -> sleep */
nxsig_usleep(STANDBY_TIME);
nxsched_usleep(STANDBY_TIME);
}
}
void board_isx012_release_sleep(void)
{
cxd56_gpio_write(IMAGER_SLEEP, true);
nxsig_usleep(SLEEP_CANCEL_TIME);
nxsched_usleep(SLEEP_CANCEL_TIME);
}
int isx012_register(struct i2c_master_s *i2c);
boards/arm/cxd56xx/common/src/cxd56_isx019.c
+4 -4
View File
@@ -86,7 +86,7 @@ int board_isx019_power_on(void)
{
/* Need to wait for a while after power-on */
nxsig_usleep(POWER_CHECK_TIME);
nxsched_usleep(POWER_CHECK_TIME);
if (board_power_monitor(POWER_IMAGE_SENSOR))
{
@@ -112,7 +112,7 @@ int board_isx019_power_off(void)
/* Need to wait for power-off to be reflected */
nxsig_usleep(POWER_OFF_TIME);
nxsched_usleep(POWER_OFF_TIME);
ret = -ETIMEDOUT;
for (i = 0; i < POWER_CHECK_RETRY; i++)
@@ -123,7 +123,7 @@ int board_isx019_power_off(void)
break;
}
nxsig_usleep(POWER_CHECK_TIME);
nxsched_usleep(POWER_CHECK_TIME);
}
return ret;
@@ -153,7 +153,7 @@ struct i2c_master_s *board_isx019_initialize(void)
{
/* ISX019 requires stable RTC */
nxsig_usleep(100 * USEC_PER_MSEC);
nxsched_usleep(100 * USEC_PER_MSEC);
}
cxd56_gpio_config(IMAGER_RST, false);
boards/arm/cxd56xx/drivers/audio/cxd56_audio_analog.c
+1 -1
View File
@@ -81,7 +81,7 @@ static void wait_mic_boot_finish(void)
if (time < CXD56_AUDIO_MIC_BOOT_WAIT)
{
nxsig_usleep((CXD56_AUDIO_MIC_BOOT_WAIT - time) * 1000);
nxsched_usleep((CXD56_AUDIO_MIC_BOOT_WAIT - time) * 1000);
}
}
}
boards/arm/cxd56xx/drivers/audio/cxd56_audio_volume.c
+2 -2
View File
@@ -115,7 +115,7 @@ static CXD56_AUDIO_ECODE set_mute(cxd56_audio_volid_t id,
if (wait)
{
nxsig_usleep(waittime);
nxsched_usleep(waittime);
}
g_volparam[id].mute_bit |= type;
@@ -181,7 +181,7 @@ static CXD56_AUDIO_ECODE set_unmute(cxd56_audio_volid_t id,
if (wait)
{
nxsig_usleep(waittime);
nxsched_usleep(waittime);
}
}
boards/arm/cxd56xx/drivers/sensors/cxd5610_gnss.c
+1 -1
View File
@@ -1633,7 +1633,7 @@ static int cxd5610_gnss_finalize(struct cxd5610_gnss_dev_s *priv)
/* Finalize CXD5610 device */
cxd5610_gnss_core_finalize(priv);
nxsig_sleep(1);
nxsched_sleep(1);
/* Terminate thread */
boards/arm/cxd56xx/spresense/src/cxd56_power.c
+2 -2
View File
@@ -236,7 +236,7 @@ int board_power_control(int target, bool en)
if (!g_rtc_enabled && (PMIC_GET_TYPE(target) == PMIC_TYPE_GPO))
{
nxsig_usleep(1);
nxsched_usleep(1);
}
}
@@ -274,7 +274,7 @@ int board_power_control_tristate(int target, int value)
if (!g_rtc_enabled)
{
nxsig_usleep(1);
nxsched_usleep(1);
}
}
else if (PMIC_GET_TYPE(target) == CHIP_TYPE_GPIO)
boards/arm/lc823450/lc823450-xgevk/src/lc823450_bt.c
+2 -2
View File
@@ -56,9 +56,9 @@ void up_bt_enable(int enable)
if (enable)
{
lc823450_gpio_write(BT_POWER, 0);
nxsig_usleep(100 * 1000);
nxsched_usleep(100 * 1000);
lc823450_gpio_write(BT_POWER, 1);
nxsig_usleep(100 * 1000);
nxsched_usleep(100 * 1000);
}
else
{
boards/arm/lpc17xx_40xx/u-blox-c027/src/lpc17_40_ubxmdm.c
+3 -3
View File
@@ -268,7 +268,7 @@ static int lpc17_40_poweron(struct ubxmdm_lower * lower)
/* Min. time for power_on_n being low is 5 ms */
nxsig_usleep(10 * 1000);
nxsched_usleep(10 * 1000);
if (priv->usb_used)
{
@@ -287,7 +287,7 @@ static int lpc17_40_poweron(struct ubxmdm_lower * lower)
/* Delay to obtain correct voltage on shifters */
nxsig_usleep(1 * 1000);
nxsched_usleep(1 * 1000);
/* UART shifter enabled */
@@ -339,7 +339,7 @@ static int lpc17_40_reset(struct ubxmdm_lower * lower)
/* The minimum reset_n low time is 50 ms */
nxsig_usleep(75 * 1000);
nxsched_usleep(75 * 1000);
/* Modem not in reset */
boards/arm/nrf52/nrf52840-dk/src/nrf52_highpri.c
+1 -1
View File
@@ -257,7 +257,7 @@ int highpri_main(int argc, char *argv[])
/* Flush stdout and wait a bit */
fflush(stdout);
nxsig_sleep(1);
nxsched_sleep(1);
seconds++;
/* Sample counts so that they are not volatile. Missing a count now
boards/arm/nrf52/nrf52840-dk/src/nrf52_sx127x.c
+2 -2
View File
@@ -110,7 +110,7 @@ static void sx127x_chip_reset(void)
/* Wait 1 ms */
nxsig_usleep(1000);
nxsched_usleep(1000);
/* Configure reset as input */
@@ -118,7 +118,7 @@ static void sx127x_chip_reset(void)
/* Wait 10 ms */
nxsig_usleep(10000);
nxsched_usleep(10000);
}
/****************************************************************************
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c
+1 -1
View File
@@ -310,7 +310,7 @@ int s32k3xx_tja1153_initialize(int bus)
/* Sleep for 100 ms to ensure that CAN frames have been transmitted */
nxsig_usleep(100 * 1000);
nxsched_usleep(100 * 1000);
/* TJA1153 must be taken out of STB mode */
boards/arm/sam34/sam4s-xplained-pro/src/sam_wdt.c
+2 -2
View File
@@ -105,10 +105,10 @@ static int wdog_daemon(int argc, char *argv[])
goto errout_with_dev;
}
nxsig_usleep(200);
nxsched_usleep(200);
while (1)
{
nxsig_usleep((CONFIG_WDT_THREAD_INTERVAL)*1000);
nxsched_usleep((CONFIG_WDT_THREAD_INTERVAL)*1000);
wdinfo("ping\n");
ret = file_ioctl(&filestruct, WDIOC_KEEPALIVE, 0);
boards/arm/sama5/sama5d3-xplained/src/sam_bringup.c
+1 -1
View File
@@ -166,7 +166,7 @@ int sam_bringup(void)
{
/* Wait for mmc block driver to be registered. */
nxsig_sleep(1);
nxsched_sleep(1);
/* Mount the volume on HSMCI0 */
boards/arm/samv7/same70-qmtech/src/sam_bringup.c
+1 -1
View File
@@ -175,7 +175,7 @@ int sam_bringup(void)
{
if (sam_cardinserted(HSMCI0_SLOTNO))
{
nxsig_usleep(1000 * 1000);
nxsched_usleep(1000 * 1000);
/* Mount the volume on HSMCI0 */
boards/arm/samv7/same70-xplained/src/sam_bringup.c
+1 -1
View File
@@ -236,7 +236,7 @@ int sam_bringup(void)
{
if (sam_cardinserted(HSMCI0_SLOTNO))
{
nxsig_usleep(1000 * 1000);
nxsched_usleep(1000 * 1000);
/* Mount the volume on HSMCI0 */
boards/arm/samv7/samv71-xult/src/sam_bringup.c
+1 -1
View File
@@ -357,7 +357,7 @@ int sam_bringup(void)
{
if (sam_cardinserted(HSMCI0_SLOTNO))
{
nxsig_usleep(1000 * 1000);
nxsched_usleep(1000 * 1000);
/* Mount the volume on HSMCI0 */
boards/arm/stm32/axoloti/src/stm32_extmem.c
+1 -1
View File
@@ -237,7 +237,7 @@ int stm32_sdram_initialize(void)
* power-up).
*/
nxsig_usleep(1000);
nxsched_usleep(1000);
/* Step 5:
* Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1
boards/arm/stm32/clicker2-stm32/src/stm32_appinit.c
+1 -1
View File
@@ -96,7 +96,7 @@ int board_app_initialize(uintptr_t arg)
* bringing up file syslog.
*/
nxsig_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000);
nxsched_usleep(CONFIG_CLICKER2_STM32_SYSLOG_FILE_DELAY * 1000);
syslog_channel_t *channel;
channel = syslog_file_channel(CONFIG_CLICKER2_STM32_SYSLOG_FILE_PATH);
boards/arm/stm32/cloudctrl/src/stm32_relays.c
+2 -2
View File
@@ -231,11 +231,11 @@ void relays_onoff(int relays, uint32_t mdelay)
if (relays_getstat(relays))
{
relays_setstat(relays, false);
nxsig_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000);
nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000);
}
relays_setstat(relays, true);
nxsig_usleep(mdelay * 100 * 1000);
nxsched_usleep(mdelay * 100 * 1000);
relays_setstat(relays, false);
}
}
boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c
+3 -3
View File
@@ -490,7 +490,7 @@ int highpri_main(int argc, char *argv[])
adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0);
nxsig_usleep(100);
nxsched_usleep(100);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
@@ -498,7 +498,7 @@ int highpri_main(int argc, char *argv[])
adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0);
nxsig_usleep(100);
nxsched_usleep(100);
#endif
/* Lock global data */
@@ -534,7 +534,7 @@ int highpri_main(int argc, char *argv[])
g_highpri.lock = false;
nxsig_sleep(1);
nxsched_sleep(1);
}
errout:
boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c
+3 -3
View File
@@ -532,7 +532,7 @@ int highpri_main(int argc, char *argv[])
adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0);
nxsig_usleep(100);
nxsched_usleep(100);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
@@ -540,7 +540,7 @@ int highpri_main(int argc, char *argv[])
adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0);
nxsig_usleep(100);
nxsched_usleep(100);
#endif
/* Lock global data */
@@ -576,7 +576,7 @@ int highpri_main(int argc, char *argv[])
g_highpri.lock = false;
nxsig_sleep(1);
nxsched_sleep(1);
}
errout:
boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c
+1 -1
View File
@@ -1034,7 +1034,7 @@ int spwm_main(int argc, char *argv[])
/* Sleep */
nxsig_sleep(1);
nxsched_sleep(1);
}
errout:
boards/arm/stm32/photon/src/stm32_wdt.c
+1 -1
View File
@@ -75,7 +75,7 @@ static int wdog_daemon(int argc, char *argv[])
while (1)
{
nxsig_usleep((CONFIG_PHOTON_WDG_THREAD_INTERVAL)*1000);
nxsched_usleep((CONFIG_PHOTON_WDG_THREAD_INTERVAL)*1000);
/* Send keep alive ioctl */
boards/arm/stm32/shenzhou/src/stm32_relays.c
+2 -2
View File
@@ -231,11 +231,11 @@ void relays_onoff(int relays, uint32_t mdelay)
if (relays_getstat(relays))
{
relays_setstat(relays, false);
nxsig_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000);
nxsched_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000);
}
relays_setstat(relays, true);
nxsig_usleep(mdelay * 100 * 1000);
nxsched_usleep(mdelay * 100 * 1000);
relays_setstat(relays, false);
}
}
boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c
+1 -1
View File
@@ -98,7 +98,7 @@ static void *stm32_cd_thread(void *arg)
* rest for a millisecond or so.
*/
nxsig_usleep(1 * 1000);
nxsched_usleep(1 * 1000);
g_chmediaclbk(g_chmediaarg);
}
}
boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c
+1 -1
View File
@@ -113,7 +113,7 @@ static int stm32_i2c_power_reset(struct hyt271_bus_s *bus)
}
stm32_gpiowrite(BOARD_HYT271_POWOUT, false);
nxsig_usleep(250000);
nxsched_usleep(250000);
stm32_gpiowrite(BOARD_HYT271_POWOUT, true);
while (1)
boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c
+3 -3
View File
@@ -481,7 +481,7 @@ int highpri_main(int argc, char *argv[])
adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_REG, 0);
nxsig_usleep(100);
nxsched_usleep(100);
#endif
#ifdef HIGHPRI_HAVE_INJECTED
@@ -489,7 +489,7 @@ int highpri_main(int argc, char *argv[])
adc1->ad_ops->ao_ioctl(adc1, IO_TRIGGER_INJ, 0);
nxsig_usleep(100);
nxsched_usleep(100);
#endif
/* Lock global data */
@@ -525,7 +525,7 @@ int highpri_main(int argc, char *argv[])
g_highpri.lock = false;
nxsig_sleep(1);
nxsched_sleep(1);
}
errout:
boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c
+2 -2
View File
@@ -113,7 +113,7 @@ static void sx127x_chip_reset(void)
/* Wait 1 ms */
nxsig_usleep(1000);
nxsched_usleep(1000);
/* Configure reset as input */
@@ -121,7 +121,7 @@ static void sx127x_chip_reset(void)
/* Wait 10 ms */
nxsig_usleep(10000);
nxsched_usleep(10000);
}
/****************************************************************************
boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c
+1 -1
View File
@@ -225,7 +225,7 @@ int highpri_main(int argc, char *argv[])
/* Flush stdout and wait a bit */
fflush(stdout);
nxsig_sleep(1);
nxsched_sleep(1);
seconds++;
/* Sample counts so that they are not volatile. Missing a count now
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c
+2 -2
View File
@@ -114,7 +114,7 @@ static void sx127x_chip_reset(void)
/* Wait 1 ms */
nxsig_usleep(1000);
nxsched_usleep(1000);
/* Configure reset as input */
@@ -122,7 +122,7 @@ static void sx127x_chip_reset(void)
/* Wait 10 ms */
nxsig_usleep(10000);
nxsched_usleep(10000);
}
/****************************************************************************
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c
+2 -2
View File
@@ -112,7 +112,7 @@ static void sx127x_chip_reset(void)
/* Wait 1 ms */
nxsig_usleep(1000);
nxsched_usleep(1000);
/* Configure reset as input */
@@ -120,7 +120,7 @@ static void sx127x_chip_reset(void)
/* Wait 10 ms */
nxsig_usleep(10000);
nxsched_usleep(10000);
}
/****************************************************************************
boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c
+2 -2
View File
@@ -112,7 +112,7 @@ static void sx127x_chip_reset(void)
/* Wait 1 ms */
nxsig_usleep(1000);
nxsched_usleep(1000);
/* Configure reset as input */
@@ -120,7 +120,7 @@ static void sx127x_chip_reset(void)
/* Wait 10 ms */
nxsig_usleep(10000);
nxsched_usleep(10000);
}
/****************************************************************************
boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c
+1 -1
View File
@@ -135,7 +135,7 @@ static int stm32l4_reset(const struct spirit_lower_s *lower)
/* Wait minimum 1.5 ms to allow Spirit a proper boot-up sequence */
nxsig_usleep(1500);
nxsched_usleep(1500);
return OK;
}
boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c
+1 -1
View File
@@ -277,7 +277,7 @@ int dac_wgen_main(int argc, char *argv[])
/* Sleep */
nxsig_sleep(1);
nxsched_sleep(1);
}
errout:
boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c
+1 -1
View File
@@ -630,7 +630,7 @@ int spwm_main(int argc, char *argv[])
/* Sleep */
nxsig_sleep(1);
nxsched_sleep(1);
}
errout: