diff --git a/arch/arm/src/imx6/Kconfig b/arch/arm/src/imx6/Kconfig
index 172ef502a78..f4c53b79891 100644
--- a/arch/arm/src/imx6/Kconfig
+++ b/arch/arm/src/imx6/Kconfig
@@ -80,4 +80,31 @@ config IMX6_SPI2
 	select SPI
 
 endmenu # iMX Peripheral Selection
+
+choice
+	prompt "i.MX6 Boot Configuration"
+	default IMX6_BOOT_SDRAM
+	---help---
+		The startup code needs to know if the code is running from internal SRAM,
+		external SRAM, or CS0-3 in order to initialize properly.  Note that the
+		boot device is not specified for cases where the code is copied into
+		RAM.
+
+config IMX6_BOOT_OCRAM
+	bool "Running from internal OCRAM"
+	select BOOT_RUNFROMISRAM
+
+config IMX6_BOOT_SDRAM
+	bool "Running from external SDRAM"
+	select BOOT_RUNFROMSDRAM
+
+config IMX6_BOOT_NOR
+	bool "Running from external NOR FLASH"
+	select BOOT_RUNFROMFLASH
+
+config IMX6_BOOT_SRAM
+	bool "Running from external SRAM"
+	select BOOT_RUNFROMEXTSRAM
+
+endchoice # i.MX6 Boot Configuration
 endif # ARCH_CHIP_IMX6
diff --git a/arch/arm/src/imx6/chip/imx_ccm.h b/arch/arm/src/imx6/chip/imx_ccm.h
index d0b1a3b7f91..73faa18365e 100644
--- a/arch/arm/src/imx6/chip/imx_ccm.h
+++ b/arch/arm/src/imx6/chip/imx_ccm.h
@@ -200,7 +200,7 @@
 #define CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK             (3 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT)
 #  define CCM_CBCMR_GPU3D_CORE_CLK_SEL_MMDC_CH0       (0 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from mmdc_ch0 */
 #  define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL3_SWCLK     (1 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
-#  efine CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL2_PFD1       (2 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD1 */
+#  define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL2_PFD1      (2 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD1 */
 #  define CCM_CBCMR_GPU3D_CORE_CLK_SEL_PLL2_PFD2      (3 << CCM_CBCMR_GPU3D_CORE_CLK_SEL_SHIFT) /* Derive clock from PLL2 PFD2 */
 #define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT          (8)       /* Bits 8-9: Selector for gpu3d_shader clock multiplexer */
 #define CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK           (3 << CCM_CBCMR_GPU3D_SHADER_CLK_SEL_SHIFT)
@@ -415,8 +415,8 @@
 #define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT        (20)       /* Bits 20-21: Selector for spdif0 clock multiplexer */
 #define CCM_CDCDR_SPDIF0_CLK_SEL_MASK         (3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)
 #  define CCM_CDCDR_SPDIF0_CLK_SEL_DIV_PLL4   (0 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL4 divided clock */
-#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3 PFD2  (1 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */
-#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3 PFD3  (2 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD2  (1 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD2 */
+#  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_PFD3  (2 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from PLL3 PFD3 */
 #  define CCM_CDCDR_SPDIF0_CLK_SEL_PLL3_SWCLK (3 << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT) /* Derive clock from pll3_sw_clk */
 #define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT       (22)       /* Bits 22-24: Divider for spdif0 clock podf */
 #define CCM_CDCDR_SPDIF0_CLK_PODF_MASK        (7 << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)
@@ -437,7 +437,7 @@
 #  define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI0_CLK    (1 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ipp_di0_clk */
 #  define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI1_CLK    (2 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ipp_di1_clk */
 #  define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI0_CLK    (3 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */
-#  define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI0_CLK    (4 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di0_clk */
+#  define CCM_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI1_CLK    (4 << CCM_CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT) /* Derive clock from ldb_di1_clk */
 #define CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT               (3)       /* Bits 3-5: Divider for ipu1_di0 clock divider */
 #define CCM_CHSCCDR_IPU1_DI0_PODF_MASK                (7 << CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT)
 #  define CCM_CHSCCDR_IPU1_DI0_PODF(n)                ((uint32_t)(n) << CCM_CHSCCDR_IPU1_DI0_PODF_SHIFT) /* n=(divisor-1) */
diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h
index 4bea9165928..b26f3e8f07c 100644
--- a/arch/arm/src/imx6/chip/imx_memorymap.h
+++ b/arch/arm/src/imx6/chip/imx_memorymap.h
@@ -720,7 +720,7 @@
  * must have a separate mapping for the non-contiguous RAM region.
  */
 
-#ifdef CONFIG_BOOT_RUNFROMFLASH
+#ifdef CONFIG_IMX6_BOOT_NOR
 
 /* Some sanity checks.  If we are running from FLASH, then one of the
  * external chip selects must be configured to boot from NOR flash.
@@ -732,7 +732,7 @@
 #      error EIM FLASH size disagreement
 #    endif
 #  else
-#    error CONFIG_BOOT_RUNFROMFLASH=y, but no bootable NOR flash defined
+#    error CONFIG_IMX6_BOOT_NOR=y, but no bootable NOR flash defined
 #  endif
 
   /* Set up the NOR FLASH region as the NUTTX .text region */
@@ -749,7 +749,8 @@
 #  define NUTTX_RAM_PEND         ((CONFIG_RAM_END + 0x000fffff) & 0xfff00000)
 #  define NUTTX_RAM_SIZE         (NUTTX_RAM_PEND - NUTTX_RAM_PADDR)
 
-#else /* CONFIG_BOOT_RUNFROMFLASH */
+#else /* CONFIG_IMX6_BOOT_NOR */
+  /* Must be CONFIG_IMX6_BOOT_OCRAM || CONFIG_IMX6_BOOT_SDRAM || CONFIG_IMX6_BOOT_SRAM */
 
   /* Otherwise we are running from some kind of RAM (OCRAM, SRAM, or SDRAM).
    * Setup the RAM region as the NUTTX .txt, .bss, and .data region.
@@ -760,7 +761,7 @@
 #  define NUTTX_TEXT_PEND        ((CONFIG_RAM_END + 0x000fffff) & 0xfff00000)
 #  define NUTTX_TEXT_SIZE        (NUTTX_TEXT_PEND - NUTTX_TEXT_PADDR)
 
-#endif /* CONFIG_BOOT_RUNFROMFLASH */
+#endif /* CONFIG_IMX6_BOOT_NOR */
 
 /* MMU Page Table Location
  *
diff --git a/arch/arm/src/imx6/imx_clockconfig.c b/arch/arm/src/imx6/imx_clockconfig.c
index fa428342072..a4d6b9a433e 100644
--- a/arch/arm/src/imx6/imx_clockconfig.c
+++ b/arch/arm/src/imx6/imx_clockconfig.c
@@ -39,6 +39,8 @@
 
 #include <nuttx/config.h>
 
+#include "up_arch.h"
+#include "chip/imx_ccm.h"
 #include "imx_config.h"
 #include "imx_clockconfig.h"
 
@@ -58,16 +60,22 @@
 
 void imx_clockconfig(void)
 {
+  uint32_t regval;
+
   /* Don't change the current basic clock configuration if we are running
    * from SDRAM.  In this case, some bootloader logic has already configured
    * clocking and SDRAM.  We are pretty much committed to using things the
    * way that the bootloader has left them.
    */
 
-#ifndef CONFIG_IMX_BOOT_SDRAM
+#ifndef CONFIG_IMX6_BOOT_SDRAM
 #  warning Missing logic
 #endif
 
   /* Make certain that the ipg_clk is enabled */
-#warning Missing logic
+
+  regval  = getreg32(IMX_CCM_CCGR5);
+  regval &= (CCM_CCGR5_CG12_MASK);
+  regval |= CCM_CCGR5_CG12(CCM_CCGR_ALLMODES);
+  putreg32(regval, IMX_CCM_CCGR5);
 }
diff --git a/arch/arm/src/imx6/imx_lowputc.c b/arch/arm/src/imx6/imx_lowputc.c
index 09e036d227a..bfc8c3704a5 100644
--- a/arch/arm/src/imx6/imx_lowputc.c
+++ b/arch/arm/src/imx6/imx_lowputc.c
@@ -46,6 +46,7 @@
 
 #include "chip/imx_iomuxc.h"
 #include "chip/imx_pinmux.h"
+#include "chip/imx_ccm.h"
 #include "chip/imx_uart.h"
 #include "imx_config.h"
 #include "imx_gpio.h"
@@ -107,7 +108,7 @@
  * characters.This clock is used in order to allow frequency scaling on
  * peripheral_clock without changing configuration of baud rate.
  *
- * The default ipg_perclk is 80MHz (max 80MHz).  ipg_clk is gated by
+ * The default ipg_perclk is 80MHz (max 80MHz).  ipg_perclk is gated by
  * CCGR5[CG13], uart_serial_clk_enable.  The clock generation sequence is:
  *
  *   pll3_sw_clk (480M) -> CCGR5[CG13] -> 3 bit divider cg podf=6 ->
@@ -157,10 +158,17 @@ static const struct uart_config_s g_console_config =
 void imx_lowsetup(void)
 {
 #ifdef IMX_HAVE_UART
+  uint32_t regval;
+
   /* Make certain that the ipg_perclk is enabled.  The ipg_clk should already
-   * have been enabled.
+   * have been enabled.  Here we set BOTH the ipg_clk and ipg_perclk so that
+   * clocking is on in all modes (except STOP).
    */
-#warning Missing logic
+
+  regval  = getreg32(IMX_CCM_CCGR5);
+  regval &= (CCM_CCGR5_CG12_MASK | CCM_CCGR5_CG13_MASK);
+  regval |= (CCM_CCGR5_CG12(CCM_CCGR_ALLMODES) | CCM_CCGR5_CG13(CCM_CCGR_ALLMODES));
+  putreg32(regval, IMX_CCM_CCGR5);
 
 #ifdef CONFIG_IMX6_UART1
   /* Disable and configure UART1 */
diff --git a/arch/arm/src/imx6/imx_memorymap.h b/arch/arm/src/imx6/imx_memorymap.h
index 7cab296d16a..6259c1b7e01 100644
--- a/arch/arm/src/imx6/imx_memorymap.h
+++ b/arch/arm/src/imx6/imx_memorymap.h
@@ -78,7 +78,7 @@
  */
 
 #undef NEED_SDRAM_CONFIGURATION
-#if defined(CONFIG_IMX6_MMDC) && !defined(CONFIG_IMX_BOOT_SDRAM)
+#if defined(CONFIG_IMX6_MMDC) && !defined(CONFIG_IMX6_BOOT_SDRAM)
 #  define NEED_SDRAM_CONFIGURATION 1
 #endif