diff --git a/arch/arm/src/max326xx/Kconfig b/arch/arm/src/max326xx/Kconfig index 58e48ba0abe..1bbe0ffb07b 100644 --- a/arch/arm/src/max326xx/Kconfig +++ b/arch/arm/src/max326xx/Kconfig @@ -201,6 +201,10 @@ config MAX326XX_HAVE_SPIM bool default n +config MAX326XX_HAVE_UART + bool + default n + # Peripheral Driver Selections config MAX326XX_WDOG @@ -348,16 +352,19 @@ config MAX326XX_I2CS1 config MAX326XX_UART0 bool "UART 0" default n + select MAX326XX_HAVE_UART select UART0_SERIALDRIVER config MAX326XX_UART1 bool "UART 1" default n + select MAX326XX_HAVE_UART select UART1_SERIALDRIVER config MAX326XX_UART2 bool "UART 2" default n + select MAX326XX_HAVE_UART select UART2_SERIALDRIVER depends on MAX326XX_HAVE_UART2 diff --git a/arch/arm/src/max326xx/Make.defs b/arch/arm/src/max326xx/Make.defs index 655152d67f5..fd2787b0d7c 100644 --- a/arch/arm/src/max326xx/Make.defs +++ b/arch/arm/src/max326xx/Make.defs @@ -33,6 +33,8 @@ # ############################################################################ +# Common ARMv7-M Source Files + HEAD_ASRC = CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S @@ -75,9 +77,21 @@ CMN_ASRCS += up_fpu.S CMN_CSRCS += up_copyarmstate.c endif +# Common MAX326XX Source Files + CHIP_ASRCS = CHIP_CSRCS = max326_start.c max326_clockconfig.c max326_irq.c max326_clrpend.c -CHIP_CSRCS += max326_allocateheap.c max326_lowputc.c max326_gpio.c +CHIP_CSRCS += max326_allocateheap.c + +# Source Files for the MAX32620 and MAX32630 + +# Source Files for the MAX32660 + +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) +CHIP_CSRCS += max32660_lowputc.c max32660_gpio.c +endif + +# Configuration-Dependent Source Files ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += max326_timerisr.c @@ -90,7 +104,9 @@ CHIP_CSRCS += max326_userspace.c max326_mpuinit.c endif ifeq ($(CONFIG_MAX326_DMA),y) -CHIP_CSRCS += max326_dma.c +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) +CHIP_CSRCS += max32660_dma.c +endif endif ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) @@ -98,32 +114,42 @@ CHIP_CSRCS += max326_idle.c endif ifeq ($(CONFIG_MAX326_GPIOIRQ),y) -CHIP_CSRCS += max326_gpioirq.c +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) +CHIP_CSRCS += max32660_gpioirq.c +endif endif ifeq ($(CONFIG_RTC),y) -CHIP_CSRCS += max326_rtc.c +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) +CHIP_CSRCS += max32660_rtc.c +endif ifeq ($(CONFIG_RTC_DRIVER),y) CHIP_CSRCS += max326_rtc_lowerhalf.c endif endif ifeq ($(CONFIG_MAX326_WDT),y) -CHIP_CSRCS += max326_wdt.c +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) +CHIP_CSRCS += max32660_wdt.c +endif endif ifeq ($(CONFIG_MAX326_RNG),y) CHIP_CSRCS += max326_rng.c endif -ifeq ($(CONFIG_MAX326_HAVE_USART),y) -CHIP_CSRCS += max326_serial.c +ifeq ($(CONFIG_MAX326XX_HAVE_UART),y) +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) +CHIP_CSRCS += max32660_serial.c +endif endif ifeq ($(CONFIG_MAX326XX_HAVE_I2CM),y) -CHIP_CSRCS += max326_i2c_master.c +ifeq ($(CONFIG_ARCH_FAMILY_MAX32660),y) +CHIP_CSRCS += max32660_i2cm.c +endif endif ifeq ($(CONFIG_MAX326XX_HAVE_SPIM),y) -CHIP_CSRCS += max326_spi_master.c +CHIP_CSRCS += max326_spim.c endif diff --git a/arch/arm/src/max326xx/chip/max32660_i2c.h b/arch/arm/src/max326xx/chip/max32660_i2c.h new file mode 100644 index 00000000000..2da782b7700 --- /dev/null +++ b/arch/arm/src/max326xx/chip/max32660_i2c.h @@ -0,0 +1,301 @@ +/************************************************************************************ + * arch/arm/src/max326xx/chip/max326_i2c.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_I2C_H +#define __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_I2C_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/max326_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define MAX326_I2C_CTRL0_OFFSET 0x0000 /* I2C Control 0 Register */ +#define MAX326_I2C_STATUS_OFFSET 0x0004 /* I2C Status Register */ +#define MAX326_I2C_INTFL0_OFFSET 0x0008 /* I2C Interrupt Flags 0 Register */ +#define MAX326_I2C_INTEN0_OFFSET 0x000c /* I2C Interrupt Enable 0 Register */ +#define MAX326_I2C_INTFL1_OFFSET 0x0010 /* I2C Interrupts Flags 1 Register */ +#define MAX326_I2C_INTEN1_OFFSET 0x0014 /* I2C Interrupts Enable 1 Register */ +#define MAX326_I2C_FIFOLEN_OFFSET 0x0018 /* I2C FIFO Length Register */ +#define MAX326_I2C_RXCTRL0_OFFSET 0x001c /* I2C Receive Control 0 Register */ +#define MAX326_I2C_RXCTRL1_OFFSET 0x0020 /* I2C Receive Control 1 Register 1 */ +#define MAX326_I2C_TXCTRL0_OFFSET 0x0024 /* I2C Transmit Control 0 Register 0 */ +#define MAX326_I2C_TXCTRL1_OFFSET 0x0028 /* I2C Transmit Control 1 Register 1 */ +#define MAX326_I2C_FIFO_OFFSET 0x002c /* I2C Transmit and Receive FIFO Register */ +#define MAX326_I2C_MSTRMODE_OFFSET 0x0030 /* I2C Master Mode Register */ +#define MAX326_I2C_CLKLO_OFFSET 0x0034 /* I2C Clock Low Time Register */ +#define MAX326_I2C_CLKHI_OFFSET 0x0038 /* I2C Clock High Time Register */ +#define MAX326_I2C_HSCLK_OFFSET 0x003c /* I2C Hs-Mode Clock Control Register */ +#define MAX326_I2C_TIMEOUT_OFFSET 0x0040 /* I2C Timeout Register */ +#define MAX326_I2C_SLADDR_OFFSET 0x0044 /* I2C Slave Address Register */ +#define MAX326_I2C_DMA_OFFSET 0x0048 /* I2C DMA Enable Register */ + +/* Register Addresses ***************************************************************/ + +#define MAX326_I2C0_CTRL0 (MAX326_I2C0_BASE + MAX326_I2C_CTRL0_OFFSET) +#define MAX326_I2C0_STATUS (MAX326_I2C0_BASE + MAX326_I2C_STATUS_OFFSET) +#define MAX326_I2C0_INTFL0 (MAX326_I2C0_BASE + MAX326_I2C_INTFL0_OFFSET) +#define MAX326_I2C0_INTEN0 (MAX326_I2C0_BASE + MAX326_I2C_INTEN0_OFFSET) +#define MAX326_I2C0_INTFL1 (MAX326_I2C0_BASE + MAX326_I2C_INTFL1_OFFSET) +#define MAX326_I2C0_INTEN1 (MAX326_I2C0_BASE + MAX326_I2C_INTEN1_OFFSET) +#define MAX326_I2C0_FIFOLEN (MAX326_I2C0_BASE + MAX326_I2C_FIFOLEN_OFFSET) +#define MAX326_I2C0_RXCTRL0 (MAX326_I2C0_BASE + MAX326_I2C_RXCTRL0_OFFSET) +#define MAX326_I2C0_RXCTRL1 (MAX326_I2C0_BASE + MAX326_I2C_RXCTRL1_OFFSET) +#define MAX326_I2C0_TXCTRL0 (MAX326_I2C0_BASE + MAX326_I2C_TXCTRL0_OFFSET) +#define MAX326_I2C0_TXCTRL1 (MAX326_I2C0_BASE + MAX326_I2C_TXCTRL1_OFFSET) +#define MAX326_I2C0_FIFO (MAX326_I2C0_BASE + MAX326_I2C_FIFO_OFFSET) +#define MAX326_I2C0_MSTRMODE (MAX326_I2C0_BASE + MAX326_I2C_MSTRMODE_OFFSET) +#define MAX326_I2C0_CLKLO (MAX326_I2C0_BASE + MAX326_I2C_CLKLO_OFFSET) +#define MAX326_I2C0_CLKHI (MAX326_I2C0_BASE + MAX326_I2C_CLKHI_OFFSET) +#define MAX326_I2C0_HSCLK (MAX326_I2C0_BASE + MAX326_I2C_HSCLK_OFFSET) +#define MAX326_I2C0_TIMEOUT (MAX326_I2C0_BASE + MAX326_I2C_TIMEOUT_OFFSET) +#define MAX326_I2C0_SLADDR (MAX326_I2C0_BASE + MAX326_I2C_SLADDR_OFFSET) +#define MAX326_I2C0_DMA (MAX326_I2C0_BASE + MAX326_I2C_DMA_OFFSET) + +#define MAX326_I2C1_CTRL0 (MAX326_I2C1_BASE + MAX326_I2C_CTRL0_OFFSET) +#define MAX326_I2C1_STATUS (MAX326_I2C1_BASE + MAX326_I2C_STATUS_OFFSET) +#define MAX326_I2C1_INTFL0 (MAX326_I2C1_BASE + MAX326_I2C_INTFL0_OFFSET) +#define MAX326_I2C1_INTEN0 (MAX326_I2C1_BASE + MAX326_I2C_INTEN0_OFFSET) +#define MAX326_I2C1_INTFL1 (MAX326_I2C1_BASE + MAX326_I2C_INTFL1_OFFSET) +#define MAX326_I2C1_INTEN1 (MAX326_I2C1_BASE + MAX326_I2C_INTEN1_OFFSET) +#define MAX326_I2C1_FIFOLEN (MAX326_I2C1_BASE + MAX326_I2C_FIFOLEN_OFFSET) +#define MAX326_I2C1_RXCTRL0 (MAX326_I2C1_BASE + MAX326_I2C_RXCTRL0_OFFSET) +#define MAX326_I2C1_RXCTRL1 (MAX326_I2C1_BASE + MAX326_I2C_RXCTRL1_OFFSET) +#define MAX326_I2C1_TXCTRL0 (MAX326_I2C1_BASE + MAX326_I2C_TXCTRL0_OFFSET) +#define MAX326_I2C1_TXCTRL1 (MAX326_I2C1_BASE + MAX326_I2C_TXCTRL1_OFFSET) +#define MAX326_I2C1_FIFO (MAX326_I2C1_BASE + MAX326_I2C_FIFO_OFFSET) +#define MAX326_I2C1_MSTRMODE (MAX326_I2C1_BASE + MAX326_I2C_MSTRMODE_OFFSET) +#define MAX326_I2C1_CLKLO (MAX326_I2C1_BASE + MAX326_I2C_CLKLO_OFFSET) +#define MAX326_I2C1_CLKHI (MAX326_I2C1_BASE + MAX326_I2C_CLKHI_OFFSET) +#define MAX326_I2C1_HSCLK (MAX326_I2C1_BASE + MAX326_I2C_HSCLK_OFFSET) +#define MAX326_I2C1_TIMEOUT (MAX326_I2C1_BASE + MAX326_I2C_TIMEOUT_OFFSET) +#define MAX326_I2C1_SLADDR (MAX326_I2C1_BASE + MAX326_I2C_SLADDR_OFFSET) +#define MAX326_I2C1_DMA (MAX326_I2C1_BASE + MAX326_I2C_DMA_OFFSET) + +/* Register Bit-field Definitions ***************************************************/ + +/* I2C Control 0 Register */ + +#define I2C_CTRL0_I2CEN (1 << 0) /* Bit 0: I2C Enable */ +#define I2C_CTRL0_MST (1 << 1) /* Bit 1: Master Mode Enable */ +#define I2C_CTRL0_GCEN (1 << 2) /* Bit 2: General Call Address Enable */ +#define I2C_CTRL0_IRXM (1 << 3) /* Bit 3: Interactive Receive Mode (IRXM) */ +#define I2C_CTRL0_ACK (1 << 4) /* Bit 4: Interactive Receive Mode (IRXM) + * Acknowledge */ +#define I2C_CTRL0_SCLO (1 << 6) /* Bit 6: SCL Pin Control */ +#define I2C_CTRL0_SDAO (1 << 7) /* Bit 7: SDA Pin Control */ +#define I2C_CTRL0_SCL (1 << 8) /* Bit 8: SCL Status */ +#define I2C_CTRL0_SDA (1 << 9) /* Bit 9: SDA Status */ +#define I2C_CTRL0_SWOE (1 << 10) /* Bit 10: Software output Enabled */ +#define I2C_CTRL0_READ (1 << 11) /* Bit 11: Read/Write Bit Status */ +#define I2C_CTRL0_SCLSTRD (1 << 12) /* Bit 12: SCL Clock Stretch Control */ +#define I2C_CTRL0_SCLPPM (1 << 13) /* Bit 13: SCL Push-Pull Mode Enable */ +#define I2C_CTRL0_HSMODE (1 << 15) /* Bit 15: High Speed Mode */ + +/* I2C Status Register */ + +#define I2C_STATUS_BUSY (1 << 0) /* Bit 0: Bus Busy */ +#define I2C_STATUS_RXE (1 << 1) /* Bit 1: RX FIFO Empty */ +#define I2C_STATUS_RXF (1 << 2) /* Bit 2: RX FIFO Full */ +#define I2C_STATUS_TXE (1 << 3) /* Bit 3: TX FIFO Empty */ +#define I2C_STATUS_TXF (1 << 4) /* Bit 4: TX FIFO Full */ +#define I2C_STATUS_CKMD (1 << 5) /* Bit 5: SCL Drive Status */ +#define I2C_STATUS_STAT_SHIFT (8) /* Bits 8-11: I2C Controller Status */ +#define I2C_STATUS_STAT_MASK (15 << I2C_STATUS_STAT_SHIFT) + +# define I2C_STATUS_STAT_IDLE (0 << I2C_STATUS_STAT_SHIFT) /* Idle */ +# define I2C_STATUS_STAT_MTXADDR (1 << I2C_STATUS_STAT_SHIFT) /* Master Transmit + * address */ +# define I2C_STATUS_STAT_MRXACK (2 << I2C_STATUS_STAT_SHIFT) /* Master Receive + * address ACK */ +# define I2C_STATUS_STAT_MTXEXTADDR (3 << I2C_STATUS_STAT_SHIFT) /* Master Transmit + * extended address */ +# define I2C_STATUS_STAT_MRXEXTACK (4 << I2C_STATUS_STAT_SHIFT) /* Master Receive + * extended address + * ACK */ +# define I2C_STATUS_STAT_SRXADDR (5 << I2C_STATUS_STAT_SHIFT) /* Slave Receive + * address */ +# define I2C_STATUS_STAT_STXRACK (6 << I2C_STATUS_STAT_SHIFT) /* Slave Transmit + * address ACK */ +# define I2C_STATUS_STAT_SRXEXTADDR (7 << I2C_STATUS_STAT_SHIFT) /* Slave Receive + * extended address */ +# define I2C_STATUS_STAT_STXEXTACK (8 << I2C_STATUS_STAT_SHIFT) /* Slave transit + * extended address + * ACK */ +# define I2C_STATUS_STAT_TXDATA (9 << I2C_STATUS_STAT_SHIFT) /* Transmit data + * (Master or Slave) */ +# define I2C_STATUS_STAT_RXACK (10 << I2C_STATUS_STAT_SHIFT) /* Receive data ACK + * (Master or Slave) */ +# define I2C_STATUS_STAT_RXDATA (11 << I2C_STATUS_STAT_SHIFT) /* Receive data + * (Master or Slave) */ +# define I2C_STATUS_STAT_TXACK (12 << I2C_STATUS_STAT_SHIFT) /* Transmit data ACK + * (Master or Slave) */ +# define I2C_STATUS_STAT_NACK (13 << I2C_STATUS_STAT_SHIFT) /* NACK stage (Master + * or Slave) */ +# define I2C_STATUS_STAT_MBUSY (15 << I2C_STATUS_STAT_SHIFT) /* Another master is + * addressing another + * slave. */ + +/* I2C Interrupt Flags 0 Register and I2C Interrupt Enable 0 Register */ + +#define I2C_INT0_DONEI (1 << 0) /* Bit 0: Transfer Complete Interrupt */ +#define I2C_INT0_IRXMI (1 << 1) /* Bit 1: Interactive Receive Mode + * Interrupt */ +#define I2C_INT0_GCI (1 << 2) /* Bit 2: General Call Address Match + * Received Interrupt (slave) */ +#define I2C_INT0_AMI (1 << 3) /* Bit 3: Address Match Status Interrupt + * (slave) */ +#define I2C_INT0_RXTHI (1 << 4) /* Bit 4: RX FIFO Threshold Level Interrupt */ +#define I2C_INT0_TXTHI (1 << 5) /* Bit 5: TX FIFO Threshold Level Interrupt */ +#define I2C_INT0_STOPI (1 << 6) /* Bit 6: Slave Mode: STOP Condition + * Interrupt (slave) */ +#define I2C_INT0_ADRACKI (1 << 7) /* Bit 7: Address ACK from External Slave + * Interrupt (master) */ +#define I2C_INT0_ARBERI (1 << 8) /* Bit 8: Arbitration Lost Interrupt + * (master) */ +#define I2C_INT0_TOERI (1 << 9) /* Bit 9: Timeout Error Interrupt */ +#define I2C_INT0_ADRERI (1 << 10) /* Bit 10: Address NACK from Slave Error + * (master) */ +#define I2C_INT0_DATERI (1 << 11) /* Bit 11: Data NACK from External Slave + * Interrupt (master) */ +#define I2C_INT0_DNRERI (1 << 12) /* Bit 12: Slave Mode Do Not Respond + * Interrupt */ +#define I2C_INT0_STRTERI (1 << 13) /* Bit 13: Out of Sequence START Interrupt */ +#define I2C_INT0_STOPERI (1 << 14) /* Bit 14: Out of Sequence STOP Interrupt */ +#define I2C_INT0_TXLOI (1 << 15) /* Bit 15: TX FIFO Locked Interrupt */ + +/* I2C Interrupts Flags 1 Register and I2C Interrupts Enable 1 Register */ + +#define I2C_INT1_RXOFI (1 << 0) /* Bit 0: RX FIFO Overflow Interrupt + * (slave) */ +#define I2C_INT1_TXUFI (1 << 1) /* Bit 1: TX FIFO Underflow Interrupt + * (slave) */ + +/* I2C FIFO Length Register */ + +#define I2C_FIFOLEN_RXLEN_SHIFT (0) /* Bits 0-7: RX FIFO Length */ +#define I2C_FIFOLEN_RXLEN_MASK (0xff << I2C_FIFOLEN_RXLEN_SHIFT) +#define I2C_FIFOLEN_TXLEN_SHIFT (8) /* Bits 8-15: TX FIFO Length */ +#define I2C_FIFOLEN_TXLEN_MASK (0xff << I2C_FIFOLEN_TXLEN_SHIFT) + +/* I2C Receive Control 0 Register */ + +#define I2C_RXCTRL0_DNR (1 << 0) /* Bit 0: Do Not Respond (slave) */ +#define I2C_RXCTRL0_RXFSH (1 << 7) /* Bit 7: Flush RX FIFO */ +#define I2C_RXCTRL0_RXTH_SHIFT (8) /* Bits 8-11: RX FIFO Threshold Level */ +#define I2C_RXCTRL0_RXTH_MASK (15 << I2C_RXCTRL0_RXTH_SHIFT) + +/* I2C Receive Control 1 Register 1 */ + +#define I2C_RXCTRL1_RXCNT_SHIFT (0) /* Bits 0-7: RX FIFO Transaction Byte Count */ +#define I2C_RXCTRL1_RXCNT_MASK (0xff << I2C_RXCTRL1_RXCNT_SHIFT) +# define I2C_RXCTRL1_RXCNT(n) ((uint16_t)((n) & 0xff) << I2C_RXCTRL1_RXFIFO_SHIFT) +#define I2C_RXCTRL1_RXFIFO_SHIFT (8) /* Bits 8-11: RX FIFO Byte Count */ +#define I2C_RXCTRL1_RXFIFO_MASK (15 << I2C_RXCTRL1_RXFIFO_SHIFT) + +/* I2C Transmit Control 0 Register 0 */ + +#define I2C_TXCTRL0_TXPRELD (1 << 0) /* Bit 0: TX FIFO Preload Mode Enable */ +#define I2C_TXCTRL0_TXFSH (1 << 7) /* Bit 7: Flush TX FIFO */ +#define I2C_TXCTRL0_TXTH_SHIFT (8) /* Bits 8-11: TX FIFO Threshold Level */ +#define I2C_TXCTRL0_TXTH_MASK (15 << I2C_TXCTRL0_TXTH_SHIFT) + +/* I2C Transmit Control 1 Register 1 */ + +#define I2C_TXCTRL1_TXRDY (1 << 0) /* Bit 0: Transmit FIFO Preload Ready + * Status */ +#define I2C_TXCTRL1_TXLAST (1 << 1) /* Bit 1: Transmit Last (slave) */ +#define I2C_TXCTRL1_FLSH_GCADDRDIS (1 << 2) /* Bit 2: TX FIFO Auto Flush Disable on + * General Call Address Match */ +#define I2C_TXCTRL1_FLSH_SLADDRDIS (1 << 4) /* Bit 4: TX FIFO Auto Flush Disable for + * Slave Address Match */ +#define I2C_TXCTRL1_FLSH_NACKDIS (1 << 5) /* Bit 5: TX FIFO Auto Flush Disable for + * NACK */ +#define I2C_TXCTRL1_TXFIFO_SHIFT (8) /* Bits 8-11: TX FIFO Byte Count */ +#define I2C_TXCTRL1_TXFIFO_MASK (15 << I2C_TXCTRL1_TXFIFO_SHIFT) + +/* I2C Transmit and Receive FIFO Register */ + +#define I2C_FIFO_MASK (0xff) /* Bits 0-7: I2C FIFO Data */ + +/* I2C Master Mode Register */ + +#define I2C_MSTRMODE_START (1 << 0) /* Bit 0: Start Master Mode Transfer */ +#define I2C_MSTRMODE_RESTART (1 << 1) /* Bit 1: Send Repeated START Condition */ +#define I2C_MSTRMODE_STOP (1 << 2) /* Bit 2: Send STOP Condition */ +#define I2C_MSTRMODE_SEA (1 << 7) /* Bit 7: Slave Extended Addressing */ + +/* I2C Clock Low Time Register */ + +#define I2C_CLKLO_MASK (0x1ff) /* Bits 0-8: Clock Low Time */ + +/* I2C Clock High Time Register */ + +#define I2C_CLKHI_MASK (0x1ff) /* Bits 0-8: Clock High Time */ + +/* I2C Hs-Mode Clock Control Register */ + +#define I2C_HSCLK_HSCLKLO_SHIFT (0) /* Bits 0-7: Hs-Mode Clock Low Time */ +#define I2C_HSCLK_HSCLKLO_MASK (0xff << I2C_HSCLK_HSCLKLO_SHIFT) +# define I2C_HSCLK_HSCLKLO(n) ((uint32_t)((n) - 1) << I2C_HSCLK_HSCLKLO_SHIFT) +#define I2C_HSCLK_HSCLKHI_SHIFT (8) /* Bits 8-15: Hs-Mode Clock High Time */ +#define I2C_HSCLK_HSCLKHI_MASK (0xff << I2C_HSCLK_HSCLKHI_SHIFT) +# define I2C_HSCLK_HSCLKHI(n) ((uint32_t)((n) - 1) << I2C_HSCLK_HSCLKHI_SHIFT) + +/* I2C Timeout Register */ + +#define I2C_TIMEOUT_MASK (0xffff) /* Bits 0-15: Bus Error SCL Timeout Period */ + +/* I2C Slave Address Register */ + +#define I2C_SLADDR_SLA_SHIFT (0) /* Bits 0-9: Slave Mode Slave Address */ +#define I2C_SLADDR_SLA_MASK (0x3ff << I2C_SLADDR_SLA_SHIFT) +# define I2C_SLADDR_SLA(n) ((uint32_t)(n) << I2C_SLADDR_SLA_SHIFT) +#define I2C_SLADDR_EA (1 << 15) /* Bit 15: Slave Mode Extended Address + * Select */ + +/* I2C DMA Enable Register */ + +#define I2C_DMA_TXEN (1 << 0) /* Bit 0: TX DMA Channel Enable */ +#define I2C_DMA_RXEN (1 << 1) /* Bit 1: RX DMA Channel Enable */ + +#endif /* __ARCH_ARM_SRC_MAX326XX_CHIP_MAX326_I2C_H */ diff --git a/arch/arm/src/max326xx/chip/max32660_memorymap.h b/arch/arm/src/max326xx/chip/max32660_memorymap.h index 8399f2e4ce3..6d9fc8ca5b1 100644 --- a/arch/arm/src/max326xx/chip/max32660_memorymap.h +++ b/arch/arm/src/max326xx/chip/max32660_memorymap.h @@ -69,19 +69,13 @@ #define MAX326_TMR2_BASE 0x40012000 /* TMR2 */ #define MAX326_SPIMSS_BASE 0x40019000 /* SPIMSS (I2S) */ #define MAX326_I2C0_BASE 0x4001d000 /* I2CM 0 Master/Slave */ -# define MAX326_I2CM0_BASE 0x4001d000 /* I2CM 0 Master */ -# define MAX326_I2CS0_BASE 0x4001d000 /* I2CS 0 Slave */ #define MAX326_I2C1_BASE 0x4001e000 /* I2CM 1 Master/Slave */ -# define MAX326_I2CM1_BASE 0x4001e000 /* I2CM 1 Master */ -# define MAX326_I2CS1_BASE 0x4001e000 /* I2CS 1 Slave */ #define MAX326_DMA_BASE 0x40028000 /* Standard DMA */ #define MAX326_FLC_BASE 0x40029000 /* FLASH Controller */ #define MAX326_ICC_BASE 0x4002a000 /* Internal Cache Controller */ #define MAX326_UART0_BASE 0x40042000 /* UART 0 */ #define MAX326_UART1_BASE 0x40043000 /* UART 1 */ #define MAX326_SPI0_BASE 0x40046000 /* SPIM 0 Master/Slave */ -# define MAX326_SPIM0_BASE 0x40046000 /* SPIM 0 Master */ -# define MAX326_SPIS0_BASE 0x40046000 /* SPIS 0 Slave */ /******************************************************************************************** * Public Types