arch:risc-v:bl602: enable FPU for this target.

arch/risc-v/Kconfig

@@ -47,6 +47,7 @@ config ARCH_CHIP_GAP8
 config ARCH_CHIP_BL602
 	bool "BouffaloLab BL602"
 	select ARCH_RV32IM
+	select ARCH_HAVE_FPU
 	select ARCH_HAVE_RESET
 	---help---
 		BouffaloLab BL602(rv32imfc)

arch/risc-v/include/csr.h

@@ -311,10 +311,13 @@
 
 /* In mstatus register */
 
-#define MSTATUS_MIE   (0x1 << 3)  /* Machine Interrupt Enable */
-#define MSTATUS_MPIE  (0x1 << 7)  /* Machine Previous Interrupt Enable */
-#define MSTATUS_MPPM  (0x3 << 11) /* Machine Previous Privilege (m-mode) */
-#define MSTATUS_FS    (0x3 << 13) /* Machine Floating-point Status */
+#define MSTATUS_MIE       (0x1 << 3)  /* Machine Interrupt Enable */
+#define MSTATUS_MPIE      (0x1 << 7)  /* Machine Previous Interrupt Enable */
+#define MSTATUS_MPPM      (0x3 << 11) /* Machine Previous Privilege (m-mode) */
+#define MSTATUS_FS        (0x3 << 13) /* Machine Floating-point Status */
+#define MSTATUS_FS_INIT   (0x1 << 13)
+#define MSTATUS_FS_CLEAN  (0x2 << 13)
+#define MSTATUS_FS_DIRTY  (0x3 << 13)
 
 /* In mie (machine interrupt enable) register */
 

arch/risc-v/src/bl602/Make.defs

@@ -38,6 +38,10 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
 CMN_CSRCS += riscv_checkstack.c
 endif
 
+ifeq ($(CONFIG_ARCH_FPU),y)
+CMN_ASRCS  += riscv_fpu.S
+endif
+
 ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
 CMN_CSRCS  += riscv_vfork.c
 endif

arch/risc-v/src/bl602/bl602_irq.c

@@ -184,7 +184,11 @@ uint32_t up_get_newintctx(void)
    * Also set machine previous interrupt enable
    */
 
+#ifdef CONFIG_ARCH_FPU
+  return (MSTATUS_FS_INIT | MSTATUS_MPPM | MSTATUS_MPIE);
+#else
   return (MSTATUS_MPPM | MSTATUS_MPIE);
+#endif
 }
 
 /****************************************************************************

arch/risc-v/src/bl602/bl602_irq_dispatch.c

@@ -90,8 +90,36 @@ void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs)
 
   irq_dispatch(irq, regs);
 
+#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
+  /* Check for a context switch.  If a context switch occurred, then
+   * g_current_regs will have a different value than it did on entry.  If an
+   * interrupt level context switch has occurred, then restore the floating
+   * point state and the establish the correct address environment before
+   * returning from the interrupt.
+   */
+
+  if (regs != g_current_regs)
+    {
+#ifdef CONFIG_ARCH_FPU
+      /* Restore floating point registers */
+
+      up_restorefpu((uint32_t *)g_current_regs);
 #endif
 
+#ifdef CONFIG_ARCH_ADDRENV
+      /* Make sure that the address environment for the previously
+       * running task is closed down gracefully (data caches dump,
+       * MMU flushed) and set up the address environment for the new
+       * thread at the head of the ready-to-run list.
+       */
+
+      group_addrenv(NULL);
+#endif
+    }
+#endif /* CONFIG_ARCH_FPU || CONFIG_ARCH_ADDRENV */
+
+#endif /* CONFIG_SUPPRESS_INTERRUPTS */
+
   /* If a context switch occurred while processing the interrupt then
    * g_current_regs may have change value.  If we return any value different
    * from the input regs, then the lower level will know that a context

arch/risc-v/src/rv32im/riscv_copystate.c

@@ -70,6 +70,10 @@ void up_copystate(uint32_t *dest, uint32_t *src)
 {
   int i;
 
+#ifdef CONFIG_ARCH_FPU
+  uint32_t *regs = dest;
+#endif
+
   /* In the RISC-V model, the state is copied from the stack to the TCB,
    * but only a reference is passed to get the state from the TCB.  So the
    * following check avoids copying the TCB save area onto itself:
@@ -77,13 +81,20 @@ void up_copystate(uint32_t *dest, uint32_t *src)
 
   if (src != dest)
     {
-      for (i = 0; i < XCPTCONTEXT_REGS; i++)
+      /* save integer registers first */
+
+      for (i = 0; i < INT_XCPT_REGS; i++)
         {
           *dest++ = *src++;
         }
 
+      /* Save the floating point registers: This will initialize the floating
+       * registers at indices INT_XCPT_REGS through (XCPTCONTEXT_REGS-1).
+       * Do this after saving REG_INT_CTX with the ORIGINAL context pointer.
+       */
+
 #ifdef CONFIG_ARCH_FPU
-      up_savefpu(dest);
+      up_savefpu(regs);
 #endif
     }
 }