diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3cea8205891..8aa8681902d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -353,6 +353,16 @@ config ARM64_GICV2_LEGACY_IRQ0
 
 endif
 
+if ARM64_GIC_VERSION = 3
+
+config ARM64_GICV3_SPI_EDGE
+	bool "Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default"
+	default n
+	---help---
+		Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default.
+
+endif
+
 config ARM64_SEMIHOSTING_HOSTFS
 	bool "Semihosting HostFS"
 	depends on FS_HOSTFS
diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c
index 9a8b77b4c6f..9b0d2985fb7 100644
--- a/arch/arm64/src/common/arm64_gicv3.c
+++ b/arch/arm64/src/common/arm64_gicv3.c
@@ -607,7 +607,15 @@ static void gicv3_dist_init(void)
        intid += GIC_NUM_CFG_PER_REG)
     {
       idx = intid / GIC_NUM_CFG_PER_REG;
+#ifdef CONFIG_ARM64_GICV3_SPI_EDGE
+      /* Configure all SPIs as edge-triggered by default */
+
+      putreg32(0xaaaaaaaa, ICFGR(base, idx));
+#else
+      /* Configure all SPIs as level-sensitive by default */
+
       putreg32(0, ICFGR(base, idx));
+#endif
     }
 
   /* TODO: Some arrch64 Cortex-A core maybe without security state