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https://github.com/apache/nuttx.git
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Merged in raiden00/nuttx_h7 (pull request #672)
stm32h7: add lowputc, more cosmetic in stm32h7x3xx_rcc.h Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
committed by
GregoryN
GregoryN
parent
0aa30eb15b
commit
8271f72b72
@@ -108,7 +108,7 @@ endif
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CHIP_ASRCS =
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CHIP_ASRCS =
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CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
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CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
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CHIP_CSRCS += stm32_start.c stm32_rcc.c
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CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += stm32_timerisr.c
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CHIP_CSRCS += stm32_timerisr.c
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,440 @@
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/****************************************************************************
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* arch/arm/src/stm32h7/stm32_lowputc.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "chip/stm32_pinmap.h"
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#include "stm32_rcc.h"
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#include "stm32_gpio.h"
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#include "stm32_uart.h"
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Select USART parameters for the selected console */
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#ifdef HAVE_CONSOLE
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# if defined(CONFIG_USART1_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART1_BASE
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# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
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# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
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# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
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# define STM32_CONSOLE_TX GPIO_USART1_TX
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# define STM32_CONSOLE_RX GPIO_USART1_RX
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# ifdef CONFIG_USART1_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
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# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART2_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
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# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN
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# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
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# define STM32_CONSOLE_TX GPIO_USART2_TX
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# define STM32_CONSOLE_RX GPIO_USART2_RX
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# ifdef CONFIG_USART2_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
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# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART3_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
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# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN
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# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
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# define STM32_CONSOLE_TX GPIO_USART3_TX
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# define STM32_CONSOLE_RX GPIO_USART3_RX
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# ifdef CONFIG_USART3_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
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# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART4_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
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# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART4EN
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# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
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# define STM32_CONSOLE_TX GPIO_UART4_TX
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# define STM32_CONSOLE_RX GPIO_UART4_RX
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# ifdef CONFIG_UART4_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
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# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART5_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
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# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART5EN
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# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
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# define STM32_CONSOLE_TX GPIO_UART5_TX
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# define STM32_CONSOLE_RX GPIO_UART5_RX
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# ifdef CONFIG_UART5_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
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# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_USART6_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_USART6_BASE
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# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
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# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART6EN
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# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD
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# define STM32_CONSOLE_BITS CONFIG_USART6_BITS
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# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP
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# define STM32_CONSOLE_TX GPIO_USART6_TX
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# define STM32_CONSOLE_RX GPIO_USART6_RX
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# ifdef CONFIG_USART6_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
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# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_UART7_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART7_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
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# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART7EN
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# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART7_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP
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# define STM32_CONSOLE_TX GPIO_UART7_TX
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# define STM32_CONSOLE_RX GPIO_UART7_RX
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# ifdef CONFIG_UART7_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR
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# if (CONFIG_UART7_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# elif defined(CONFIG_UART8_SERIAL_CONSOLE)
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# define STM32_CONSOLE_BASE STM32_UART8_BASE
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# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
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# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
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# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART8EN
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# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD
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# define STM32_CONSOLE_BITS CONFIG_UART8_BITS
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# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY
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# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP
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# define STM32_CONSOLE_TX GPIO_UART8_TX
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# define STM32_CONSOLE_RX GPIO_UART8_RX
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# ifdef CONFIG_UART8_RS485
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# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR
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# if (CONFIG_UART8_RS485_DIR_POLARITY == 0)
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# define STM32_CONSOLE_RS485_DIR_POLARITY false
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# else
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# define STM32_CONSOLE_RS485_DIR_POLARITY true
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# endif
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# endif
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# endif
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/* CR1 settings */
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# if STM32_CONSOLE_BITS == 7
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# define USART_CR_M01_VALUE USART_CR1_M1
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# elif STM32_CONSOLE_BITS == 9
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# define USART_CR_M01_VALUE USART_CR1_M0
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# else /* STM32_CONSOLE_BITS == 8 */
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# define USART_CR_M01_VALUE 0
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# endif
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# if STM32_CONSOLE_PARITY == 1
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# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
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# elif STM32_CONSOLE_PARITY == 2
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# define USART_CR1_PARITY_VALUE USART_CR1_PCE
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# else
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# define USART_CR1_PARITY_VALUE 0
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# endif
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# define USART_CR1_CLRBITS \
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(USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | USART_CR1_PCE | \
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USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_MME | USART_CR1_OVER8 | \
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USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
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# define USART_CR1_SETBITS (USART_CR_M01_VALUE | USART_CR1_PARITY_VALUE)
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/* CR2 settings */
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# if STM32_CONSOLE_2STOP != 0
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# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
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# else
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# define USART_CR2_STOP2_VALUE 0
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# endif
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# define USART_CR2_CLRBITS \
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(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
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USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
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USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \
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USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \
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USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
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# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
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/* CR3 settings */
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# define USART_CR3_CLRBITS \
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(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
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USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
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USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT | \
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USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP | \
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USART_CR1_SCARCNT_MASK)
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# define USART_CR3_SETBITS 0
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/* Only the STM32 F3 supports oversampling by 8 */
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# undef USE_OVER8
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/* Calculate USART BAUD rate divider */
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/* Baud rate for standard USART (SPI mode included):
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*
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* In case of oversampling by 16, the equation is:
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* baud = fCK / UARTDIV
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* UARTDIV = fCK / baud
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*
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* In case of oversampling by 8, the equation is:
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*
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* baud = 2 * fCK / UARTDIV
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* UARTDIV = 2 * fCK / baud
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*/
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# define STM32_USARTDIV8 \
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(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
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# define STM32_USARTDIV16 \
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((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
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/* Use oversampling by 8 only if the divisor is small. But what is small? */
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|
# if STM32_USARTDIV8 > 100
|
||||||
|
# define STM32_BRR_VALUE STM32_USARTDIV16
|
||||||
|
# else
|
||||||
|
# define USE_OVER8 1
|
||||||
|
# define STM32_BRR_VALUE \
|
||||||
|
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
|
||||||
|
# endif
|
||||||
|
#endif /* HAVE_CONSOLE */
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Private Types
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Private Function Prototypes
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Public Data
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Private Data
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Private Functions
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: up_lowputc
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Output one byte on the serial console
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
void up_lowputc(char ch)
|
||||||
|
{
|
||||||
|
#ifdef HAVE_CONSOLE
|
||||||
|
/* Wait until the TX data register is empty */
|
||||||
|
|
||||||
|
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
|
||||||
|
#ifdef STM32_CONSOLE_RS485_DIR
|
||||||
|
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Then send the character */
|
||||||
|
|
||||||
|
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
|
||||||
|
|
||||||
|
#ifdef STM32_CONSOLE_RS485_DIR
|
||||||
|
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
|
||||||
|
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HAVE_CONSOLE */
|
||||||
|
}
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: stm32_lowsetup
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* This performs basic initialization of the USART used for the serial
|
||||||
|
* console. Its purpose is to get the console output availabe as soon
|
||||||
|
* as possible.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
void stm32_lowsetup(void)
|
||||||
|
{
|
||||||
|
#if defined(HAVE_UART)
|
||||||
|
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||||
|
uint32_t cr;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(HAVE_CONSOLE)
|
||||||
|
/* Enable USART APB1/2 clock */
|
||||||
|
|
||||||
|
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Enable the console USART and configure GPIO pins needed for rx/tx.
|
||||||
|
*
|
||||||
|
* NOTE: Clocking for selected U[S]ARTs was already provided in stm32_rcc.c
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef STM32_CONSOLE_TX
|
||||||
|
stm32_configgpio(STM32_CONSOLE_TX);
|
||||||
|
#endif
|
||||||
|
#ifdef STM32_CONSOLE_RX
|
||||||
|
stm32_configgpio(STM32_CONSOLE_RX);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STM32_CONSOLE_RS485_DIR
|
||||||
|
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
|
||||||
|
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Enable and configure the selected console device */
|
||||||
|
|
||||||
|
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||||
|
/* Configure CR2 */
|
||||||
|
|
||||||
|
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||||
|
cr &= ~USART_CR2_CLRBITS;
|
||||||
|
cr |= USART_CR2_SETBITS;
|
||||||
|
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
|
||||||
|
|
||||||
|
/* Configure CR1 */
|
||||||
|
|
||||||
|
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||||
|
cr &= ~USART_CR1_CLRBITS;
|
||||||
|
cr |= USART_CR1_SETBITS;
|
||||||
|
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||||
|
|
||||||
|
/* Configure CR3 */
|
||||||
|
|
||||||
|
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||||
|
cr &= ~USART_CR3_CLRBITS;
|
||||||
|
cr |= USART_CR3_SETBITS;
|
||||||
|
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
|
||||||
|
|
||||||
|
/* Configure the USART Baud Rate */
|
||||||
|
|
||||||
|
putreg32(STM32_BRR_VALUE, STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
|
||||||
|
|
||||||
|
/* Select oversampling by 8 */
|
||||||
|
|
||||||
|
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||||
|
#ifdef USE_OVER8
|
||||||
|
cr |= USART_CR1_OVER8;
|
||||||
|
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Enable Rx, Tx, and the USART */
|
||||||
|
|
||||||
|
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
|
||||||
|
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
|
||||||
|
|
||||||
|
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
|
||||||
|
#endif /* HAVE_UART */
|
||||||
|
}
|
||||||
@@ -0,0 +1,77 @@
|
|||||||
|
/************************************************************************************
|
||||||
|
* arch/arm/src/stm32h7/stm32_lowputc.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_LOWPUTC_H
|
||||||
|
#define __ARCH_ARM_SRC_STM32H7_STM32_LOWPUTC_H
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Function Prototypes
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
#define EXTERN extern "C"
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#else
|
||||||
|
#define EXTERN extern
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Name: stm32_lowsetup
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Called at the very beginning of _start. Performs low level initialization
|
||||||
|
* of serial console.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
void stm32_lowsetup(void);
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASSEMBLY__ */
|
||||||
|
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_LOWPUTC_H */
|
||||||
@@ -54,9 +54,9 @@
|
|||||||
# include "nvic.h"
|
# include "nvic.h"
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// TODO: #include "stm32_rcc.h"
|
#include "stm32_rcc.h"
|
||||||
// TODO: #include "stm32_userspace.h"
|
// TODO: #include "stm32_userspace.h"
|
||||||
// TODO: #include "stm32_lowputc.h"
|
#include "stm32_lowputc.h"
|
||||||
#include "stm32_start.h"
|
#include "stm32_start.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -109,6 +109,20 @@ static void go_os_start(void *pv, unsigned int nbytes)
|
|||||||
__attribute__ ((naked, no_instrument_function, noreturn));
|
__attribute__ ((naked, no_instrument_function, noreturn));
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
/****************************************************************************
|
||||||
|
* Name: showprogress
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Print a character on the UART to show boot status.
|
||||||
|
*
|
||||||
|
****************************************************************************/
|
||||||
|
|
||||||
|
#ifdef CONFIG_DEBUG_FEATURES
|
||||||
|
# define showprogress(c) up_lowputc(c)
|
||||||
|
#else
|
||||||
|
# define showprogress(c)
|
||||||
|
#endif
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
@@ -358,9 +372,10 @@ void __start(void)
|
|||||||
|
|
||||||
/* Configure the UART so that we can get debug output as soon as possible */
|
/* Configure the UART so that we can get debug output as soon as possible */
|
||||||
|
|
||||||
// TODO: stm32_clockconfig();
|
stm32_clockconfig();
|
||||||
stm32_fpuconfig();
|
stm32_fpuconfig();
|
||||||
// TODO: stm32_lowsetup();
|
stm32_lowsetup();
|
||||||
|
showprogress('A');
|
||||||
|
|
||||||
/* Enable/disable tightly coupled memories */
|
/* Enable/disable tightly coupled memories */
|
||||||
|
|
||||||
@@ -369,18 +384,21 @@ void __start(void)
|
|||||||
/* Initialize onboard resources */
|
/* Initialize onboard resources */
|
||||||
|
|
||||||
stm32_boardinitialize();
|
stm32_boardinitialize();
|
||||||
|
showprogress('B');
|
||||||
|
|
||||||
/* Enable I- and D-Caches */
|
/* Enable I- and D-Caches */
|
||||||
|
|
||||||
arch_dcache_writethrough();
|
arch_dcache_writethrough();
|
||||||
arch_enable_icache();
|
arch_enable_icache();
|
||||||
arch_enable_dcache();
|
arch_enable_dcache();
|
||||||
|
showprogress('C');
|
||||||
|
|
||||||
/* Perform early serial initialization */
|
/* Perform early serial initialization */
|
||||||
|
|
||||||
#ifdef USE_EARLYSERIALINIT
|
#ifdef USE_EARLYSERIALINIT
|
||||||
up_earlyserialinit();
|
up_earlyserialinit();
|
||||||
#endif
|
#endif
|
||||||
|
showprogress('D');
|
||||||
|
|
||||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||||
* platform specific initialization of the user memory is required.
|
* platform specific initialization of the user memory is required.
|
||||||
@@ -391,9 +409,13 @@ void __start(void)
|
|||||||
#ifdef CONFIG_BUILD_PROTECTED
|
#ifdef CONFIG_BUILD_PROTECTED
|
||||||
stm32_userspace();
|
stm32_userspace();
|
||||||
#endif
|
#endif
|
||||||
|
showprogress('E');
|
||||||
|
|
||||||
/* Then start NuttX */
|
/* Then start NuttX */
|
||||||
|
|
||||||
|
showprogress('\r');
|
||||||
|
showprogress('\n');
|
||||||
|
|
||||||
#ifdef CONFIG_STACK_COLORATION
|
#ifdef CONFIG_STACK_COLORATION
|
||||||
/* Set the IDLE stack to the coloration value and jump into os_start() */
|
/* Set the IDLE stack to the coloration value and jump into os_start() */
|
||||||
|
|
||||||
|
|||||||
@@ -0,0 +1,240 @@
|
|||||||
|
/************************************************************************************
|
||||||
|
* arch/arm/src/stm32h7/stm32_uart.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_UART_H
|
||||||
|
#define __ARCH_ARM_SRC_STM32H7_STM32_UART_H
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include <nuttx/serial/serial.h>
|
||||||
|
|
||||||
|
#include "chip/stm32_uart.h"
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************/
|
||||||
|
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
|
||||||
|
* device.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if STM32H7_NUART < 4
|
||||||
|
# undef CONFIG_STM32H7_UART8
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NUART < 3
|
||||||
|
# undef CONFIG_STM32H7_UART7
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NUART < 2
|
||||||
|
# undef CONFIG_STM32H7_UART5
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NUART < 1
|
||||||
|
# undef CONFIG_STM32H7_UART4
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if STM32H7_NUSART < 4
|
||||||
|
# undef CONFIG_STM32H7_USART6
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NUSART < 3
|
||||||
|
# undef CONFIG_STM32H7_USART3
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NUSART < 2
|
||||||
|
# undef CONFIG_STM32H7_USART2
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NUSART < 1
|
||||||
|
# undef CONFIG_STM32H7_USART1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Is there a USART enabled? */
|
||||||
|
|
||||||
|
#if defined(CONFIG_STM32H7_USART1) || defined(CONFIG_STM32H7_USART2) || \
|
||||||
|
defined(CONFIG_STM32H7_USART3) || defined(CONFIG_STM32H7_UART4) || \
|
||||||
|
defined(CONFIG_STM32H7_UART5) || defined(CONFIG_STM32H7_USART6) || \
|
||||||
|
defined(CONFIG_STM32H7_UART7) || defined(CONFIG_STM32H7_UART8)
|
||||||
|
# define HAVE_UART 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Is there a serial console? */
|
||||||
|
|
||||||
|
#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART1)
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 1
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART2)
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 2
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART3)
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 3
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART4)
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 4
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART5)
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 5
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART6)
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 6
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART7)
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 7
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART8)
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 8
|
||||||
|
# define HAVE_CONSOLE 1
|
||||||
|
#else
|
||||||
|
# undef CONFIG_USART1_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART2_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART3_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART4_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART5_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_USART6_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART7_SERIAL_CONSOLE
|
||||||
|
# undef CONFIG_UART8_SERIAL_CONSOLE
|
||||||
|
# define CONSOLE_UART 0
|
||||||
|
# undef HAVE_CONSOLE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Is RS-485 used? */
|
||||||
|
|
||||||
|
#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \
|
||||||
|
defined(CONFIG_USART3_RS485) || defined(CONFIG_UART4_RS485) || \
|
||||||
|
defined(CONFIG_UART5_RS485) || defined(CONFIG_USART6_RS485) || \
|
||||||
|
defined(CONFIG_UART7_RS485) || defined(CONFIG_UART8_RS485)
|
||||||
|
# define HAVE_RS485 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HAVE_RS485
|
||||||
|
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE)
|
||||||
|
#else
|
||||||
|
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
#define EXTERN extern "C"
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#else
|
||||||
|
#define EXTERN extern
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Name: stm32_serial_get_uart
|
||||||
|
*
|
||||||
|
* Description:
|
||||||
|
* Get serial driver structure for STM32 USART
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
FAR uart_dev_t *stm32_serial_get_uart(int uart_num);
|
||||||
|
|
||||||
|
#undef EXTERN
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __ASSEMBLY__ */
|
||||||
|
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_UART_H */
|
||||||
@@ -102,7 +102,9 @@ static inline void rcc_reset(void)
|
|||||||
/* Reset HSION, HSEON, CSSON and PLLON bits */
|
/* Reset HSION, HSEON, CSSON and PLLON bits */
|
||||||
|
|
||||||
regval = getreg32(STM32_RCC_CR);
|
regval = getreg32(STM32_RCC_CR);
|
||||||
regval &= ~(RCC_CR_HSEON | RCC_CR_HSI48ON | RCC_CR_CSION | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
|
regval &= ~(RCC_CR_HSEON | RCC_CR_HSI48ON |
|
||||||
|
RCC_CR_CSION | RCC_CR_PLL1ON |
|
||||||
|
RCC_CR_PLL2ON | RCC_CR_PLL3ON);
|
||||||
putreg32(regval, STM32_RCC_CR);
|
putreg32(regval, STM32_RCC_CR);
|
||||||
|
|
||||||
/* Reset PLLCFGR register to reset default */
|
/* Reset PLLCFGR register to reset default */
|
||||||
@@ -138,7 +140,17 @@ static inline void rcc_enableahb1(void)
|
|||||||
|
|
||||||
regval = getreg32(STM32_RCC_AHB1ENR);
|
regval = getreg32(STM32_RCC_AHB1ENR);
|
||||||
|
|
||||||
// TODO: ...
|
#ifdef CONFIG_STM32H7_DMA1
|
||||||
|
/* DMA 1 clock enable */
|
||||||
|
|
||||||
|
regval |= RCC_AHB1ENR_DMA1EN;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32H7_DMA2
|
||||||
|
/* DMA 2 clock enable */
|
||||||
|
|
||||||
|
regval |= RCC_AHB1ENR_DMA2EN;
|
||||||
|
#endif
|
||||||
|
|
||||||
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
|
||||||
}
|
}
|
||||||
@@ -190,10 +202,10 @@ static inline void rcc_enableahb3(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: rcc_enableahb3
|
* Name: rcc_enableahb4
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable selected AHB1 peripherals
|
* Enable selected AHB4 peripherals
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
@@ -207,7 +219,54 @@ static inline void rcc_enableahb4(void)
|
|||||||
|
|
||||||
regval = getreg32(STM32_RCC_AHB4ENR);
|
regval = getreg32(STM32_RCC_AHB4ENR);
|
||||||
|
|
||||||
// TODO: ...
|
/* Enable GPIO, GPIOB, ... GPIOK */
|
||||||
|
|
||||||
|
#if STM32H7_NGPIO > 0
|
||||||
|
regval |= (RCC_AHB4ENR_GPIOAEN
|
||||||
|
#if STM32H7_NGPIO > 1
|
||||||
|
| RCC_AHB4ENR_GPIOBEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 2
|
||||||
|
| RCC_AHB4ENR_GPIOCEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 3
|
||||||
|
| RCC_AHB4ENR_GPIODEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 4
|
||||||
|
| RCC_AHB4ENR_GPIOEEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 5
|
||||||
|
| RCC_AHB4ENR_GPIOFEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 6
|
||||||
|
| RCC_AHB4ENR_GPIOGEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 7
|
||||||
|
| RCC_AHB4ENR_GPIOHEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 8
|
||||||
|
| RCC_AHB4ENR_GPIOIEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 9
|
||||||
|
| RCC_AHB4ENR_GPIOJEN
|
||||||
|
#endif
|
||||||
|
#if STM32H7_NGPIO > 10
|
||||||
|
| RCC_AHB4ENR_GPIOKEN
|
||||||
|
#endif
|
||||||
|
);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32H7_CRC
|
||||||
|
/* CRC clock enable */
|
||||||
|
|
||||||
|
regval |= RCC_AHB4ENR_CRCEN;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_STM32H7_BKPSRAM
|
||||||
|
/* Backup SRAM clock enable */
|
||||||
|
|
||||||
|
regval |= RCC_AHB4ENR_BKPSRAMEN;
|
||||||
|
#endif
|
||||||
|
|
||||||
putreg32(regval, STM32_RCC_AHB4ENR); /* Enable peripherals */
|
putreg32(regval, STM32_RCC_AHB4ENR); /* Enable peripherals */
|
||||||
}
|
}
|
||||||
@@ -654,8 +713,11 @@ static inline void rcc_enableperipherals(void)
|
|||||||
rcc_enableahb1();
|
rcc_enableahb1();
|
||||||
rcc_enableahb2();
|
rcc_enableahb2();
|
||||||
rcc_enableahb3();
|
rcc_enableahb3();
|
||||||
|
rcc_enableahb4();
|
||||||
rcc_enableapb1();
|
rcc_enableapb1();
|
||||||
rcc_enableapb2();
|
rcc_enableapb2();
|
||||||
|
rcc_enableapb3();
|
||||||
|
rcc_enableapb4();
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
|
|||||||
Reference in New Issue
Block a user