Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-04 23:03:27 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

SAM3/4: Cosmetic updates to ADC register defintion header files

Browse Source
This commit is contained in:
Gregory Nutt
2014-02-27 08:41:03 -06:00
parent 8e8c2cd5ec
commit 81999adb15
2 changed files with 67 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/sam34/chip/sam_adc.h
+14 -3
View File
@@ -48,8 +48,11 @@
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* General definitions ******************************************************************/
/* ADC register offsets ****************************************************************/
#define SAM_ADC_NCHANNELS 8 /* 8 ADC Channels */
/* ADC register offsets *****************************************************************/
#define SAM_ADC_CR_OFFSET 0x00 /* Control Register (Both) */
#define SAM_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */
@@ -75,7 +78,7 @@
#define SAM_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */
#define SAM_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */
/* ADC register addresses **************************************************************/
/* ADC register addresses ***************************************************************/
#define SAM_ADC12B_CR (SAM_ADC12B_BASE+SAM_ADC_CR_OFFSET)
#define SAM_ADC12B_MR (SAM_ADC12B_BASE+SAM_ADC_MR_OFFSET)
@@ -119,7 +122,7 @@
# define SAM_ADC_CDR6 (SAM_ADC_BASE+SAM_ADC_CDR6_OFFSET)
# define SAM_ADC_CDR7 (SAM_ADC_BASE+SAM_ADC_CDR7_OFFSET)
/* ADC register bit definitions ********************************************************/
/* ADC register bit definitions *********************************************************/
/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */
@@ -131,16 +134,21 @@
#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT)
# define ADC_MR_TRGSEL(n) ((uint32_t)(n) << ADC_MR_TRGSEL_SHIFT)
#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */
#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */
#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT)
# define ADC_MR_PRESCAL(n) ((uint32_t)(n) << ADC_MR_PRESCAL_SHIFT)
#define ADB12B_MR_STARTUP_SHIFT (16) /* Bits 16-23: Start Up Time (ADC12B) */
#define ADB12B_MR_STARTUP_MASK (0xff << ADB12B_MR_STARTUP_SHIFT
# define ADB12B_MR_STARTUP(n) ((uint32_t)(n) << ADB12B_MR_STARTUP_SHIFT
#define ADB10B_MR_STARTUP_SHIFT (16) /* Bits 16-22: Start Up Time (ADC10B) */
#define ADB10B_MR_STARTUP_MASK (0x7f << ADB10B_MR_STARTUP_SHIFT)
# define ADB10B_MR_STARTUP(n) ((uint32_t)(n) << ADB10B_MR_STARTUP_SHIFT)
#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27: Sample & Hold Time */
#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
# define ADC_MR_SHTIM(n) ((uint32_t)(n) << ADC_MR_SHTIM_SHIFT)
/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel
* Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register,
@@ -161,8 +169,10 @@
#define ADC12B_ACR_GAIN_SHIFT (0) /* Bits 0-1: Input Gain */
#define ADC12B_ACR_GAIN_MASK (3 << ADC12B_ACR_GAIN_SHIFT)
# define ADC12B_ACR_GAIN(n) ((uint32_t)(n) << ADC12B_ACR_GAIN_SHIFT)
#define ADC12B_ACR_IBCTL_SHIFT (8) /* Bits 8-9: Bias Current Control */
#define ADC12B_ACR_IBCTL_MASK (3 << ADC12B_ACR_IBCTL_SHIFT)
# define ADC12B_ACR_IBCTL(n) ((uint32_t)(n) << ADC12B_ACR_IBCTL_SHIFT)
#define ADC12B_ACR_DIFF (1 << 16) /* Bit 16: Differential Mode */
#define ADC12B_ACR_OFFSET (1 << 17) /* Bit 17: Input OFFSET */
@@ -171,6 +181,7 @@
#define ADC12B_EMR_OFFMODES (1 << 0) /* Bit 0: Off Mode if Sleep Bit (ADC12B_MR) = 1 */
#define ADC12B_EMR_OFFMSTIME_SHIFT (16) /* Bits 16-23: Startup Time */
#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT)
# define ADC12B_EMR_OFFMSTIME(n) ((uint32_t)(n) << ADC12B_EMR_OFFMSTIME_SHIFT)
/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt
* Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register,
arch/arm/src/sam34/chip/sam_afec.h
+3
View File
@@ -49,6 +49,9 @@
/****************************************************************************************
* Pre-processor Definitions
****************************************************************************************/
/* General definitions ******************************************************************/
#define SAM_ADC_NCHANNELS 16 /* 16 ADC Channels */
/* AFEC register offsets ****************************************************************/