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style: fix multiple style issues and remove unused

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Signed-off-by: Petro Karashchenko <petro.karashchenko@gmail.com>
This commit is contained in:
Petro Karashchenko
2023-09-10 15:20:43 +03:00
committed by Xiang Xiao
parent f06c509f9e
commit 816cb3cfaf
6 changed files with 57 additions and 60 deletions
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arch/arm/src/armv7-m/mpu.h
+43 -38
View File
@@ -72,11 +72,11 @@
#if defined(CONFIG_ARM_MPU_NREGIONS) && defined(CONFIG_ARM_MPU) #if defined(CONFIG_ARM_MPU_NREGIONS) && defined(CONFIG_ARM_MPU)
# if CONFIG_ARM_MPU_NREGIONS <= 8 # if CONFIG_ARM_MPU_NREGIONS <= 8
# define MPU_RNR_MASK (0x00000007) # define MPU_RNR_MASK (0x00000007)
# elif CONFIG_ARM_MPU_NREGIONS <= 16 # elif CONFIG_ARM_MPU_NREGIONS <= 16
# define MPU_RNR_MASK (0x0000000f) # define MPU_RNR_MASK (0x0000000f)
# elif CONFIG_ARM_MPU_NREGIONS <= 32 # elif CONFIG_ARM_MPU_NREGIONS <= 32
# define MPU_RNR_MASK (0x0000001f) # define MPU_RNR_MASK (0x0000001f)
# else # else
# error "FIXME: Unsupported number of MPU regions" # error "FIXME: Unsupported number of MPU regions"
# endif # endif
@@ -94,7 +94,7 @@
#define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */ #define MPU_RASR_ENABLE (1 << 0) /* Bit 0: Region enable */
#define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */ #define MPU_RASR_SIZE_SHIFT (1) /* Bits 1-5: Size of the MPU protection region */
#define MPU_RASR_SIZE_MASK (31 << MPU_RASR_SIZE_SHIFT) #define MPU_RASR_SIZE_MASK (31 << MPU_RASR_SIZE_SHIFT)
# define MPU_RASR_SIZE_LOG2(n) ((n-1) << MPU_RASR_SIZE_SHIFT) # define MPU_RASR_SIZE_LOG2(n) ((n - 1) << MPU_RASR_SIZE_SHIFT)
#define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */ #define MPU_RASR_SRD_SHIFT (8) /* Bits 8-15: Subregion disable */
#define MPU_RASR_SRD_MASK (0xff << MPU_RASR_SRD_SHIFT) #define MPU_RASR_SRD_MASK (0xff << MPU_RASR_SRD_SHIFT)
# define MPU_RASR_SRD_0 (0x01 << MPU_RASR_SRD_SHIFT) # define MPU_RASR_SRD_0 (0x01 << MPU_RASR_SRD_SHIFT)
@@ -115,7 +115,7 @@
# define MPU_RASR_TEX_SO (0 << MPU_RASR_TEX_SHIFT) /* Strongly Ordered */ # define MPU_RASR_TEX_SO (0 << MPU_RASR_TEX_SHIFT) /* Strongly Ordered */
# define MPU_RASR_TEX_NOR (1 << MPU_RASR_TEX_SHIFT) /* Normal */ # define MPU_RASR_TEX_NOR (1 << MPU_RASR_TEX_SHIFT) /* Normal */
# define MPU_RASR_TEX_DEV (2 << MPU_RASR_TEX_SHIFT) /* Device */ # define MPU_RASR_TEX_DEV (2 << MPU_RASR_TEX_SHIFT) /* Device */
# define MPU_RASR_TEX_BB(bb) ((4|(bb)) << MPU_RASR_TEX_SHIFT) # define MPU_RASR_TEX_BB(bb) ((4 | (bb)) << MPU_RASR_TEX_SHIFT)
# define MPU_RASR_CP_NC (0) /* Non-cacheable */ # define MPU_RASR_CP_NC (0) /* Non-cacheable */
# define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */ # define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */
# define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */ # define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */
@@ -142,7 +142,7 @@
#if defined(CONFIG_MPU_RESET) #if defined(CONFIG_MPU_RESET)
void mpu_reset(void); void mpu_reset(void);
#else #else
# define mpu_reset() do { } while (0) # define mpu_reset()
#endif #endif
/**************************************************************************** /****************************************************************************
@@ -157,7 +157,7 @@ void mpu_reset(void);
#if defined(CONFIG_ARM_MPU_EARLY_RESET) #if defined(CONFIG_ARM_MPU_EARLY_RESET)
void mpu_early_reset(void); void mpu_early_reset(void);
#else #else
# define mpu_early_reset() do { } while (0) # define mpu_early_reset()
#endif #endif
#ifdef CONFIG_ARM_MPU #ifdef CONFIG_ARM_MPU
@@ -246,8 +246,7 @@ void mpu_control(bool enable, bool hfnmiena, bool privdefena);
* *
****************************************************************************/ ****************************************************************************/
void mpu_configure_region(uintptr_t base, size_t size, void mpu_configure_region(uintptr_t base, size_t size, uint32_t flags);
uint32_t flags);
/**************************************************************************** /****************************************************************************
* Inline Functions * Inline Functions
@@ -267,12 +266,13 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \ { \
uint32_t regval = getreg32(MPU_TYPE); \ uint32_t regval = getreg32(MPU_TYPE); \
sinfo("%s MPU Regions: data=%d instr=%d\n", \ sinfo("%s MPU Regions: data=%d instr=%d\n", \
(regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified", \ (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified", \
(regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT, \ (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT, \
(regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT); \ (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT); \
} while (0) } \
while (0)
#else #else
# define mpu_showtype() do { } while (0) # define mpu_showtype()
#endif #endif
/**************************************************************************** /****************************************************************************
@@ -288,13 +288,14 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \ { \
/* The configure the region */ \ /* The configure the region */ \
mpu_configure_region(base, size, \ mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \ MPU_RASR_TEX_SO | /* Ordered */ \
/* Not Cacheable */ \ /* Not Cacheable */ \
/* Not Bufferable */ \ /* Not Bufferable */ \
MPU_RASR_S | /* Shareable */ \ MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO /* P:RW U:None */ \ MPU_RASR_AP_RWNO /* P:RW U:None */ \
/* Instruction access */); \ /* Instruction access */); \
} while (0) } \
while (0)
/**************************************************************************** /****************************************************************************
* Name: mpu_user_flash * Name: mpu_user_flash
@@ -309,13 +310,14 @@ void mpu_configure_region(uintptr_t base, size_t size,
{ \ { \
/* The configure the region */ \ /* The configure the region */ \
mpu_configure_region(base, size, \ mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \ MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \ MPU_RASR_C | /* Cacheable */ \
/* Not Bufferable */ \ /* Not Bufferable */ \
/* Not Shareable */ \ /* Not Shareable */ \
MPU_RASR_AP_RORO /* P:RO U:RO */ \ MPU_RASR_AP_RORO /* P:RO U:RO */ \
/* Instruction access */); \ /* Instruction access */); \
} while (0) } \
while (0)
/**************************************************************************** /****************************************************************************
* Name: mpu_priv_flash * Name: mpu_priv_flash
@@ -336,7 +338,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
/* Not Shareable */ \ /* Not Shareable */ \
MPU_RASR_AP_RONO /* P:RO U:None */ \ MPU_RASR_AP_RONO /* P:RO U:None */ \
/* Instruction access */); \ /* Instruction access */); \
} while (0) } \
while (0)
/**************************************************************************** /****************************************************************************
* Name: mpu_user_intsram * Name: mpu_user_intsram
@@ -357,7 +360,8 @@ void mpu_configure_region(uintptr_t base, size_t size,
MPU_RASR_S | /* Shareable */ \ MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWRW /* P:RW U:RW */ \ MPU_RASR_AP_RWRW /* P:RW U:RW */ \
/* Instruction access */); \ /* Instruction access */); \
} while (0) } \
while (0)
/**************************************************************************** /****************************************************************************
* Name: mpu_priv_intsram * Name: mpu_priv_intsram
@@ -371,14 +375,15 @@ void mpu_configure_region(uintptr_t base, size_t size,
do \ do \
{ \ { \
/* The configure the region */ \ /* The configure the region */ \
mpu_configure_region(base, size,\ mpu_configure_region(base, size, \
MPU_RASR_TEX_SO | /* Ordered */ \ MPU_RASR_TEX_SO | /* Ordered */ \
MPU_RASR_C | /* Cacheable */ \ MPU_RASR_C | /* Cacheable */ \
/* Not Bufferable */ \ /* Not Bufferable */ \
MPU_RASR_S | /* Shareable */ \ MPU_RASR_S | /* Shareable */ \
MPU_RASR_AP_RWNO /* P:RW U:None */ \ MPU_RASR_AP_RWNO /* P:RW U:None */ \
/* Instruction access */); \ /* Instruction access */); \
} while (0) } \
while (0)
/**************************************************************************** /****************************************************************************
* Name: mpu_priv_shmem * Name: mpu_priv_shmem
arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c
+4 -4
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@@ -71,7 +71,7 @@
#include "esp32c3_clockconfig.h" #include "esp32c3_clockconfig.h"
#ifdef CONFIG_PM #ifdef CONFIG_PM
#include "esp32c3_pm.h" # include "esp32c3_pm.h"
#endif #endif
#include "espidf_wifi.h" #include "espidf_wifi.h"
@@ -1654,7 +1654,7 @@ static int32_t esp_queue_send_generic(void *queue, void *item,
if (ret < 0) if (ret < 0)
{ {
wlerr("ERROR: Failed to send message to mqueue error=%d\n", wlerr("ERROR: Failed to send message to mqueue error=%d\n",
ret); ret);
} }
} }
else else
@@ -1676,7 +1676,7 @@ static int32_t esp_queue_send_generic(void *queue, void *item,
if (ret < 0) if (ret < 0)
{ {
wlerr("ERROR: Failed to timedsend message to mqueue error=%d\n", wlerr("ERROR: Failed to timedsend message to mqueue error=%d\n",
ret); ret);
} }
} }
@@ -1825,7 +1825,7 @@ static int32_t esp_queue_recv(void *queue, void *item, uint32_t ticks)
if (ret < 0) if (ret < 0)
{ {
wlerr("ERROR: Failed to timedreceive from mqueue error=%d\n", wlerr("ERROR: Failed to timedreceive from mqueue error=%d\n",
ret); ret);
} }
} }
arch/xtensa/src/esp32/esp32_ble.c
+1 -9
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@@ -41,7 +41,7 @@
#include <nuttx/wireless/bluetooth/bt_uart.h> #include <nuttx/wireless/bluetooth/bt_uart.h>
#if defined(CONFIG_UART_BTH4) #if defined(CONFIG_UART_BTH4)
#include <nuttx/serial/uart_bth4.h> # include <nuttx/serial/uart_bth4.h>
#endif #endif
#include "esp32_ble_adapter.h" #include "esp32_ble_adapter.h"
@@ -50,18 +50,10 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
/* BLE packet buffer max number */
#define BLE_BUF_NUM CONFIG_ESP32_BLE_PKTBUF_NUM
/* BLE packet buffer max size */ /* BLE packet buffer max size */
#define BLE_BUF_SIZE 1024 #define BLE_BUF_SIZE 1024
/* Low-priority work queue process RX/TX */
#define BLE_WORK LPWORK
/**************************************************************************** /****************************************************************************
* Private Types * Private Types
****************************************************************************/ ****************************************************************************/
arch/xtensa/src/esp32/esp32_irq.c
+7 -7
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@@ -317,7 +317,7 @@ static int esp32_getcpuint(uint32_t intmask)
* that CPU interrupt is available. * that CPU interrupt is available.
*/ */
bitmask = (1ul << cpuint); bitmask = 1ul << cpuint;
if ((intset & bitmask) != 0) if ((intset & bitmask) != 0)
{ {
/* Got it! */ /* Got it! */
@@ -335,7 +335,7 @@ static int esp32_getcpuint(uint32_t intmask)
if (ret >= 0) if (ret >= 0)
{ {
xtensa_enable_cpuint(&g_intenable[cpu], (1ul << ret)); xtensa_enable_cpuint(&g_intenable[cpu], 1ul << ret);
} }
return ret; return ret;
@@ -411,7 +411,7 @@ static void esp32_free_cpuint(int cpuint)
/* Mark the CPU interrupt as available */ /* Mark the CPU interrupt as available */
bitmask = (1ul << cpuint); bitmask = 1ul << cpuint;
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
if (up_cpu_index() != 0) if (up_cpu_index() != 0)
@@ -469,7 +469,7 @@ void up_irqinitialize(void)
/* Reserve CPU0 interrupt for some special drivers */ /* Reserve CPU0 interrupt for some special drivers */
#ifdef CONFIG_ESP32_WIFI #ifdef CONFIG_ESP32_WIFI
g_cpu0_intmap[ESP32_CPUINT_MAC] = CPUINT_ASSIGN(ESP32_IRQ_MAC); g_cpu0_intmap[ESP32_CPUINT_MAC] = CPUINT_ASSIGN(ESP32_IRQ_MAC);
xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32_CPUINT_MAC); xtensa_enable_cpuint(&g_intenable[0], 1 << ESP32_CPUINT_MAC);
#endif #endif
@@ -556,7 +556,7 @@ void up_disable_irq(int irq)
} }
#endif #endif
xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint)); xtensa_disable_cpuint(&g_intenable[cpu], 1ul << cpuint);
} }
else else
{ {
@@ -612,7 +612,7 @@ void up_enable_irq(int irq)
/* Enable the CPU interrupt now for internal CPU. */ /* Enable the CPU interrupt now for internal CPU. */
xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint)); xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint);
} }
else else
{ {
@@ -956,7 +956,7 @@ uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
for (; bit < ESP32_NCPUINTS && cpuints != 0; bit++) for (; bit < ESP32_NCPUINTS && cpuints != 0; bit++)
{ {
mask = (1 << bit); mask = 1 << bit;
if ((cpuints & mask) != 0) if ((cpuints & mask) != 0)
{ {
/* Extract the IRQ number from the mapping table */ /* Extract the IRQ number from the mapping table */
arch/xtensa/src/esp32/esp32_rtc_gpio.c
+1 -1
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@@ -342,7 +342,7 @@ void esp32_rtcioirqinitialize(void)
int cpu = up_cpu_index(); int cpu = up_cpu_index();
g_rtcio_cpuint = esp32_setup_irq(cpu, ESP32_PERIPH_RTC_CORE, g_rtcio_cpuint = esp32_setup_irq(cpu, ESP32_PERIPH_RTC_CORE,
1, ESP32_CPUINT_LEVEL); 1, ESP32_CPUINT_LEVEL);
DEBUGASSERT(g_rtcio_cpuint >= 0); DEBUGASSERT(g_rtcio_cpuint >= 0);
/* Attach and enable the interrupt handler */ /* Attach and enable the interrupt handler */
include/nuttx/signal.h
+1 -1
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@@ -638,7 +638,7 @@ int nxsig_notification(pid_t pid, FAR struct sigevent *event,
#ifdef CONFIG_SIG_EVTHREAD #ifdef CONFIG_SIG_EVTHREAD
void nxsig_cancel_notification(FAR struct sigwork_s *work); void nxsig_cancel_notification(FAR struct sigwork_s *work);
#else #else
#define nxsig_cancel_notification(work) (void)(work) # define nxsig_cancel_notification(work) (void)(work)
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus