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PIC32MZ: Fix some configuration settings and POSC mode should be external clock

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This commit is contained in:
Gregory Nutt
2015-02-28 11:54:47 -06:00
parent 6f6d73d757
commit 80f298ebf7
3 changed files with 25 additions and 10 deletions
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arch/mips/src/pic32mz/chip/pic32mzec-features.h
+2
View File
@@ -439,6 +439,8 @@
#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */
#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT)
# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */
# define DEVCFG1_DMTCNT_MIN (0 << DEVCFG1_DMTCNT_SHIFT) /* 2**8 (256) */
# define DEVCFG1_DMTCNT_MAX (12 << DEVCFG1_DMTCNT_SHIFT) /* 2**318 (2147483648) */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */
arch/mips/src/pic32mz/pic32mz-config.h
+5 -5
View File
@@ -211,13 +211,13 @@
#if (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 5000000
# error BOARD_PLL_INPUT / BOARD_PLL_IDIV too low
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_BYPASS /* < 5 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 9000000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 8000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_5_10MHZ /* 5-10 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 14500000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 13000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_8_16MHZ /* 8-16 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 23500000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 210000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_13_26MHZ /* 13-26 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 39000000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 36000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_21_42MHZ /* 21-42 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 64000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_34_64MHZ /* 36-64 MHz */
@@ -393,7 +393,7 @@
#define CONFIG_PIC32MZ_WDTSPGM DEVCFG1_WDTSPGM_STOP
#define CONFIG_PIC32MZ_WINDIS DEVCFG1_WDT_NORMAL
#define CONFIG_PIC32MZ_FWDTWINSZ DEVCFG1_FWDTWINSZ_25
#define CONFIG_PIC32MZ_DMTCNT DEVCFG1_DMTCNT_MASK
#define CONFIG_PIC32MZ_DMTCNT DEVCFG1_DMTCNT_MAX
#define CONFIG_PIC32MZ_FDMTEN 0
/* DEVCFG0 */