From 80dce6dba1b156dd643a1d110ad0f59854082092 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 9 Mar 2016 09:08:01 -0600 Subject: [PATCH] i.MX6: Add incomplete GPT header file --- arch/arm/src/armv7-a/gtm.h | 8 +-- arch/arm/src/imx6/chip/imx_gpt.h | 103 +++++++++++++++++++++++++++++++ 2 files changed, 107 insertions(+), 4 deletions(-) create mode 100644 arch/arm/src/imx6/chip/imx_gpt.h diff --git a/arch/arm/src/armv7-a/gtm.h b/arch/arm/src/armv7-a/gtm.h index 31ad61a6e2e..054d37f1784 100644 --- a/arch/arm/src/armv7-a/gtm.h +++ b/arch/arm/src/armv7-a/gtm.h @@ -54,7 +54,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* GIC Register Offsets *****************************************************/ +/* GTM Register Offsets *****************************************************/ #define GTM_COUNT0_OFFSET 0x0000 /* Global Timer Counter Register 0 */ #define GTM_COUNT1_OFFSET 0x0004 /* Global Timer Counter Register 1 */ @@ -64,7 +64,7 @@ #define GTM_COMP1_OFFSET 0x0014 /* Comparator Value Register 1 */ #define GTM_AUTO_OFFSET 0x0018 /* Auto-increment Register */ -/* GIC Register Addresses ***************************************************/ +/* GTM Register Addresses ***************************************************/ #define GTM_COUNT0 (MPCORE_GTM_VBASE+GTM_COUNT0_OFFSET) #define GTM_COUNT1 (MPCORE_GTM_VBASE+GTM_COUNT1_OFFSET) @@ -74,7 +74,7 @@ #define GTM_COMP1 (MPCORE_GTM_VBASE+COMPARE1_OFFSET) #define GTM_AUTO (MPCORE_GTM_VBASE+AUTO_OFFSET) -/* GIC Register Bit Definitions *********************************************/ +/* GTM Register Bit Definitions *********************************************/ /* Global Timer Counter Register 0/1 -- 64-bit timer counter value */ @@ -139,5 +139,5 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_ARMV7A_HAVE_GIC */ +#endif /* CONFIG_ARMV7A_HAVE_GTM */ #endif /* __ARCH_ARM_SRC_ARMV7_A_GTM_H */ diff --git a/arch/arm/src/imx6/chip/imx_gpt.h b/arch/arm/src/imx6/chip/imx_gpt.h new file mode 100644 index 00000000000..4c9573bd9c3 --- /dev/null +++ b/arch/arm/src/imx6/chip/imx_gpt.h @@ -0,0 +1,103 @@ +/************************************************************************************ + * arch/arm/src/imx6/imx_gpt.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: + * "i.MX 6Dual/6Quad ApplicationsProcessor Reference Manual," Document Number + * IMX6DQRM, Rev. 3, 07/2015, FreeScale. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPT_H +#define __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPT_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* GPT Register Offsets ************************************************************/ + +#define IMX_GPT_CR_OFFSET 0x0000 /* GPT Control Register */ +#define IMX_GPT_PR_OFFSET 0x0004 /* GPT Prescaler Register */ +#define IMX_GPT_SR_OFFSET 0x0008 /* GPT Status Register */ +#define IMX_GPT_IR_OFFSET 0x000c /* GPT Interrupt Register */ +#define IMX_GPT_OCR1_OFFSET 0x0010 /* GPT Output Compare Register 1 */ +#define IMX_GPT_OCR2_OFFSET 0x0014 /* GPT Output Compare Register 2 */ +#define IMX_GPT_OCR3_OFFSET 0x0018 /* GPT Output Compare Register 3 */ +#define IMX_GPT_ICR1_OFFSET 0x001c /* GPT Input Capture Register 1 */ +#define IMX_GPT_ICR2_OFFSET 0x0020 /* GPT Input Capture Register 2 */ +#define IMX_GPT_CNT_OFFSET 0x0024 /* GPT Counter Register */ + +/* GPT Register Addresses **********************************************************/ + +#define IMX_GPT_CR (IMX_GPT_VBASE+IMX_GPT_CR_OFFSET) +#define IMX_GPT_PR (IMX_GPT_VBASE+IMX_GPT_PR_OFFSET) +#define IMX_GPT_SR (IMX_GPT_VBASE+IMX_GPT_SR_OFFSET) +#define IMX_GPT_IR (IMX_GPT_VBASE+IMX_GPT_IR_OFFSET) +#define IMX_GPT_OCR1 (IMX_GPT_VBASE+IMX_GPT_OCR1_OFFSET) +#define IMX_GPT_OCR2 (IMX_GPT_VBASE+IMX_GPT_OCR2_OFFSET) +#define IMX_GPT_OCR3 (IMX_GPT_VBASE+IMX_GPT_OCR3_OFFSET) +#define IMX_GPT_ICR1 (IMX_GPT_VBASE+IMX_GPT_ICR1_OFFSET) +#define IMX_GPT_ICR2 (IMX_GPT_VBASE+IMX_GPT_ICR2_OFFSET) +#define IMX_GPT_CNT (IMX_GPT_VBASE+IMX_GPT_CNT_OFFSET) + +/* GPT Register Bit Definitions ****************************************************/ + +/* GPT Control Register */ +#define GPT_CR_ +/* GPT Prescaler Register */ +#define GPT_PR_ +/* GPT Status Register */ +#define GPT_SR_ +/* GPT Interrupt Register */ +#define GPT_IR_ +/* GPT Output Compare Register 1 */ +#define GPT_OCR1_ +/* GPT Output Compare Register 2 */ +#define GPT_OCR2_ +/* GPT Output Compare Register 3 */ +#define GPT_OCR3_ +/* GPT Input Capture Register 1 */ +#define GPT_ICR1_ +/* GPT Input Capture Register 2 */ +#define GPT_ICR2_ +/* GPT Counter Register */ +#define GPT_CNT_ + +#endif /* __ARCH_ARM_SRC_IMX6_CHIP_IMX_GPT_H */