From 80bbb0f24ce20edeeb805c7a2a1b82eb3c34f44e Mon Sep 17 00:00:00 2001
From: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
Date: Tue, 24 Jan 2023 10:16:43 -0300
Subject: [PATCH] esp32c3: Fix IRQ initialization, it was crashing on
 DEBUG_ASSERTIONS

Co-author: Alan C. Assis <alan.carvalho@espressif.com>
---
 arch/risc-v/include/esp32c3/irq.h       |  4 +---
 arch/risc-v/src/esp32c3/esp32c3_irq.c   | 19 +++++++------------
 arch/risc-v/src/esp32c3/esp32c3_start.c |  6 ------
 3 files changed, 8 insertions(+), 21 deletions(-)

diff --git a/arch/risc-v/include/esp32c3/irq.h b/arch/risc-v/include/esp32c3/irq.h
index 25e6855357f..9775a7a1999 100644
--- a/arch/risc-v/include/esp32c3/irq.h
+++ b/arch/risc-v/include/esp32c3/irq.h
@@ -116,10 +116,8 @@
  * The ESP32-C3 CPU interrupt controller accepts 31 asynchronous interrupts.
  */
 
-#define ESP32C3_CPUINT_MIN             1
-#define ESP32C3_CPUINT_MAX             31
-
 #define ESP32C3_NCPUINTS               32
+#define ESP32C3_CPUINT_MAX             (ESP32C3_NCPUINTS - 1)
 
 #define ESP32C3_CPUINT_MAC             0
 #define ESP32C3_CPUINT_MAC_NMI         1
diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c
index d3e145d29b0..5b95ceed4ae 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_irq.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c
@@ -189,8 +189,6 @@ static int esp32c3_getcpuint(void)
 
 void up_irqinitialize(void)
 {
-  int periphid;
-
   /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
 
   for (int i = 0; i < NR_IRQS; i++)
@@ -213,16 +211,9 @@ void up_irqinitialize(void)
   g_cpu_intmap[ESP32C3_CPUINT_RWBLE] = CPUINT_ASSIGN(ESP32C3_IRQ_RWBLE);
 #endif
 
-  /* Clear all peripheral interrupts from "bootloader" */
+  /* Initialize CPU interrupts */
 
-  for (periphid = 0; periphid < ESP32C3_NPERIPHERALS; periphid++)
-    {
-      putreg32(0, DR_REG_INTERRUPT_BASE + periphid * 4);
-    }
-
-  /* Set CPU interrupt threshold level */
-
-  putreg32(ESP32C3_DEFAULT_INT_THRESHOLD, INTERRUPT_CPU_INT_THRESH_REG);
+  esp32c3_cpuint_initialize();
 
   /* Attach the common interrupt handler */
 
@@ -257,7 +248,7 @@ void up_enable_irq(int irq)
 
   irqinfo("irq=%d | cpuint=%d \n", irq, cpuint);
 
-  DEBUGASSERT(cpuint >= ESP32C3_CPUINT_MIN && cpuint <= ESP32C3_CPUINT_MAX);
+  DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C3_CPUINT_MAX);
 
   irqstate = enter_critical_section();
   setbits(1 << cpuint, INTERRUPT_CPU_INT_ENABLE_REG);
@@ -379,6 +370,10 @@ int esp32c3_cpuint_initialize(void)
       putreg32(0, DR_REG_INTERRUPT_BASE + i * 4);
     }
 
+  /* Set CPU interrupt threshold level */
+
+  putreg32(ESP32C3_DEFAULT_INT_THRESHOLD, INTERRUPT_CPU_INT_THRESH_REG);
+
   /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
 
   memset(g_cpu_intmap, CPUINT_UNASSIGNED, ESP32C3_NCPUINTS);
diff --git a/arch/risc-v/src/esp32c3/esp32c3_start.c b/arch/risc-v/src/esp32c3/esp32c3_start.c
index bacf04649dd..eba49d39ad7 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_start.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_start.c
@@ -253,12 +253,6 @@ void __esp32c3_start(void)
   esp32c3_region_protection();
 #endif
 
-#ifndef CONFIG_SUPPRESS_INTERRUPTS
-  /* Put the CPU Interrupts in initial state */
-
-  esp32c3_cpuint_initialize();
-#endif
-
   /* Initialize RTC parameters */
 
   esp32c3_rtc_init();