diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 540fe3e44f9..6c261ce4159 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -274,7 +274,7 @@ static int rtc_interrupt(int irq, void *context) ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0); if (ret < 0) { - rtcllerr("ERRPR: work_queue failed: %d\n", ret); + rtcllerr("ERR0R: work_queue failed: %d\n", ret); } /* Disable any further alarm interrupts */ diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index c2850d67e49..4f7b2371dbb 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -1393,9 +1393,9 @@ endif # SAMA5_LCDC_HCR config SAMA5_LCDC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_LCD_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_LCD_INFO. endmenu # LCDC configuration endif # SAMA5_LCDC @@ -1499,9 +1499,9 @@ endif # !SAMA5_GMAC_AUTONEG config SAMA5_GMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # GMAC device driver options endif # SAMA5_GMAC @@ -1678,9 +1678,9 @@ config SAMA5_EMACA_NBC config SAMA5_EMACA_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_FEATURES ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_FEATURES. endmenu # EMAC device driver options endif # SAMA5_EMACA @@ -2087,9 +2087,9 @@ config SAMA5_EMACB_DEBUG config SAMA5_EMACB_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # EMAC device driver options endif # SAMA5_EMACB @@ -2364,11 +2364,11 @@ config SAMA5_SPI_DMADEBUG config SAMA5_SPI_REGDEBUG bool "SPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level SPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endmenu # SPI device driver options endif # SAMA5_SPI0 || SAMA5_SPI1 @@ -2399,11 +2399,11 @@ config SAMA5_TWI3_FREQUENCY config SAMA5_TWI_REGDEBUG bool "TWI register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2C_INFO default n ---help--- Output detailed register-level TWI device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2C_INFO. endmenu # TWI device driver options endif # SAMA5_TWI0 || SAMA5_TWI1 || SAMA5_TWI2 || SAMA5_TWI3 @@ -2776,11 +2776,11 @@ config SAMA5_SSC_DMADEBUG config SAMA5_SSC_REGDEBUG bool "SSC Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2S_INFO default n ---help--- Output detailed register-level SSC device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2S_INFO. config SAMA5_SSC_QDEBUG bool "SSC Queue debug" @@ -2881,11 +2881,11 @@ config SAMA5_HSMCI_CMDDEBUG config SAMA5_HSMCI_REGDEBUG bool "HSMCI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_MEMCARD_INFO default n ---help--- Output detailed register-level HSCMI device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_MEMCARD_INFO. endmenu # HSMCI device driver options endif # SAMA5_HSMCI0 || SAMA5_HSMCI1 || SAMA5_HSMCI2 @@ -2920,7 +2920,7 @@ config SAMA5_UDPHS_PREALLOCATE config SAMA5_UDPHS_REGDEBUG bool "Enable low-level UDPHS register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endmenu # USB High Speed Device Controller driver (DCD) options endif # SAMA5_UDPHS @@ -2960,7 +2960,7 @@ config SAMA5_OHCI_TDBUFSIZE config SAMA5_OHCI_REGDEBUG bool "Enable low-level OHCI register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endif # SAMA5_OHCI @@ -3009,7 +3009,7 @@ config SAMA5_EHCI_PREALLOCATE config SAMA5_EHCI_REGDEBUG bool "Enable low-level EHCI register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endif # SAMA5_EHCI @@ -3661,7 +3661,7 @@ endif # SAMA5_ADC_HAVE_CHAN config SAMA5_ADC_REGDEBUG bool "Enable register-level ADC/touchscreen debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_ANALOG_INFO ---help--- Enable very low register-level debug output. @@ -3915,11 +3915,11 @@ config SAMA5_TC_DEBUG config SAMA5_TC_REGDEBUG bool "TC register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_TIMER_INFO default n ---help--- Output detailed register-level Timer/Counter device debug - information. Very invasive! Requires also CONFIG_DEBUG_FEATURES. + information. Very invasive! Requires also CONFIG_DEBUG_TIMER_INFO. endmenu # Timer/counter Configuration endif # SAMA5_HAVE_TC @@ -4150,7 +4150,7 @@ endif # SAMA5_PWM_CHAN3 config SAMA5_PWM_REGDEBUG bool "Enable register-level PWM debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_PWM_INFO ---help--- Enable very low register-level debug output. @@ -4185,7 +4185,7 @@ config SAMA5_WDT_IDLEHALT config SAMA5_WDT_REGDEBUG bool "Register level debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_WATCHDOG_INFO ---help--- Enable low-level register debug output @@ -4699,10 +4699,9 @@ config SAMA5_NAND_DMADEBUG config SAMA5_NAND_REGDEBUG bool "Register-Level NAND Debug" default n - depends on DEBUG_FEATURES && DEBUG_FS + depends on DEBUG_FS_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES and - DEBUG_FS. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FS_INFO. config SAMA5_NAND_DUMP bool "NAND data dump" diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index 24099c0d920..ad276ff947a 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -371,6 +371,10 @@ #define SAMA5_ADC_SAMPLES (CONFIG_SAMA5_ADC_DMASAMPLES * SAMA5_NCHANNELS) +#ifndef CONFIG_DEBUG_ANALOG_INFO +# undef CONFIG_SAMA5_ADC_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -423,7 +427,7 @@ struct sam_adc_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_ADC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_ADC_REGDEBUG static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr, uint32_t regval, uintptr_t address); #endif @@ -544,7 +548,7 @@ static bool sam_adc_checkreg(struct sam_adc_s *priv, bool wr, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ainfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -2187,7 +2191,7 @@ uint32_t sam_adc_getreg(struct sam_adc_s *priv, uintptr_t address) if (sam_adc_checkreg(priv, false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + ainfo("%08x->%08x\n", address, regval); } return regval; @@ -2207,7 +2211,7 @@ void sam_adc_putreg(struct sam_adc_s *priv, uintptr_t address, uint32_t regval) { if (sam_adc_checkreg(priv, true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + ainfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index f772735bae7..29dcf728f6f 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -312,9 +312,9 @@ void up_addregion(void) } else { - _llerr("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: SDRAM memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -331,9 +331,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS0 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -350,9 +350,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS1 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -369,9 +369,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS2 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -388,9 +388,9 @@ void up_addregion(void) } else { - _llerr("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS); - _llerr(" Increase the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: CS3 memory not added to heap. CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS); + serr(" Increase the size of CONFIG_MM_NREGIONS\n"); } #endif @@ -398,9 +398,9 @@ void up_addregion(void) if (nregions > 0) { - _llerr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n", - CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS); - _llerr(" Decrease the size of CONFIG_MM_NREGIONS\n"); + serr("ERROR: Not all regions added to heap: %d added, but CONFIG_MM_NREGIONS=%d\n", + CONFIG_MM_REGIONS - nregions, CONFIG_MM_REGIONS); + serr(" Decrease the size of CONFIG_MM_NREGIONS\n"); } } #endif diff --git a/arch/arm/src/sama5/sam_can.c b/arch/arm/src/sama5/sam_can.c index bb580c9e143..10bb9a4d330 100644 --- a/arch/arm/src/sama5/sam_can.c +++ b/arch/arm/src/sama5/sam_can.c @@ -371,7 +371,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) { if (priv->count == 4) { - _llerr("...\n"); + caninfo("...\n"); } return regval; @@ -388,7 +388,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", priv->count - 3); + caninfo("[repeats %d more times]\n", priv->count - 3); } /* Save the new address, value, and count */ @@ -400,7 +400,7 @@ static uint32_t can_getreg(FAR struct sam_can_s *priv, int offset) /* Show the register value read */ - _llerr("%08x->%08x\n", regaddr, regval); + caninfo("%08x->%08x\n", regaddr, regval); return regval; } @@ -437,7 +437,7 @@ static void can_putreg(FAR struct sam_can_s *priv, int offset, uint32_t regval) /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + caninfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -474,29 +474,29 @@ static void can_dumpctrlregs(FAR struct sam_can_s *priv, FAR const char *msg) if (msg) { - canllerr("Control Registers: %s\n", msg); + caninfo("Control Registers: %s\n", msg); } else { - canllerr("Control Registers:\n"); + caninfo("Control Registers:\n"); } /* CAN control and status registers */ - _llerr(" MR: %08x IMR: %08x SR: %08x\n", - getreg32(config->base + SAM_CAN_MR_OFFSET), - getreg32(config->base + SAM_CAN_IMR_OFFSET), - getreg32(config->base + SAM_CAN_SR_OFFSET)); + caninfo(" MR: %08x IMR: %08x SR: %08x\n", + getreg32(config->base + SAM_CAN_MR_OFFSET), + getreg32(config->base + SAM_CAN_IMR_OFFSET), + getreg32(config->base + SAM_CAN_SR_OFFSET)); - _llerr(" BR: %08x TIM: %08x TIMESTP: %08x\n", - getreg32(config->base + SAM_CAN_BR_OFFSET), - getreg32(config->base + SAM_CAN_TIM_OFFSET), - getreg32(config->base + SAM_CAN_TIMESTP_OFFSET)); + caninfo(" BR: %08x TIM: %08x TIMESTP: %08x\n", + getreg32(config->base + SAM_CAN_BR_OFFSET), + getreg32(config->base + SAM_CAN_TIM_OFFSET), + getreg32(config->base + SAM_CAN_TIMESTP_OFFSET)); - _llerr(" ECR: %08x WPMR: %08x WPSR: %08x\n", - getreg32(config->base + SAM_CAN_ECR_OFFSET), - getreg32(config->base + SAM_CAN_TCR_OFFSET), - getreg32(config->base + SAM_CAN_ACR_OFFSET)); + caninfo(" ECR: %08x WPMR: %08x WPSR: %08x\n", + getreg32(config->base + SAM_CAN_ECR_OFFSET), + getreg32(config->base + SAM_CAN_TCR_OFFSET), + getreg32(config->base + SAM_CAN_ACR_OFFSET)); } #endif @@ -523,30 +523,30 @@ static void can_dumpmbregs(FAR struct sam_can_s *priv, FAR const char *msg) if (msg) { - canllerr("Mailbox Registers: %s\n", msg); + caninfo("Mailbox Registers: %s\n", msg); } else { - canllerr("Mailbox Registers:\n"); + caninfo("Mailbox Registers:\n"); } for (i = 0; i < SAM_CAN_NMAILBOXES; i++) { mbbase = config->base + SAM_CAN_MBn_OFFSET(i); - _llerr(" MB%d:\n", i); + caninfo(" MB%d:\n", i); /* CAN mailbox registers */ - _llerr(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n", - getreg32(mbbase + SAM_CAN_MMR_OFFSET), - getreg32(mbbase + SAM_CAN_MAM_OFFSET), - getreg32(mbbase + SAM_CAN_MID_OFFSET), - getreg32(mbbase + SAM_CAN_MFID_OFFSET)); + caninfo(" MMR: %08x MAM: %08x MID: %08x MFID: %08x\n", + getreg32(mbbase + SAM_CAN_MMR_OFFSET), + getreg32(mbbase + SAM_CAN_MAM_OFFSET), + getreg32(mbbase + SAM_CAN_MID_OFFSET), + getreg32(mbbase + SAM_CAN_MFID_OFFSET)); - _llerr(" MSR: %08x MDL: %08x MDH: %08x\n", - getreg32(mbbase + SAM_CAN_MSR_OFFSET), - getreg32(mbbase + SAM_CAN_MDL_OFFSET), - getreg32(mbbase + SAM_CAN_MDH_OFFSET)); + caninfo(" MSR: %08x MDL: %08x MDH: %08x\n", + getreg32(mbbase + SAM_CAN_MSR_OFFSET), + getreg32(mbbase + SAM_CAN_MDL_OFFSET), + getreg32(mbbase + SAM_CAN_MDH_OFFSET)); } } #endif @@ -851,7 +851,7 @@ static int can_setup(FAR struct can_dev_s *dev) ret = can_hwinitialize(priv); if (ret < 0) { - canllerr("CAN%d H/W initialization failed: %d\n", config->port, ret); + canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret); return ret; } @@ -863,7 +863,7 @@ static int can_setup(FAR struct can_dev_s *dev) ret = irq_attach(config->pid, config->handler); if (ret < 0) { - canllerr("Failed to attach CAN%d IRQ (%d)", config->port, config->pid); + canllerr("ERROR: Failed to attach CAN%d IRQ (%d)", config->port, config->pid); return ret; } @@ -872,7 +872,7 @@ static int can_setup(FAR struct can_dev_s *dev) ret = can_recvsetup(priv); if (ret < 0) { - canllerr("CAN%d H/W initialization failed: %d\n", config->port, ret); + canllerr("ERROR: CAN%d H/W initialization failed: %d\n", config->port, ret); return ret; } @@ -1693,7 +1693,7 @@ static int can_bittiming(struct sam_can_s *priv) { /* The BRP field must be within the range 1 - 0x7f */ - canerr("CAN%d: baud %d too high\n", config->port, config->baud); + canerr("CAN%d ERROR: baud %d too high\n", config->port, config->baud); return -EINVAL; } @@ -1741,7 +1741,7 @@ static int can_bittiming(struct sam_can_s *priv) if ((propag + phase1 + phase2) != (uint32_t)(tq - 4)) { - canerr("CAN%d: Could not realize baud %d\n", config->port, config->baud); + canerr("CAN%d ERROR: Could not realize baud %d\n", config->port, config->baud); return -EINVAL; } diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c index db6bad2ce6a..74bbd3f533e 100644 --- a/arch/arm/src/sama5/sam_dmac.c +++ b/arch/arm/src/sama5/sam_dmac.c @@ -657,7 +657,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table, } } - dmaerr("No channel found for pid %d\n", pid); + dmaerr("ERROR: No channel found for pid %d\n", pid); DEBUGPANIC(); return 0x3f; } @@ -2414,27 +2414,27 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle; struct sam_dmac_s *dmac = sam_controller(dmach); - dmaerr("%s\n", msg); - dmaerr(" DMA Global Registers:\n"); - dmaerr(" GCFG[%08x]: %08x\n", dmac->base + SAM_DMAC_GCFG_OFFSET, regs->gcfg); - dmaerr(" EN[%08x]: %08x\n", dmac->base + SAM_DMAC_EN_OFFSET, regs->en); - dmaerr(" SREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_SREQ_OFFSET, regs->sreq); - dmaerr(" CREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_CREQ_OFFSET, regs->creq); - dmaerr(" LAST[%08x]: %08x\n", dmac->base + SAM_DMAC_LAST_OFFSET, regs->last); - dmaerr(" EBCIMR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCIMR_OFFSET, regs->ebcimr); - dmaerr(" EBCISR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCISR_OFFSET, regs->ebcisr); - dmaerr(" CHSR[%08x]: %08x\n", dmac->base + SAM_DMAC_CHSR_OFFSET, regs->chsr); - dmaerr(" WPMR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPMR_OFFSET, regs->wpmr); - dmaerr(" WPSR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPSR_OFFSET, regs->wpsr); - dmaerr(" DMA Channel Registers:\n"); - dmaerr(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SADDR_OFFSET, regs->saddr); - dmaerr(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DADDR_OFFSET, regs->daddr); - dmaerr(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DSCR_OFFSET, regs->dscr); - dmaerr(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLA_OFFSET, regs->ctrla); - dmaerr(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLB_OFFSET, regs->ctrlb); - dmaerr(" CFG[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CFG_OFFSET, regs->cfg); - dmaerr(" SPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SPIP_OFFSET, regs->spip); - dmaerr(" DPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DPIP_OFFSET, regs->dpip); + dmainfo("%s\n", msg); + dmainfo(" DMA Global Registers:\n"); + dmainfo(" GCFG[%08x]: %08x\n", dmac->base + SAM_DMAC_GCFG_OFFSET, regs->gcfg); + dmainfo(" EN[%08x]: %08x\n", dmac->base + SAM_DMAC_EN_OFFSET, regs->en); + dmainfo(" SREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_SREQ_OFFSET, regs->sreq); + dmainfo(" CREQ[%08x]: %08x\n", dmac->base + SAM_DMAC_CREQ_OFFSET, regs->creq); + dmainfo(" LAST[%08x]: %08x\n", dmac->base + SAM_DMAC_LAST_OFFSET, regs->last); + dmainfo(" EBCIMR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCIMR_OFFSET, regs->ebcimr); + dmainfo(" EBCISR[%08x]: %08x\n", dmac->base + SAM_DMAC_EBCISR_OFFSET, regs->ebcisr); + dmainfo(" CHSR[%08x]: %08x\n", dmac->base + SAM_DMAC_CHSR_OFFSET, regs->chsr); + dmainfo(" WPMR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPMR_OFFSET, regs->wpmr); + dmainfo(" WPSR[%08x]: %08x\n", dmac->base + SAM_DMAC_WPSR_OFFSET, regs->wpsr); + dmainfo(" DMA Channel Registers:\n"); + dmainfo(" SADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SADDR_OFFSET, regs->saddr); + dmainfo(" DADDR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DADDR_OFFSET, regs->daddr); + dmainfo(" DSCR[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DSCR_OFFSET, regs->dscr); + dmainfo(" CTRLA[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLA_OFFSET, regs->ctrla); + dmainfo(" CTRLB[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CTRLB_OFFSET, regs->ctrlb); + dmainfo(" CFG[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_CFG_OFFSET, regs->cfg); + dmainfo(" SPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_SPIP_OFFSET, regs->spip); + dmainfo(" DPIP[%08x]: %08x\n", dmach->base + SAM_DMAC_CH_DPIP_OFFSET, regs->dpip); } #endif /* CONFIG_DEBUG_DMA */ #endif /* CONFIG_SAMA5_DMAC0 || CONFIG_SAMA5_DMAC1 */ diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index b39d925c8ba..cdd86c208b7 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -112,7 +112,7 @@ /* Debug options */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_SAMA5_EHCI_REGDEBUG #endif @@ -628,7 +628,7 @@ static uint32_t sam_swap32(uint32_t value) static void sam_printreg(volatile uint32_t *regaddr, uint32_t regval, bool iswrite) { - _llerr("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); + uinfo("%08x%s%08x\n", (uintptr_t)regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -679,7 +679,7 @@ static void sam_checkreg(volatile uint32_t *regaddr, uint32_t regval, bool iswri { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } @@ -1268,13 +1268,13 @@ static int sam_qh_flush(struct sam_qh_s *qh) #ifdef CONFIG_SAMA5_EHCI_REGDEBUG static void sam_qtd_print(struct sam_qtd_s *qtd) { - uerr(" QTD[%p]:\n", qtd); - uerr(" hw:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], - qtd->hw.bpl[3], qtd->hw.bpl[4]); + uinfo(" QTD[%p]:\n", qtd); + uinfo(" hw:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + qtd->hw.nqp, qtd->hw.alt, qtd->hw.token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + qtd->hw.bpl[0], qtd->hw.bpl[1], qtd->hw.bpl[2], + qtd->hw.bpl[3], qtd->hw.bpl[4]); } #endif @@ -1292,30 +1292,30 @@ static void sam_qh_print(struct sam_qh_s *qh) struct sam_epinfo_s *epinfo; struct ehci_overlay_s *overlay; - uerr("QH[%p]:\n", qh); - uerr(" hw:\n"); - uerr(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", - qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); + uinfo("QH[%p]:\n", qh); + uinfo(" hw:\n"); + uinfo(" hlp: %08x epchar: %08x epcaps: %08x cqp: %08x\n", + qh->hw.hlp, qh->hw.epchar, qh->hw.epcaps, qh->hw.cqp); overlay = &qh->hw.overlay; - uerr(" overlay:\n"); - uerr(" nqp: %08x alt: %08x token: %08x\n", - overlay->nqp, overlay->alt, overlay->token); - uerr(" bpl: %08x %08x %08x %08x %08x\n", - overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], - overlay->bpl[3], overlay->bpl[4]); + uinfo(" overlay:\n"); + uinfo(" nqp: %08x alt: %08x token: %08x\n", + overlay->nqp, overlay->alt, overlay->token); + uinfo(" bpl: %08x %08x %08x %08x %08x\n", + overlay->bpl[0], overlay->bpl[1], overlay->bpl[2], + overlay->bpl[3], overlay->bpl[4]); - uerr(" fqp:\n", qh->fqp); + uinfo(" fqp:\n", qh->fqp); epinfo = qh->epinfo; - uerr(" epinfo[%p]:\n", epinfo); + uinfo(" epinfo[%p]:\n", epinfo); if (epinfo) { - uerr(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", - epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, - epinfo->xfrtype, epinfo->maxpacket); - uerr(" Toggle=%d iocwait=%d speed=%d result=%d\n", - epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); + uinfo(" EP%d DIR=%s FA=%08x TYPE=%d MaxPacket=%d\n", + epinfo->epno, epinfo->dirin ? "IN" : "OUT", epinfo->devaddr, + epinfo->xfrtype, epinfo->maxpacket); + uinfo(" Toggle=%d iocwait=%d speed=%d result=%d\n", + epinfo->toggle, epinfo->iocwait, epinfo->speed, epinfo->result); } } #endif diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 04267d09a83..553d15f51b9 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -223,7 +223,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_SAMA5_EMACA_REGDEBUG #endif @@ -335,7 +335,7 @@ static uint8_t g_rxbuffer[CONFIG_SAMA5_EMAC_NRXBUFFERS * EMAC_RX_UNITSIZE] ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_EMACA_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_EMACA_REGDEBUG static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, uintptr_t address); static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr); @@ -461,7 +461,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -493,7 +493,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + ninfo("%08x->%08x\n", address, regval); } return regval; @@ -514,7 +514,7 @@ static void sam_putreg(struct sam_emac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + ninfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); @@ -1212,7 +1212,7 @@ static void sam_receive(struct sam_emac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); continue; } @@ -1322,7 +1322,7 @@ static void sam_receive(struct sam_emac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } } } @@ -1584,7 +1584,7 @@ static int sam_emac_interrupt(int irq, void *context) if ((pending & EMAC_INT_PFR) != 0) { - nllerr("Pause frame received\n"); + nllwarn("WARNING: Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -1594,7 +1594,7 @@ static int sam_emac_interrupt(int irq, void *context) if ((pending & EMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllwarn("WARNING: Pause TO!\n"); } #endif @@ -1624,7 +1624,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) { struct sam_emac_s *priv = (struct sam_emac_s *)arg; - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); /* Then reset the hardware. Just take the interface down, then back * up again. @@ -1699,9 +1699,9 @@ static int sam_ifup(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; int ret; - nllerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Configure the EMAC interface for normal operation. */ @@ -1775,7 +1775,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + ninfo("Taking the network down\n"); /* Disable the EMAC interrupt */ diff --git a/arch/arm/src/sama5/sam_emacb.c b/arch/arm/src/sama5/sam_emacb.c index 66155406e92..6dab62599f4 100644 --- a/arch/arm/src/sama5/sam_emacb.c +++ b/arch/arm/src/sama5/sam_emacb.c @@ -295,7 +295,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_SAMA5_EMACB_REGDEBUG #endif @@ -820,7 +820,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -853,7 +853,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset) #ifdef CONFIG_SAMA5_EMACB_REGDEBUG if (sam_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + ninfo("%08x->%08x\n", regaddr, regval); } #endif @@ -877,7 +877,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, #ifdef CONFIG_SAMA5_EMACB_REGDEBUG if (sam_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + ninfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1575,7 +1575,7 @@ static void sam_receive(struct sam_emac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); continue; } @@ -1685,7 +1685,7 @@ static void sam_receive(struct sam_emac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } } } @@ -1972,7 +1972,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) if ((pending & EMAC_INT_PFNZ) != 0) { - nllerr("Pause frame received\n"); + nllwarn("WARNING: Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -1982,7 +1982,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv) if ((pending & EMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllwarn("WARNING: Pause TO!\n"); } #endif } @@ -2147,7 +2147,7 @@ static int sam_emac1_interrupt(int irq, void *context) static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) { - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); /* Reset the hardware. Just take the interface down, then back up again. */ @@ -2377,15 +2377,15 @@ static int sam_ifup(struct net_driver_s *dev) int ret; #ifdef CONFIG_NET_IPv4 - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); #endif #ifdef CONFIG_NET_IPv6 - nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], - dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], - dev->d_ipv6addr[6], dev->d_ipv6addr[7]); + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); #endif /* Configure the EMAC interface for normal operation. */ @@ -2460,7 +2460,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + nllinfo("Taking the network down\n"); /* Disable the EMAC interrupt */ diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index 3bf136c3104..66472d36835 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -149,7 +149,7 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_NET_INFO # undef CONFIG_SAMA5_GMAC_REGDEBUG #endif @@ -392,7 +392,7 @@ static bool sam_checkreg(struct sam_gmac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -424,7 +424,7 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t address) if (sam_checkreg(priv, false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + ninfo("%08x->%08x\n", address, regval); } return regval; @@ -445,7 +445,7 @@ static void sam_putreg(struct sam_gmac_s *priv, uintptr_t address, { if (sam_checkreg(priv, true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + ninfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); @@ -1142,7 +1142,7 @@ static void sam_receive(struct sam_gmac_s *priv) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); continue; } @@ -1252,7 +1252,7 @@ static void sam_receive(struct sam_gmac_s *priv) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); } } } @@ -1536,7 +1536,7 @@ static int sam_gmac_interrupt(int irq, void *context) if ((pending & GMAC_INT_PFNZ) != 0) { - nllerr("Pause frame received\n"); + nllwarn("WARNING: Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -1546,7 +1546,7 @@ static int sam_gmac_interrupt(int irq, void *context) if ((pending & GMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllwarn("WARNING: Pause TO!\n"); } #endif @@ -1576,7 +1576,7 @@ static void sam_txtimeout(int argc, uint32_t arg, ...) { struct sam_gmac_s *priv = (struct sam_gmac_s *)arg; - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); /* Then reset the hardware. Just take the interface down, then back * up again. @@ -1651,9 +1651,9 @@ static int sam_ifup(struct net_driver_s *dev) struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private; int ret; - nllerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Configure the GMAC interface for normal operation. */ @@ -1730,7 +1730,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_gmac_s *priv = (struct sam_gmac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + ninfo("Taking the network down\n"); /* Disable the GMAC interrupt */ diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index 026424fae74..db8054fe2d4 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -79,6 +79,10 @@ /* Configuration ************************************************************/ +#ifndef CONFIG_DEBUG_MEMCARD_INFO +# undef CONFIG_SAMA5_HSMCI_REGDEBUG +#endif + #if defined(ATSAMA5D3) /* The SAMA5D3 has three HSMCI blocks: HSMCI0-2. HSMCI0 requires DMAC0 * support, HSMCI1-2 require DMAC1 support. @@ -725,7 +729,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + mcinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -758,7 +762,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset) #ifdef CONFIG_SAMA5_HSMCI_REGDEBUG if (sam_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + mcinfo("%08x->%08x\n", address, value); } #endif @@ -781,7 +785,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value, #ifdef CONFIG_SAMA5_HSMCI_REGDEBUG if (sam_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + mcinfo("%08x<-%08x\n", address, value); } #endif @@ -1003,23 +1007,23 @@ static void sam_hsmcisample(struct sam_dev_s *priv, static void sam_hsmcidump(struct sam_dev_s *priv, struct sam_hsmciregs_s *regs, const char *msg) { - ferr("HSMCI Registers: %s\n", msg); - ferr(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); - ferr(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); - ferr(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); - ferr(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); - ferr(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); - ferr(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); - ferr(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); - ferr(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); - ferr(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); - ferr(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); - ferr(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); - ferr(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); - ferr(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); - ferr(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); - ferr(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); - ferr(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); + lcdinfo("HSMCI Registers: %s\n", msg); + lcdinfo(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); + lcdinfo(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); + lcdinfo(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); + lcdinfo(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); + lcdinfo(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); + lcdinfo(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); + lcdinfo(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); + lcdinfo(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); + lcdinfo(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); + lcdinfo(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); + lcdinfo(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); + lcdinfo(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); + lcdinfo(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); + lcdinfo(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); + lcdinfo(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); + lcdinfo(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); } #endif @@ -1093,7 +1097,7 @@ static void sam_xfrdumpone(struct sam_dev_s *priv, int index, } else { - ferr("%s: Not collected\n", msg); + lcdinfo("%s: Not collected\n", msg); } } #endif @@ -2253,7 +2257,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, { /* Some fatal error has occurred */ - ferr("ERROR: sr %08x\n", sr); + lcderr("ERROR: sr %08x\n", sr); return -EIO; } else if ((sr & HSMCI_INT_TXRDY) != 0) @@ -2388,7 +2392,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. Was the error some kind of timeout? */ - ferr("ERROR: cmd: %08x events: %08x SR: %08x\n", + lcderr("ERROR: cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -2418,8 +2422,8 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) } else if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", - cmd, priv->cmdrmask, sr); + lcderr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", + cmd, priv->cmdrmask, sr); priv->wkupevent = SDIOWAIT_TIMEOUT; return -ETIMEDOUT; @@ -2493,7 +2497,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + lcderr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2505,7 +2509,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + lcderr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2555,7 +2559,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + lcderr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2746,7 +2750,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + lcderr("ERROR: wd_start failed: %d\n", ret); } } @@ -3150,7 +3154,7 @@ static void sam_callback(void *arg) { /* NOTE: Currently, work_cancel only returns success */ - ferr("ERROR: Failed to cancel work: %d\n", ret); + lcderr("ERROR: Failed to cancel work: %d\n", ret); } fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); @@ -3160,7 +3164,7 @@ static void sam_callback(void *arg) { /* NOTE: Currently, work_queue only returns success */ - ferr("ERROR: Failed to schedule work: %d\n", ret); + lcderr("ERROR: Failed to schedule work: %d\n", ret); } } @@ -3199,7 +3203,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) * for now, an* HSMCI peripheral does correspond to a slot. */ - ferr("slotno: %d\n", slotno); + lcdinfo("slotno: %d\n", slotno); #ifdef CONFIG_SAMA5_HSMCI0 if (slotno == 0) diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index eef9767adfc..3befc8fec63 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -492,7 +492,7 @@ /* Debug */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_LCD_INFO # undef CONFIG_SAMA5_LCDC_REGDEBUG #endif @@ -666,7 +666,7 @@ struct sam_lcdc_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_LCDC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_LCDC_REGDEBUG static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address); static uint32_t sam_getreg(uintptr_t addr); static void sam_putreg(uintptr_t addr, uint32_t val); @@ -977,10 +977,6 @@ static const uintptr_t g_layerclut[LCDC_NLAYERS] = }; #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -1021,7 +1017,7 @@ static bool sam_checkreg(bool wr, uint32_t regval, uintptr_t address) { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", g_lcdc.ntimes); + lcdinfo("...[Repeats %d times]...\n", g_lcdc.ntimes); } /* Save information about the new access */ @@ -1053,7 +1049,7 @@ static uint32_t sam_getreg(uintptr_t address) if (sam_checkreg(false, regval, address)) { - _llerr("%08x->%08x\n", address, regval); + lcdinfo("%08x->%08x\n", address, regval); } return regval; @@ -1073,7 +1069,7 @@ static void sam_putreg(uintptr_t address, uint32_t regval) { if (sam_checkreg(true, regval, address)) { - _llerr("%08x<-%08x\n", address, regval); + lcdinfo("%08x<-%08x\n", address, regval); } putreg32(regval, address); @@ -1101,14 +1097,14 @@ static void sam_wait_lcdstatus(uint32_t mask, uint32_t value) static int sam_base_getvideoinfo(struct fb_vtable_s *vtable, struct fb_videoinfo_s *vinfo) { - ginfo("vtable=%p vinfo=%p\n", vtable, vinfo); + lcdinfo("vtable=%p vinfo=%p\n", vtable, vinfo); if (vtable && vinfo) { memcpy(vinfo, &g_base_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; } - gerr("ERROR: Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1119,7 +1115,7 @@ static int sam_base_getvideoinfo(struct fb_vtable_s *vtable, static int sam_base_getplaneinfo(struct fb_vtable_s *vtable, int planeno, struct fb_planeinfo_s *pinfo) { - ginfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); + lcdinfo("vtable=%p planeno=%d pinfo=%p\n", vtable, planeno, pinfo); if (vtable && planeno == 0 && pinfo) { pinfo->fbmem = (void *)LAYER_BASE.framebuffer; @@ -1130,7 +1126,7 @@ static int sam_base_getplaneinfo(struct fb_vtable_s *vtable, int planeno, return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } @@ -1166,27 +1162,27 @@ static int sam_base_putcmap(struct fb_vtable_s *vtable, static int sam_hcr_getcursor(struct fb_vtable_s *vtable, struct fb_cursorattrib_s *attrib) { - ginfo("vtable=%p attrib=%p\n", vtable, attrib); + lcdinfo("vtable=%p attrib=%p\n", vtable, attrib); if (vtable && attrib) { #ifdef CONFIG_FB_HWCURSORIMAGE attrib->fmt = SAMA5_HCR_COLOR_FMT; #endif - ginfo("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); + lcdinfo("pos: (x=%d, y=%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); attrib->pos = g_lcdc.cpos; #ifdef CONFIG_FB_HWCURSORSIZE attrib->mxsize.h = CONFIG_SAMA5_LCDC_HCR_HEIGHT; attrib->mxsize.w = CONFIG_SAMA5_LCDC_HCR_WIDTH; - ginfo("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); + lcdinfo("size: (h=%d, w=%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); attrib->size = g_lcdc.csize; #endif return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -1199,26 +1195,26 @@ static int sam_hcr_getcursor(struct fb_vtable_s *vtable, static int sam_hcr_setcursor(struct fb_vtable_s *vtable, struct fb_setcursor_s *setttings) { - ginfo("vtable=%p setttings=%p\n", vtable, setttings); + lcdinfo("vtable=%p setttings=%p\n", vtable, setttings); if (vtable && setttings) { - ginfo("flags: %02x\n", settings->flags); + lcdinfo("flags: %02x\n", settings->flags); if ((flags & FB_CUR_SETPOSITION) != 0) { g_lcdc.cpos = settings->pos; - ginfo("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); + lcdinfo("pos: (h:%d, w:%d)\n", g_lcdc.cpos.x, g_lcdc.cpos.y); } #ifdef CONFIG_FB_HWCURSORSIZE if ((flags & FB_CUR_SETSIZE) != 0) { g_lcdc.csize = settings->size; - ginfo("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); + lcdinfo("size: (h:%d, w:%d)\n", g_lcdc.csize.h, g_lcdc.csize.w); } #endif #ifdef CONFIG_FB_HWCURSORIMAGE if ((flags & FB_CUR_SETIMAGE) != 0) { - ginfo("image: (h:%d, w:%d) @ %p\n", + lcdinfo("image: (h:%d, w:%d) @ %p\n", settings->img.height, settings->img.width, settings->img.image); } @@ -1226,7 +1222,7 @@ static int sam_hcr_setcursor(struct fb_vtable_s *vtable, return OK; } - gerr("Returning EINVAL\n"); + lcderr("ERROR: Returning EINVAL\n"); return -EINVAL; } #endif @@ -1294,11 +1290,11 @@ static void sam_dmasetup(int lid, struct sam_dscr_s *dscr, uint8_t *buffer) #if defined(CONFIG_DEBUG_GRAPHICS) && defined(CONFIG_DEBUG_INFO) /* Dump the DMA setup */ - ginfo("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n", - dscr->addr, dscr->ctrl, dscr->next); - ginfo("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n", - lid, sam_getreg(g_layerhead[lid]), sam_getreg(g_layeraddr[lid]), - sam_getreg(g_layerctrl[lid]), sam_getreg(g_layernext[lid])); + lcdinfo("DMA descriptor: addr=%08x ctrl=%08x next=%08x\n", + dscr->addr, dscr->ctrl, dscr->next); + lcdinfo("DMA registers[%d]: head=%08x addr=%08x ctrl=%08x next=%08x\n", + lid, sam_getreg(g_layerhead[lid]), sam_getreg(g_layeraddr[lid]), + sam_getreg(g_layerctrl[lid]), sam_getreg(g_layernext[lid])); #endif } @@ -1379,8 +1375,8 @@ static int sam_setclut(struct sam_layer_s *layer, unsigned int end; int i; - ginfo("layer=%d cmap=%p first=%d len=%d\n", - layer->lid, cmap, cmap->first, cmap->len); + lcdinfo("layer=%d cmap=%p first=%d len=%d\n", + layer->lid, cmap, cmap->first, cmap->len); DEBUGASSERT(layer && cmap); @@ -1391,7 +1387,7 @@ static int sam_setclut(struct sam_layer_s *layer, if (offset >= SAM_LCDC_NCLUT) { - gerr("ERROR: CLUT offset is out of range: %d\n", offset); + lcderr("ERROR: CLUT offset is out of range: %d\n", offset); return -EINVAL; } @@ -1460,7 +1456,7 @@ static int sam_getclut(struct sam_layer_s *layer, uintptr_t regval; int i; - ginfo("layer=%d cmap=%p first=%d len=%d\n", + lcdinfo("layer=%d cmap=%p first=%d len=%d\n", layer->lid, cmap, layer->offset, layer->nclut); DEBUGASSERT(layer && cmap); @@ -1514,7 +1510,7 @@ static void sam_pio_config(void) { int i; - ginfo("Configuring pins\n"); + lcdinfo("Configuring pins\n"); /* Configure each pin */ @@ -2915,7 +2911,7 @@ int up_fbinitialize(int display) uint32_t regval; #endif - ginfo("Entry\n"); + lcdinfo("Entry\n"); /* Configure layer layer structures, DMA descriptor memory, and * framebuffers @@ -2931,7 +2927,7 @@ int up_fbinitialize(int display) sam_pio_config(); - ginfo("Configuring the LCD controller\n"); + lcdinfo("Configuring the LCD controller\n"); /* Enable the LCD peripheral clock */ @@ -2959,7 +2955,7 @@ int up_fbinitialize(int display) /* And turn the LCD on */ - ginfo("Enabling the display\n"); + lcdinfo("Enabling the display\n"); sam_lcd_enable(); /* Display base layer */ @@ -3012,7 +3008,7 @@ int up_fbinitialize(int display) FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane) { - ginfo("vplane: %d\n", vplane); + lcdinfo("vplane: %d\n", vplane); if (vplane == 0) { return (struct fb_vtable_s *)&g_base_vtable; @@ -3062,8 +3058,8 @@ void sam_lcdclear(nxgl_mxpixel_t color) uint16_t *dest = (uint16_t *)LAYER_BASE.framebuffer; int i; - ginfo("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n", - color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); + lcdinfo("Clearing display: BPP=16 color=%04x framebuffer=%08x size=%d\n", + color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint16_t)) { @@ -3076,8 +3072,8 @@ void sam_lcdclear(nxgl_mxpixel_t color) uint8_t b; int i; - ginfo("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n", - color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); + lcdinfo("Clearing display: BPP=24 color=%06x framebuffer=%08x size=%d\n", + color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); b = color & 0xff; g = (color >> 8) & 0xff; @@ -3093,8 +3089,8 @@ void sam_lcdclear(nxgl_mxpixel_t color) uint32_t *dest = (uint32_t *)LAYER_BASE.framebuffer; int i; - ginfo("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n", - color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); + lcdinfo("Clearing display: BPP=32 color=%08x framebuffer=%08x size=%d\n", + color, LAYER_BASE.framebuffer, SAMA5_BASE_FBSIZE); for (i = 0; i < SAMA5_BASE_FBSIZE; i += sizeof(uint32_t)) { diff --git a/arch/arm/src/sama5/sam_memories.c b/arch/arm/src/sama5/sam_memories.c index 6588309b880..54c8e65b561 100644 --- a/arch/arm/src/sama5/sam_memories.c +++ b/arch/arm/src/sama5/sam_memories.c @@ -766,7 +766,7 @@ uintptr_t sam_physregaddr(uintptr_t virtregaddr) * address */ - _err("Bad virtual address: %08lx\n", virtregaddr); + serr("ERROR: Bad virtual address: %08lx\n", virtregaddr); DEBUGPANIC(); return virtregaddr; } @@ -925,7 +925,7 @@ uintptr_t sam_physramaddr(uintptr_t virtramaddr) if (virtramaddr != 0) { - _err("Bad virtual address: %08lx\n", virtramaddr); + serr("ERROR: Bad virtual address: %08lx\n", virtramaddr); DEBUGPANIC(); } @@ -1058,7 +1058,7 @@ uintptr_t sam_virtramaddr(uintptr_t physramaddr) if (physramaddr != 0) { - _err("Bad physical address: %08lx\n|", physramaddr); + serr("ERROR: Bad physical address: %08lx\n|", physramaddr); DEBUGPANIC(); } diff --git a/arch/arm/src/sama5/sam_nand.c b/arch/arm/src/sama5/sam_nand.c index 6cb56fea97e..f063f22fb2b 100644 --- a/arch/arm/src/sama5/sam_nand.c +++ b/arch/arm/src/sama5/sam_nand.c @@ -1163,7 +1163,7 @@ static void nand_dma_sampleinit(struct sam_nandcs_s *priv) #ifdef CONFIG_SAMA5_NAND_DMADEBUG static void nand_dma_sampledone(struct sam_nandcs_s *priv, int result) { - _llerr("result: %d\n", result); + finfo("result: %d\n", result); /* Sample the final registers */ @@ -2098,7 +2098,7 @@ static int nand_readpage_pmecc(struct sam_nandcs_s *priv, off_t block, { /* Yes.. clear sector errors */ - ferr("Block=%d page=%d has been erased: %08x\n", + finfo("Block=%d page=%d has been erased: %08x\n", block, page, regval); regval = 0; } @@ -2983,7 +2983,7 @@ struct mtd_dev_s *sam_nand_initialize(int cs) ret = irq_attach(SAM_IRQ_HSMC, hsmc_interrupt); if (ret < 0) { - ferr("Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC); + ferr("ERROR: Failed to attach HSMC IRQ (%d)", SAM_IRQ_HSMC); return NULL; } #endif @@ -3088,7 +3088,7 @@ bool nand_checkreg(bool wr, uintptr_t regaddr, uint32_t regval) { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", g_nand.ntimes); + finfo("...[Repeats %d times]...\n", g_nand.ntimes); } /* Save information about the new access */ diff --git a/arch/arm/src/sama5/sam_nand.h b/arch/arm/src/sama5/sam_nand.h index 81e6cb80034..808b719aa52 100644 --- a/arch/arm/src/sama5/sam_nand.h +++ b/arch/arm/src/sama5/sam_nand.h @@ -259,14 +259,13 @@ /* Debug */ -#if !defined(CONFIG_DEBUG_FEATURES) || !defined(CONFIG_DEBUG_FS) -# undef CONFIG_DEBUG_FS +#ifndef defined(CONFIG_DEBUG_FS_INFO # undef CONFIG_SAMA5_NAND_DMADEBUG # undef CONFIG_SAMA5_NAND_REGDEBUG # undef CONFIG_SAMA5_NAND_DUMP #endif -#if !defined(CONFIG_SAMA5_NAND_DMA) || !defined(CONFIG_DEBUG_DMA) +#if !defined(CONFIG_SAMA5_NAND_DMA) || !defined(CONFIG_DEBUG_DMA_INFO) # undef CONFIG_SAMA5_NAND_DMADEBUG #endif @@ -518,7 +517,7 @@ static inline uint32_t nand_getreg(uintptr_t regaddr) #ifdef CONFIG_SAMA5_NAND_REGDEBUG if (nand_checkreg(false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + sinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -538,7 +537,7 @@ static inline void nand_putreg(uintptr_t regaddr, uint32_t regval) #ifdef CONFIG_SAMA5_NAND_REGDEBUG if (nand_checkreg(true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + sinfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index 76899223c60..bd3ec0b233b 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -151,7 +151,7 @@ /* Debug */ -#ifndef CONFIG_DEBUG_FEATURES +#ifndef CONFIG_DEBUG_USB_INFO # undef CONFIG_SAMA5_OHCI_REGDEBUG #endif @@ -505,10 +505,6 @@ static struct sam_gtd_s g_tdalloc[SAMA5_OHCI_NTDS] static uint8_t g_bufalloc[SAM_BUFALLOC] __attribute__ ((aligned (SAMA5_DMA_ALIGN))); -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -524,7 +520,7 @@ static uint8_t g_bufalloc[SAM_BUFALLOC] #ifdef CONFIG_SAMA5_OHCI_REGDEBUG static void sam_printreg(uint32_t addr, uint32_t val, bool iswrite) { - _llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + uinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -574,7 +570,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } diff --git a/arch/arm/src/sama5/sam_pmecc.c b/arch/arm/src/sama5/sam_pmecc.c index d055d0b6b33..0339068c4fc 100644 --- a/arch/arm/src/sama5/sam_pmecc.c +++ b/arch/arm/src/sama5/sam_pmecc.c @@ -632,7 +632,7 @@ static uint32_t pmecc_errorcorrection(uintptr_t sectorbase, if (bytepos < sectorsz + nand_getreg(SAM_HSMC_PMECCSADDR)) { - ferr("Correct error bit @[Byte %d, Bit %d]\n", + fwarn("WARNING: Correct error bit @[Byte %d, Bit %d]\n", (int)bytepos, (int)bitpos); if (*(uint8_t *)(sectorbase + bytepos) & (1 << bitpos)) @@ -870,7 +870,7 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize) bcherr512 = pmecc_bcherr512(nsectors512, eccsize); if (bcherr512 < 0) { - ferr("WARNING: Cannot realize 512B sectors\n"); + fwarn("WARNING: Cannot realize 512B sectors\n"); } else { @@ -895,7 +895,7 @@ static int pmecc_pagelayout(uint16_t datasize, uint16_t eccsize) if (bcherr1k < 0) { - ferr("WARNING: Cannot realize 1KB sectors\n"); + fwarn("WARNING: Cannot realize 1KB sectors\n"); } else { diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 4aac3affa81..0de1d91dea0 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -65,6 +65,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_PWM_INFO +# undef CONFIG_SAMA5_PWM_REGDEBUG +#endif + /* Currently, we support only a single PWM peripheral. However, the hooks * are in place to support multiple PWM peripherals. */ @@ -689,7 +694,7 @@ static bool pwm_checkreg(FAR struct sam_pwm_s *pwm, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", pwm->count); + pwminfo("...[Repeats %d times]...\n", pwm->count); } /* Save information about the new access */ @@ -733,7 +738,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset) #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(&g_pwm, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + pwminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -750,7 +755,7 @@ static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset) #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(pwm, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + pwminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -789,7 +794,7 @@ static uint32_t pwm_chan_getreg(struct sam_pwm_chan_s *chan, int offset) if (pwm_checkreg(chan->pwm, false, regval, regaddr)) #endif { - _llerr("%08x->%08x\n", regaddr, regval); + pwminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -820,7 +825,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(&g_pwm, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + pwminfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -833,7 +838,7 @@ static void pwm_putreg(struct sam_pwm_chan_s *chan, int offset, #ifdef CONFIG_SAMA5_PWM_REGDEBUG if (pwm_checkreg(pwm, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + pwminfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -869,7 +874,7 @@ static void pwm_chan_putreg(struct sam_pwm_chan_s *chan, int offset, if (pwm_checkreg(chan->pwm, true, regval, regaddr)) #endif { - _llerr("%08x<-%08x\n", regaddr, regval); + pwminfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_rtc.c b/arch/arm/src/sama5/sam_rtc.c index 16c4a4f2953..d710ff711f6 100644 --- a/arch/arm/src/sama5/sam_rtc.c +++ b/arch/arm/src/sama5/sam_rtc.c @@ -265,7 +265,7 @@ static int rtc_interrupt(int irq, void *context) ret = work_queue(LPWORK, &g_alarmwork, rtc_worker, NULL, 0); if (ret < 0) { - rtcllerr("ERRPR: work_queue failed: %d\n", ret); + rtcllerr("ERROR: work_queue failed: %d\n", ret); } /* Disable any further alarm interrupts */ diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index 33cd3cb93e2..0386fcc6818 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -90,6 +90,10 @@ # define CONFIG_SAMA5_SPI_DMATHRESHOLD 4 #endif +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMA5_SPI_REGDEBUG +#endif + #ifdef CONFIG_SAMA5_SPI_DMA # if defined(CONFIG_SAMA5_SPI0) && defined(CONFIG_SAMA5_DMAC0) @@ -409,7 +413,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", spi->ntimes); + spiinfo("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -443,7 +447,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAMA5_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -466,7 +470,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAMA5_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif @@ -1044,7 +1048,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) spics->frequency = frequency; spics->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index 46c564b66e3..ff50c3988e8 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -703,7 +703,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->count); + i2sinfo("...[Repeats %d times]...\n", priv->count); } /* Save information about the new access */ @@ -737,7 +737,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, #ifdef CONFIG_SAMA5_SSC_REGDEBUG if (ssc_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + i2sinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -760,7 +760,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset, #ifdef CONFIG_SAMA5_SSC_REGDEBUG if (ssc_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + i2sinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1090,7 +1090,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv, #if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_RX) static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ @@ -1155,7 +1155,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) #if defined(CONFIG_SAMA5_SSC_DMADEBUG) && defined(SSC_HAVE_TX) static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ diff --git a/arch/arm/src/sama5/sam_tc.c b/arch/arm/src/sama5/sam_tc.c index 9ea38a333d3..fc0bc9c8766 100644 --- a/arch/arm/src/sama5/sam_tc.c +++ b/arch/arm/src/sama5/sam_tc.c @@ -75,6 +75,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_SAMA5_TC_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -501,20 +505,20 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = tc->base; - _llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); - _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + tminfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); + tminfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - _llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); - _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + tminfo("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); + tminfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - _llerr(" RA: %08x RB: %08x RC: %08x SR: %08x\n", + tminfo(" RA: %08x RB: %08x RC: %08x SR: %08x\n", getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_SR_OFFSET)); - _llerr(" IMR: %08x\n", + tminfo(" IMR: %08x\n", getreg32(base+SAM_TC_IMR_OFFSET)); } #endif @@ -558,7 +562,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", tc->ntimes); + tminfo("...[Repeats %d times]...\n", tc->ntimes); } /* Save information about the new access */ @@ -593,7 +597,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -617,7 +621,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tminfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -641,7 +645,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tminfo("%08x->%08x\n", regaddr, regval); } #endif @@ -664,7 +668,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAMA5_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tminfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index de28c0a953b..9961cbee74c 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -644,7 +644,7 @@ static void sam_tsd_bottomhalf(void *arg) if (xraw == 0 || xraw >= xscale || yraw == 0 || yraw > yscale) { - ierr("Discarding: x %d:%d y %d:%d\n", xraw, xscale); + iwarn("WARNING: Discarding: x %d:%d y %d:%d\n", xraw, xscale); goto ignored; } @@ -799,7 +799,7 @@ static int sam_tsd_schedule(struct sam_tsd_s *priv) ret = work_queue(HPWORK, &priv->work, sam_tsd_bottomhalf, priv, 0); if (ret != 0) { - illerr("Failed to queue work: %d\n", ret); + illerr("ERROR: Failed to queue work: %d\n", ret); } return OK; diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index 095fb7e895e..a15ec4e1b1e 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -95,6 +95,10 @@ # define CONFIG_SAMA5_TWI3_FREQUENCY 100000 #endif +#ifndef CONFIG_DEBUG_I2C_INFO +# undef CONFIG_SAMA5_TWI_REGDEBUG +#endif + /* Driver internal definitions *************************************************/ /* If verbose I2C debug output is enabled, then allow more time before we declare * a timeout. The debug output from twi_interrupt will really slow things down! @@ -369,7 +373,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + i2cinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -401,7 +405,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + i2cinfo("%08x->%08x\n", address, value); } return value; @@ -422,7 +426,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + i2cinfo("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index a5dba4368d9..b7e4b60357f 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -91,11 +91,7 @@ # define CONFIG_SAMA5_UDPHS_NDTDS 8 #endif -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_FEATURES +#ifdef CONFIG_DEBUG_USB_INFO # undef CONFIG_SAMA5_UDPHS_REGDEBUG #endif @@ -671,7 +667,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAMA5_UDPHS_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - _llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -722,7 +718,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } @@ -802,31 +798,31 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno) { /* Global Registers */ - _llerr("Global Register:\n"); - _llerr(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL)); - _llerr(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM)); - _llerr(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN)); - _llerr(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA)); - _llerr(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST)); + uinfo("Global Register:\n"); + uinfo(" CTRL: %04x\n", sam_getreg(SAM_UDPHS_CTRL)); + uinfo(" FNUM: %04x\n", sam_getreg(SAM_UDPHS_FNUM)); + uinfo(" IEN: %04x\n", sam_getreg(SAM_UDPHS_IEN)); + uinfo(" INSTA: %04x\n", sam_getreg(SAM_UDPHS_INTSTA)); + uinfo(" TST: %04x\n", sam_getreg(SAM_UDPHS_TST)); /* Endpoint registers */ - _llerr("Endpoint %d Register:\n", epno); - _llerr(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno))); - _llerr(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno))); - _llerr(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno))); + uinfo("Endpoint %d Register:\n", epno); + uinfo(" CFG: %04x\n", sam_getreg(SAM_UDPHS_EPTCFG(epno))); + uinfo(" CTL: %04x\n", sam_getreg(SAM_UDPHS_EPTCTL(epno))); + uinfo(" STA: %04x\n", sam_getreg(SAM_UDPHS_EPTSTA(epno))); - _llerr("DMA %d Register:\n", epno); + uinfo("DMA %d Register:\n", epno); if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) { - _llerr(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno))); - _llerr(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno))); - _llerr(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno))); - _llerr(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno))); + uinfo(" NXTDSC: %04x\n", sam_getreg(SAM_UDPHS_DMANXTDSC(epno))); + uinfo(" ADDRESS: %04x\n", sam_getreg(SAM_UDPHS_DMAADDRESS(epno))); + uinfo(" CONTROL: %04x\n", sam_getreg(SAM_UDPHS_DMACONTROL(epno))); + uinfo(" STATUS: %04x\n", sam_getreg(SAM_UDPHS_DMASTATUS(epno))); } else { - _llerr(" None\n"); + uinfo(" None\n"); } } #endif diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index aa16905888c..26f40860b7c 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -57,6 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_SAMA5_WDT_REGDEBUG +#endif + /* The Watchdog Timer uses the Slow Clock divided by 128 to establish the * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of * 32768 kHz). @@ -104,7 +109,7 @@ struct sam_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else @@ -164,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev; * ****************************************************************************/ -#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr) { static uint32_t prevaddr = 0; @@ -185,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - _llerr("...\n"); + wdinfo("...\n"); } return regval; @@ -202,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - _llerr("%08x->%048\n", regaddr, regval); + wdinfo("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -227,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr) * ****************************************************************************/ -#if defined(CONFIG_SAMA5_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMA5_WDT_REGDEBUG static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + wdinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -449,7 +454,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT) { - wderr("Cannot represent timeout: %d < %d > %d\n", + wderr("ERROR: Cannot represent timeout: %d < %d > %d\n", WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT); return -ERANGE; } diff --git a/arch/arm/src/sama5/sam_xdmac.c b/arch/arm/src/sama5/sam_xdmac.c index 48a69a16e31..ef7238a209c 100644 --- a/arch/arm/src/sama5/sam_xdmac.c +++ b/arch/arm/src/sama5/sam_xdmac.c @@ -807,7 +807,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table, } } - dmaerr("No channel found for pid %d\n", pid); + dmaerr("ERROR: No channel found for pid %d\n", pid); DEBUGPANIC(); return 0x3f; } @@ -2403,7 +2403,7 @@ void sam_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; @@ -2445,7 +2445,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) leave_critical_section(flags); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /**************************************************************************** * Name: sam_dmadump @@ -2458,37 +2458,37 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; struct sam_xdmac_s *xdmac = sam_controller(xdmach); - dmaerr("%s\n", msg); - dmaerr(" DMA Global Registers:\n"); - dmaerr(" GTYPE[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GTYPE_OFFSET, regs->gtype); - dmaerr(" GCFG[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GCFG_OFFSET, regs->gcfg); - dmaerr(" GWAC[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWAC_OFFSET, regs->gwac); - dmaerr(" GIM[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIM_OFFSET, regs->gim); - dmaerr(" GIS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIS_OFFSET, regs->gis); - dmaerr(" GS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GS_OFFSET, regs->gs); - dmaerr(" GRS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GRS_OFFSET, regs->grs); - dmaerr(" GWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWS_OFFSET, regs->gws); - dmaerr(" GSWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GSWS_OFFSET, regs->gsws); - dmaerr(" DMA Channel Registers:\n"); - dmaerr(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); - dmaerr(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis); - dmaerr(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); - dmaerr(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); - dmaerr(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); - dmaerr(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); - dmaerr(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); - dmaerr(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); - dmaerr(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); - dmaerr(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); - dmaerr(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); - dmaerr(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); + dmainfo("%s\n", msg); + dmainfo(" DMA Global Registers:\n"); + dmainfo(" GTYPE[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GTYPE_OFFSET, regs->gtype); + dmainfo(" GCFG[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GCFG_OFFSET, regs->gcfg); + dmainfo(" GWAC[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWAC_OFFSET, regs->gwac); + dmainfo(" GIM[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIM_OFFSET, regs->gim); + dmainfo(" GIS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GIS_OFFSET, regs->gis); + dmainfo(" GS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GS_OFFSET, regs->gs); + dmainfo(" GRS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GRS_OFFSET, regs->grs); + dmainfo(" GWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GWS_OFFSET, regs->gws); + dmainfo(" GSWS[%08x]: %08x\n", xdmac->base + SAM_XDMAC_GSWS_OFFSET, regs->gsws); + dmainfo(" DMA Channel Registers:\n"); + dmainfo(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); + dmainfo(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis); + dmainfo(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); + dmainfo(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); + dmainfo(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); + dmainfo(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); + dmainfo(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); + dmainfo(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); + dmainfo(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); + dmainfo(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); + dmainfo(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); + dmainfo(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ #endif /* CONFIG_SAMA5_XDMAC0 || CONFIG_SAMA5_XDMAC1 */ diff --git a/arch/arm/src/samdl/Kconfig b/arch/arm/src/samdl/Kconfig index a890db6a0fd..28ca29c90c3 100644 --- a/arch/arm/src/samdl/Kconfig +++ b/arch/arm/src/samdl/Kconfig @@ -711,7 +711,7 @@ if SAMDL_HAVE_SPI config SAMDL_SPI_REGDEBUG bool "SPI register-Level Debug" default n - depends on DEBUG_SPI + depends on DEBUG_SPI_INFO ---help--- Enable very low-level register access debug. Depends on DEBUG_SPI. diff --git a/arch/arm/src/samdl/sam_dmac.c b/arch/arm/src/samdl/sam_dmac.c index f1afd24ff07..f81d77f75dc 100644 --- a/arch/arm/src/samdl/sam_dmac.c +++ b/arch/arm/src/samdl/sam_dmac.c @@ -1259,7 +1259,7 @@ void sam_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) { struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle; @@ -1291,7 +1291,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) regs->chintflag = getreg8(SAM_DMAC_CHINTFLAG); /* Channel Interrupt Flag Status and Clear Register */ regs->chstatus = getreg8(SAM_DMAC_CHSTATUS); /* Channel Status Register */ } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /**************************************************************************** * Name: sam_dmadump @@ -1304,26 +1304,26 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg) { struct sam_dmach_s *dmach = (struct sam_dmach_s *)handle; - dmaerr("%s\n", msg); - dmaerr(" DMAC Registers:\n"); - dmaerr(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n", - regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum); - dmaerr(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n", - regs->crcstatus, regs->errctrl, regs->qosctrl, regs->swtrigctrl); - dmaerr(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n", - regs->prictrl0, regs->intpend, regs->intstatus, regs->busych); - dmaerr(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n", - regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr); - dmaerr(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n", - regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag, - dmaerr(" CHSTATUS: %02x\n", - regs->chstatus); + dmainfo("%s\n", msg); + dmainfo(" DMAC Registers:\n"); + dmainfo(" CTRL: %04x CRCCTRL: %04x CRCDATAIN: %08x CRCCHKSUM: %08x\n", + regs->ctrl, regs->crcctrl, regs->crcdatain, regs->crcchksum); + dmainfo(" CRCSTATUS: %02x DBGCTRL: %02x QOSCTRL: %02x SWTRIGCTRL: %08x\n", + regs->crcstatus, regs->errctrl, regs->qosctrl, regs->swtrigctrl); + dmainfo(" PRICTRL0: %08x INTPEND: %04x INSTSTATUS: %08x BUSYCH: %08x\n", + regs->prictrl0, regs->intpend, regs->intstatus, regs->busych); + dmainfo(" PENDCH: %08x ACTIVE: %08x BASEADDR: %08x WRBADDR: %08x\n", + regs->pendch, regs->active, regs->baseaddr, regs->wrbaddr); + dmainfo(" CHID: %02x CHCRTRLA: %02x CHCRTRLB: %08x CHINFLAG: %02x\n", + regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag, + dmainfo(" CHSTATUS: %02x\n", + regs->chstatus); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ #endif /* CONFIG_SAMDL_DMAC */ diff --git a/arch/arm/src/samdl/sam_dmac.h b/arch/arm/src/samdl/sam_dmac.h index 86224469ffd..2a6937dd682 100644 --- a/arch/arm/src/samdl/sam_dmac.h +++ b/arch/arm/src/samdl/sam_dmac.h @@ -62,12 +62,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_DMA -#endif - /* DMA ******************************************************************************/ /* Flags used to characterize the desired DMA channel. The naming convention is that @@ -157,7 +151,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s { /* DMAC Registers */ @@ -321,7 +315,7 @@ void sam_dmastop(DMA_HANDLE handle); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); #else # define sam_dmasample(handle,regs) @@ -335,7 +329,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg); #else diff --git a/arch/arm/src/samdl/sam_port.c b/arch/arm/src/samdl/sam_port.c index 1b4cd115fbe..8ba1e1f88cb 100644 --- a/arch/arm/src/samdl/sam_port.c +++ b/arch/arm/src/samdl/sam_port.c @@ -62,7 +62,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_DEBUG_PORT +#ifdef CONFIG_DEBUG_GPIO_INFO static const char g_portchar[2] = { 'A', 'B' }; #endif @@ -521,7 +521,7 @@ bool sam_portread(port_pinset_t pinset) * ************************************************************************************/ -#ifdef CONFIG_DEBUG_PORT +#ifdef CONFIG_DEBUG_GPIO_INFO int sam_dumpport(uint32_t pinset, const char *msg) { irqstate_t flags; @@ -538,20 +538,20 @@ int sam_dumpport(uint32_t pinset, const char *msg) /* The following requires exclusive access to the PORT registers */ flags = enter_critical_section(); - _llerr("PORT%c pin: %d pinset: %08x base: %08x -- %s\n", - g_portchar[port], pin, pinset, base, msg); - _llerr(" DIR: %08x OUT: %08x IN: %08x\n", - getreg32(base + SAM_PORT_DIR_OFFSET), - getreg32(base + SAM_PORT_OUT_OFFSET), - getreg32(base + SAM_PORT_IN_OFFSET)); - _llerr(" CTRL: %08x WRCONFIG: %08x\n", - getreg32(base + SAM_PORT_CTRL_OFFSET), - getreg32(base + SAM_PORT_WRCONFIG_OFFSET)); - _llerr(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n", - base + SAM_PORT_PMUX_OFFSET(pin), - getreg8(base + SAM_PORT_PMUX_OFFSET(pin)), - base + SAM_PORT_PINCFG_OFFSET(pin), - getreg8(base + SAM_PORT_PINCFG_OFFSET(pin))); + gpioinfo("PORT%c pin: %d pinset: %08x base: %08x -- %s\n", + g_portchar[port], pin, pinset, base, msg); + gpioinfo(" DIR: %08x OUT: %08x IN: %08x\n", + getreg32(base + SAM_PORT_DIR_OFFSET), + getreg32(base + SAM_PORT_OUT_OFFSET), + getreg32(base + SAM_PORT_IN_OFFSET)); + gpioinfo(" CTRL: %08x WRCONFIG: %08x\n", + getreg32(base + SAM_PORT_CTRL_OFFSET), + getreg32(base + SAM_PORT_WRCONFIG_OFFSET)); + gpioinfo(" PMUX[%08x]: %02x PINCFG[%08x]: %02x\n", + base + SAM_PORT_PMUX_OFFSET(pin), + getreg8(base + SAM_PORT_PMUX_OFFSET(pin)), + base + SAM_PORT_PINCFG_OFFSET(pin), + getreg8(base + SAM_PORT_PINCFG_OFFSET(pin))); leave_critical_section(flags); return OK; diff --git a/arch/arm/src/samdl/sam_spi.c b/arch/arm/src/samdl/sam_spi.c index 1d8f2c41635..ac7ea3d2cc2 100644 --- a/arch/arm/src/samdl/sam_spi.c +++ b/arch/arm/src/samdl/sam_spi.c @@ -73,6 +73,14 @@ #ifdef SAMDL_HAVE_SPI +/**************************************************************************** + * Pre-process Definitions + ****************************************************************************/ + +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMDL_SPI_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -540,7 +548,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + spiinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -573,7 +581,7 @@ static uint8_t spi_getreg8(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, (uint32_t)regval, regaddr)) { - _llerr("%08x->%02x\n", regaddr, regval); + spiinfo("%08x->%02x\n", regaddr, regval); } #endif @@ -596,7 +604,7 @@ static void spi_putreg8(struct sam_spidev_s *priv, uint8_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, (uint32_t)regval, regaddr)) { - _llerr("%08x<-%02x\n", regaddr, regval); + spiinfo("%08x<-%02x\n", regaddr, regval); } #endif @@ -619,7 +627,7 @@ static uint16_t spi_getreg16(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, (uint32_t)regval, regaddr)) { - _llerr("%08x->%04x\n", regaddr, regval); + spiinfo("%08x->%04x\n", regaddr, regval); } #endif @@ -642,7 +650,7 @@ static void spi_putreg16(struct sam_spidev_s *priv, uint16_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, (uint32_t)regval, regaddr)) { - _llerr("%08x<-%04x\n", regaddr, regval); + spiinfo("%08x<-%04x\n", regaddr, regval); } #endif @@ -665,7 +673,7 @@ static uint32_t spi_getreg32(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + spiinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -688,7 +696,7 @@ static void spi_putreg32(struct sam_spidev_s *priv, uint32_t regval, #ifdef CONFIG_SAMDL_SPI_REGDEBUG if (spi_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + spiinfo("%08x<-%08x\n", regaddr, regval); } #endif diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index bbed32a7b86..1f217e5d4a3 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -701,7 +701,7 @@ config SAMV7_WDT_IDLEHALT config SAMV7_WDT_REGDEBUG bool "Register level debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_WATCHDOG_INFO ---help--- Enable low-level register debug output @@ -735,7 +735,7 @@ config SAMV7_RSWDT_IDLEHALT config SAMV7_RSWDT_REGDEBUG bool "Register level debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_WATCHDOG_INFO ---help--- Enable low-level register debug output @@ -894,11 +894,11 @@ endif # SAMV7_SPI_SLAVE config SAMV7_SPI_REGDEBUG bool "SPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level SPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endmenu # SPI device driver options @@ -941,11 +941,11 @@ config SAMV7_QSPI_DMADEBUG config SAMV7_QSPI_REGDEBUG bool "QSPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_SPI_INFO default n ---help--- Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_FEATURES. + Requires also CONFIG_DEBUG_SPI_INFO. endmenu # QSPI device driver options @@ -969,11 +969,11 @@ config SAMV7_TWIHS2_FREQUENCY config SAMV7_TWIHS_REGDEBUG bool "TWIHS register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2C_INFO default n ---help--- Output detailed register-level TWIHS device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2C_INFO. endmenu # TWIHS device driver options @@ -1345,11 +1345,11 @@ config SAMV7_SSC_DMADEBUG config SAMV7_SSC_REGDEBUG bool "SSC Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_I2S_INFO default n ---help--- Output detailed register-level SSC device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also CONFIG_DEBUG_I2S_INFO. config SAMV7_SSC_QDEBUG bool "SSC Queue debug" @@ -1580,11 +1580,11 @@ config SAMV7_TC_DEBUG config SAMV7_TC_REGDEBUG bool "TC register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_TIMER_INFO default n ---help--- Output detailed register-level Timer/Counter device debug - information. Very invasive! Requires also CONFIG_DEBUG_FEATURES. + information. Very invasive! Requires also CONFIG_DEBUG_TIMER_INFO. endmenu # Timer/counter Configuration endif # SAMV7_HAVE_TC @@ -1658,11 +1658,11 @@ config SAMV7_HSMCI_CMDDEBUG config SAMV7_HSMCI_REGDEBUG bool "HSMCI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_MEMCARD_INFO default n ---help--- Output detailed register-level HSCMI device debug information. - Very invasive! Requires also CONFIG_DEBUG_FEATURES. + Very invasive! Requires also DEBUG_MEMCARD_INFO. endmenu # HSMCI device driver options @@ -1882,9 +1882,9 @@ config SAMV7_EMAC_DEBUG config SAMV7_EMAC_REGDEBUG bool "Register-Level Debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_NET_INFO ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET_INFO. endmenu # EMAC0 device driver options @@ -1940,7 +1940,7 @@ config SAMV7_USBHS_EP7DMA_WAR config SAMV7_USBHS_REGDEBUG bool "Enable low-level USBHS register debug" default n - depends on DEBUG_FEATURES + depends on DEBUG_USB_INFO endmenu # USB High Speed Device Controller driver (DCD) options diff --git a/arch/arm/src/samv7/sam_emac.c b/arch/arm/src/samv7/sam_emac.c index f43d432b681..ae1151a04f6 100644 --- a/arch/arm/src/samv7/sam_emac.c +++ b/arch/arm/src/samv7/sam_emac.c @@ -307,16 +307,16 @@ * enabled. */ -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_SAMV7_EMAC_REGDEBUG -#endif - #ifdef CONFIG_NET_DUMPPACKET # define sam_dumppacket(m,a,n) lib_dumpbuffer(m,a,n) #else # define sam_dumppacket(m,a,n) #endif +#ifndef CONFIG_NET_INFO +# undef CONFIG_SAMV7_EMAC_REGDEBUG +#endif + /* EMAC buffer sizes, number of buffers, and number of descriptors *********** * * REVISIT: The CONFIG_NET_MULTIBUFFER might be useful. It might be possible @@ -560,7 +560,7 @@ struct sam_emac_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMV7_EMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_EMAC_REGDEBUG static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, uintptr_t address); #endif @@ -966,7 +966,7 @@ static bool sam_checkreg(struct sam_emac_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + ninfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -999,7 +999,7 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uint16_t offset) #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + ninfo("%08x->%08x\n", regaddr, regval); } #endif @@ -1023,7 +1023,7 @@ static void sam_putreg(struct sam_emac_s *priv, uint16_t offset, #ifdef CONFIG_SAMV7_EMAC_REGDEBUG if (sam_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + ninfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1896,7 +1896,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid) if (dev->d_len > CONFIG_NET_ETH_MTU) { - nllerr("DROPPED: Too big: %d\n", dev->d_len); + nllwarn("WARNING: Dropped, Too big: %d\n", dev->d_len); NETDEV_RXERRORS(&priv->dev); continue; } @@ -2010,7 +2010,7 @@ static void sam_receive(struct sam_emac_s *priv, int qid) else #endif { - nllerr("DROPPED: Unknown type: %04x\n", BUF->type); + nllwarn("WARNING: Dropped, Unknown type: %04x\n", BUF->type); NETDEV_RXDROPPED(&priv->dev); } } @@ -2418,7 +2418,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid) if ((pending & EMAC_INT_PFNZ) != 0) { - nllerr("Pause frame received\n"); + nllinfo("Pause frame received\n"); } /* Check for Pause Time Zero (PTZ) @@ -2428,7 +2428,7 @@ static inline void sam_interrupt_process(FAR struct sam_emac_s *priv, int qid) if ((pending & EMAC_INT_PTZ) != 0) { - nllerr("Pause TO!\n"); + nllinfo("Pause TO!\n"); } #endif } @@ -2593,7 +2593,7 @@ static int sam_emac1_interrupt(int irq, void *context) static inline void sam_txtimeout_process(FAR struct sam_emac_s *priv) { - nllerr("Timeout!\n"); + nllerr("ERROR: Timeout!\n"); NETDEV_TXTIMEOUTS(&priv->dev); /* Reset the hardware. Just take the interface down, then back up again. */ @@ -2824,15 +2824,15 @@ static int sam_ifup(struct net_driver_s *dev) int ret; #ifdef CONFIG_NET_IPv4 - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); #endif #ifdef CONFIG_NET_IPv6 - nerr("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", - dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], - dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], - dev->d_ipv6addr[6], dev->d_ipv6addr[7]); + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); #endif /* Configure the EMAC interface for normal operation. */ @@ -2910,7 +2910,7 @@ static int sam_ifdown(struct net_driver_s *dev) struct sam_emac_s *priv = (struct sam_emac_s *)dev->d_private; irqstate_t flags; - nllerr("Taking the network down\n"); + nllinfo("Taking the network down\n"); /* Disable the EMAC interrupt */ diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index ec664e0e931..bddf8e7f9ae 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -81,6 +81,10 @@ # error "HSMCI support requires CONFIG_SAMV7_XDMAC" #endif +#ifndef CONFIG_DEBUG_MEMCARD_INFO +# undef CONFIG_SAMV7_HSMCI_REGDEBUG +#endif + /* System Bus Interfaces */ #if defined(CONFIG_ARCH_CHIP_SAMV71) || defined(CONFIG_ARCH_CHIP_SAME70) @@ -653,7 +657,7 @@ static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + mcinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -686,7 +690,7 @@ static inline uint32_t sam_getreg(struct sam_dev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + mcinfo("%08x->%08x\n", address, value); } #endif @@ -709,7 +713,7 @@ static inline void sam_putreg(struct sam_dev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_HSMCI_REGDEBUG if (sam_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + mcinfo("%08x<-%08x\n", address, value); } #endif @@ -933,25 +937,25 @@ static void sam_hsmcisample(struct sam_dev_s *priv, static void sam_hsmcidump(struct sam_dev_s *priv, struct sam_hsmciregs_s *regs, const char *msg) { - ferr("HSMCI Registers: %s\n", msg); - ferr(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); - ferr(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); - ferr(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); - ferr(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); - ferr(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); - ferr(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); + mcinfo("HSMCI Registers: %s\n", msg); + mcinfo(" MR[%08x]: %08x\n", priv->base + SAM_HSMCI_MR_OFFSET, regs->mr); + mcinfo(" DTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_DTOR_OFFSET, regs->dtor); + mcinfo(" SDCR[%08x]: %08x\n", priv->base + SAM_HSMCI_SDCR_OFFSET, regs->sdcr); + mcinfo(" ARGR[%08x]: %08x\n", priv->base + SAM_HSMCI_ARGR_OFFSET, regs->argr); + mcinfo(" BLKR[%08x]: %08x\n", priv->base + SAM_HSMCI_BLKR_OFFSET, regs->blkr); + mcinfo(" CSTOR[%08x]: %08x\n", priv->base + SAM_HSMCI_CSTOR_OFFSET, regs->cstor); #if 0 /* Reading these can cause loss of response data */ - ferr(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); - ferr(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); - ferr(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); - ferr(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); + mcinfo(" RSPR0[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR0_OFFSET, regs->rsp0); + mcinfo(" RSPR1[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR1_OFFSET, regs->rsp1); + mcinfo(" RSPR2[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR2_OFFSET, regs->rsp2); + mcinfo(" RSPR3[%08x]: %08x\n", priv->base + SAM_HSMCI_RSPR3_OFFSET, regs->rsp3); #endif - ferr(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); - ferr(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); - ferr(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); - ferr(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); - ferr(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); - ferr(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); + mcinfo(" SR[%08x]: %08x\n", priv->base + SAM_HSMCI_SR_OFFSET, regs->sr); + mcinfo(" IMR[%08x]: %08x\n", priv->base + SAM_HSMCI_IMR_OFFSET, regs->imr); + mcinfo(" DMA[%08x]: %08x\n", priv->base + SAM_HSMCI_DMA_OFFSET, regs->dma); + mcinfo(" CFG[%08x]: %08x\n", priv->base + SAM_HSMCI_CFG_OFFSET, regs->cfg); + mcinfo(" WPMR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPMR_OFFSET, regs->wpmr); + mcinfo(" WPSR[%08x]: %08x\n", priv->base + SAM_HSMCI_WPSR_OFFSET, regs->wpsr); } #endif @@ -1025,7 +1029,7 @@ static void sam_xfrdumpone(struct sam_dev_s *priv, int index, } else { - ferr("%s: Not collected\n", msg); + mcerr("ERROR: %s: Not collected\n", msg); } } #endif @@ -1169,7 +1173,7 @@ static void sam_dmacallback(DMA_HANDLE handle, void *arg, int result) if (result < 0) { wkupevent = (result == -ETIMEDOUT ? SDIOWAIT_TIMEOUT : SDIOWAIT_ERROR); - fllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent); + mcllerr("ERROR: DMA failed: result=%d wkupevent=%04x\n", result, wkupevent); /* sam_endtransfer will terminate the transfer and wait up the waiting * client in this case. @@ -1269,7 +1273,7 @@ static void sam_eventtimeout(int argc, uint32_t arg) /* Yes.. wake up any waiting threads */ sam_endwait(priv, SDIOWAIT_TIMEOUT); - fllerr("ERROR: Timeout\n"); + mcllerr("ERROR: Timeout\n"); } } @@ -1469,7 +1473,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. Was it some kind of timeout error? */ - fllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending); + mcllerr("ERROR: enabled: %08x pending: %08x\n", enabled, pending); if ((pending & HSMCI_DATA_TIMEOUT_ERRORS) != 0) { /* Yes.. Terminate with a timeout. */ @@ -1590,7 +1594,7 @@ static int sam_hsmci_interrupt(struct sam_dev_s *priv) { /* Yes.. Was the error some kind of timeout? */ - fllinfo("ERROR: events: %08x SR: %08x\n", + mcllinfo("ERROR: events: %08x SR: %08x\n", priv->cmdrmask, enabled); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -2056,7 +2060,7 @@ static int sam_sendcmd(FAR struct sdio_dev_s *dev, /* Write the fully decorated command to CMDR */ - finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); sam_putreg(priv, regval, SAM_HSMCI_CMDR_OFFSET); sam_cmdsample1(priv, SAMPLENDX_AFTER_CMDR); return OK; @@ -2239,7 +2243,7 @@ static int sam_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, { /* Some fatal error has occurred */ - ferr("ERROR: sr %08x\n", sr); + mcerr("ERROR: sr %08x\n", sr); return -EIO; } else if ((sr & HSMCI_INT_TXRDY) != 0) @@ -2419,7 +2423,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { /* Yes.. Was the error some kind of timeout? */ - ferr("ERROR: cmd: %08x events: %08x SR: %08x\n", + mcerr("ERROR: cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); if ((pending & HSMCI_RESPONSE_TIMEOUT_ERRORS) != 0) @@ -2449,7 +2453,7 @@ static int sam_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) } else if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", + mcerr("ERROR: Timeout cmd: %08x events: %08x SR: %08x\n", cmd, priv->cmdrmask, sr); priv->wkupevent = SDIOWAIT_TIMEOUT; @@ -2524,7 +2528,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + mcerr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2536,7 +2540,7 @@ static int sam_recvshort(FAR struct sdio_dev_s *dev, (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2587,7 +2591,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2597,7 +2601,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, if ((priv->wkupevent & SDIOWAIT_TIMEOUT) != 0) { - ferr("ERROR: timeout\n"); + mcerr("ERROR: timeout\n"); ret = -EINVAL; } @@ -2605,7 +2609,7 @@ static int sam_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, else if ((priv->wkupevent & SDIOWAIT_ERROR) != 0) { - ferr("ERROR: Other error\n"); + mcerr("ERROR: Other error\n"); ret = -EIO; } @@ -2781,7 +2785,7 @@ static sdio_eventset_t sam_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + mcerr("ERROR: wd_start failed: %d\n", ret); } } @@ -2847,7 +2851,7 @@ static void sam_callbackenable(FAR struct sdio_dev_s *dev, { struct sam_dev_s *priv = (struct sam_dev_s *)dev; - finfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -2883,7 +2887,7 @@ static int sam_registercallback(FAR struct sdio_dev_s *dev, /* Disable callbacks and register this callback and is argument */ - finfo("Register %p(%p)\n", callback, arg); + mcinfo("Register %p(%p)\n", callback, arg); DEBUGASSERT(priv != NULL); priv->cbevents = 0; @@ -3158,7 +3162,7 @@ static void sam_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); flags = enter_critical_section(); @@ -3213,17 +3217,17 @@ static void sam_callback(void *arg) { /* NOTE: Currently, work_cancel only returns success */ - ferr("ERROR: Failed to cancel work: %d\n", ret); + mcerr("ERROR: Failed to cancel work: %d\n", ret); } - fllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + mcllinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); ret = work_queue(LPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); if (ret < 0) { /* NOTE: Currently, work_queue only returns success */ - ferr("ERROR: Failed to schedule work: %d\n", ret); + mcerr("ERROR: Failed to schedule work: %d\n", ret); } } @@ -3261,7 +3265,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) * for now, an* HSMCI peripheral does correspond to a slot. */ - finfo("slotno: %d\n", slotno); + mcinfo("slotno: %d\n", slotno); #ifdef CONFIG_SAMV7_HSMCI0 if (slotno == 0) @@ -3344,7 +3348,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } - finfo("priv: %p base: %08x hsmci: %d pid: %d\n", + mcinfo("priv: %p base: %08x hsmci: %d pid: %d\n", priv, priv->base, priv->hsmci, pid); /* Initialize the HSMCI slot structure */ @@ -3414,7 +3418,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) priv->cdstatus &= ~SDIO_STATUS_PRESENT; } - fllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcllinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -3459,7 +3463,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - finfo("cdstatus: %02x\n", priv->cdstatus); + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 1cf299e0552..adade973637 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -1195,7 +1195,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { if (priv->count == 4) { - _llerr("...\n"); + caninfo("...\n"); } return regval; @@ -1212,7 +1212,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", priv->count - 3); + caninfo("[repeats %d more times]\n", priv->count - 3); } /* Save the new address, value, and count */ @@ -1224,7 +1224,7 @@ static uint32_t mcan_getreg(FAR struct sam_mcan_s *priv, int offset) /* Show the register value read */ - _llerr("%08x->%08x\n", regaddr, regval); + caninfo("%08x->%08x\n", regaddr, regval); return regval; } @@ -1261,7 +1261,7 @@ static void mcan_putreg(FAR struct sam_mcan_s *priv, int offset, uint32_t regval /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + caninfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -1296,74 +1296,74 @@ static void mcan_dumpregs(FAR struct sam_mcan_s *priv, FAR const char *msg) { FAR const struct sam_config_s *config = priv->config; - _llerr("MCAN%d Registers: %s\n", config->port, msg); - _llerr(" Base: %08x\n", config->base); + caninfo("MCAN%d Registers: %s\n", config->port, msg); + caninfo(" Base: %08x\n", config->base); - _llerr(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n", - getreg32(config->base + SAM_MCAN_CUST_OFFSET), - getreg32(config->base + SAM_MCAN_FBTP_OFFSET), - getreg32(config->base + SAM_MCAN_TEST_OFFSET), - getreg32(config->base + SAM_MCAN_RWD_OFFSET)); + caninfo(" CUST: %08x FBTP: %08x TEST: %08x RWD: %08x\n", + getreg32(config->base + SAM_MCAN_CUST_OFFSET), + getreg32(config->base + SAM_MCAN_FBTP_OFFSET), + getreg32(config->base + SAM_MCAN_TEST_OFFSET), + getreg32(config->base + SAM_MCAN_RWD_OFFSET)); - _llerr(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n", - getreg32(config->base + SAM_MCAN_CCCR_OFFSET), - getreg32(config->base + SAM_MCAN_BTP_OFFSET), - getreg32(config->base + SAM_MCAN_TSCC_OFFSET), - getreg32(config->base + SAM_MCAN_TSCV_OFFSET)); + caninfo(" CCCR: %08x BTP: %08x TSCC: %08x TSCV: %08x\n", + getreg32(config->base + SAM_MCAN_CCCR_OFFSET), + getreg32(config->base + SAM_MCAN_BTP_OFFSET), + getreg32(config->base + SAM_MCAN_TSCC_OFFSET), + getreg32(config->base + SAM_MCAN_TSCV_OFFSET)); - _llerr(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n", - getreg32(config->base + SAM_MCAN_TOCC_OFFSET), - getreg32(config->base + SAM_MCAN_TOCV_OFFSET), - getreg32(config->base + SAM_MCAN_ECR_OFFSET), - getreg32(config->base + SAM_MCAN_PSR_OFFSET)); + caninfo(" TOCC: %08x TOCV: %08x ECR: %08x PSR: %08x\n", + getreg32(config->base + SAM_MCAN_TOCC_OFFSET), + getreg32(config->base + SAM_MCAN_TOCV_OFFSET), + getreg32(config->base + SAM_MCAN_ECR_OFFSET), + getreg32(config->base + SAM_MCAN_PSR_OFFSET)); - _llerr(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n", - getreg32(config->base + SAM_MCAN_IR_OFFSET), - getreg32(config->base + SAM_MCAN_IE_OFFSET), - getreg32(config->base + SAM_MCAN_ILS_OFFSET), - getreg32(config->base + SAM_MCAN_ILE_OFFSET)); + caninfo(" IR: %08x IE: %08x ILS: %08x ILE: %08x\n", + getreg32(config->base + SAM_MCAN_IR_OFFSET), + getreg32(config->base + SAM_MCAN_IE_OFFSET), + getreg32(config->base + SAM_MCAN_ILS_OFFSET), + getreg32(config->base + SAM_MCAN_ILE_OFFSET)); - _llerr(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n", - getreg32(config->base + SAM_MCAN_GFC_OFFSET), - getreg32(config->base + SAM_MCAN_SIDFC_OFFSET), - getreg32(config->base + SAM_MCAN_XIDFC_OFFSET), - getreg32(config->base + SAM_MCAN_XIDAM_OFFSET)); + caninfo(" GFC: %08x SIDFC: %08x XIDFC: %08x XIDAM: %08x\n", + getreg32(config->base + SAM_MCAN_GFC_OFFSET), + getreg32(config->base + SAM_MCAN_SIDFC_OFFSET), + getreg32(config->base + SAM_MCAN_XIDFC_OFFSET), + getreg32(config->base + SAM_MCAN_XIDAM_OFFSET)); - _llerr(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n", - getreg32(config->base + SAM_MCAN_HPMS_OFFSET), - getreg32(config->base + SAM_MCAN_NDAT1_OFFSET), - getreg32(config->base + SAM_MCAN_NDAT2_OFFSET), - getreg32(config->base + SAM_MCAN_RXF0C_OFFSET)); + caninfo(" HPMS: %08x NDAT1: %08x NDAT2: %08x RXF0C: %08x\n", + getreg32(config->base + SAM_MCAN_HPMS_OFFSET), + getreg32(config->base + SAM_MCAN_NDAT1_OFFSET), + getreg32(config->base + SAM_MCAN_NDAT2_OFFSET), + getreg32(config->base + SAM_MCAN_RXF0C_OFFSET)); - _llerr(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n", - getreg32(config->base + SAM_MCAN_RXF0S_OFFSET), - getreg32(config->base + SAM_MCAN_RXF0A_OFFSET), - getreg32(config->base + SAM_MCAN_RXBC_OFFSET), - getreg32(config->base + SAM_MCAN_RXF1C_OFFSET)); + caninfo(" RXF0S: %08x FXF0A: %08x RXBC: %08x RXF1C: %08x\n", + getreg32(config->base + SAM_MCAN_RXF0S_OFFSET), + getreg32(config->base + SAM_MCAN_RXF0A_OFFSET), + getreg32(config->base + SAM_MCAN_RXBC_OFFSET), + getreg32(config->base + SAM_MCAN_RXF1C_OFFSET)); - _llerr(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n", - getreg32(config->base + SAM_MCAN_RXF1S_OFFSET), - getreg32(config->base + SAM_MCAN_RXF1A_OFFSET), - getreg32(config->base + SAM_MCAN_RXESC_OFFSET), - getreg32(config->base + SAM_MCAN_TXBC_OFFSET)); + caninfo(" RXF1S: %08x FXF1A: %08x RXESC: %08x TXBC: %08x\n", + getreg32(config->base + SAM_MCAN_RXF1S_OFFSET), + getreg32(config->base + SAM_MCAN_RXF1A_OFFSET), + getreg32(config->base + SAM_MCAN_RXESC_OFFSET), + getreg32(config->base + SAM_MCAN_TXBC_OFFSET)); - _llerr(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n", - getreg32(config->base + SAM_MCAN_TXFQS_OFFSET), - getreg32(config->base + SAM_MCAN_TXESC_OFFSET), - getreg32(config->base + SAM_MCAN_TXBRP_OFFSET), - getreg32(config->base + SAM_MCAN_TXBAR_OFFSET)); + caninfo(" TXFQS: %08x TXESC: %08x TXBRP: %08x TXBAR: %08x\n", + getreg32(config->base + SAM_MCAN_TXFQS_OFFSET), + getreg32(config->base + SAM_MCAN_TXESC_OFFSET), + getreg32(config->base + SAM_MCAN_TXBRP_OFFSET), + getreg32(config->base + SAM_MCAN_TXBAR_OFFSET)); - _llerr(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n", - getreg32(config->base + SAM_MCAN_TXBCR_OFFSET), - getreg32(config->base + SAM_MCAN_TXBTO_OFFSET), - getreg32(config->base + SAM_MCAN_TXBCF_OFFSET), - getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET)); + caninfo(" TXBCR: %08x TXBTO: %08x TXBCF: %08x TXBTIE: %08x\n", + getreg32(config->base + SAM_MCAN_TXBCR_OFFSET), + getreg32(config->base + SAM_MCAN_TXBTO_OFFSET), + getreg32(config->base + SAM_MCAN_TXBCF_OFFSET), + getreg32(config->base + SAM_MCAN_TXBTIE_OFFSET)); - _llerr("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n", - getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET), - getreg32(config->base + SAM_MCAN_TXEFC_OFFSET), - getreg32(config->base + SAM_MCAN_TXEFS_OFFSET), - getreg32(config->base + SAM_MCAN_TXEFA_OFFSET)); + caninfo("TXBCIE: %08x TXEFC: %08x TXEFS: %08x TXEFA: %08x\n", + getreg32(config->base + SAM_MCAN_TXBCIE_OFFSET), + getreg32(config->base + SAM_MCAN_TXEFC_OFFSET), + getreg32(config->base + SAM_MCAN_TXEFS_OFFSET), + getreg32(config->base + SAM_MCAN_TXEFA_OFFSET)); } #endif @@ -2205,7 +2205,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) ret = mcan_hw_initialize(priv); if (ret < 0) { - canllerr("MCAN%d H/W initialization failed: %d\n", config->port, ret); + canllerr("ERROR: MCAN%d H/W initialization failed: %d\n", config->port, ret); return ret; } @@ -2216,7 +2216,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) ret = irq_attach(config->irq0, config->handler); if (ret < 0) { - canllerr("Failed to attach MCAN%d line 0 IRQ (%d)", + canllerr("ERROR: Failed to attach MCAN%d line 0 IRQ (%d)", config->port, config->irq0); return ret; } @@ -2224,7 +2224,7 @@ static int mcan_setup(FAR struct can_dev_s *dev) ret = irq_attach(config->irq1, config->handler); if (ret < 0) { - canllerr("Failed to attach MCAN%d line 1 IRQ (%d)", + canllerr("ERROR: Failed to attach MCAN%d line 1 IRQ (%d)", config->port, config->irq1); return ret; } diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index 569f3747024..b90a515d8b0 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -85,6 +85,10 @@ # define CONFIG_SAMV7_QSPI_DLYBCT 0 #endif +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMV7_QSPI_REGDEBUG +#endif + /* When QSPI DMA is enabled, small DMA transfers will still be performed by * polling logic. But we need a threshold value to determine what is small. * That value is provided by CONFIG_SAMV7_QSPI_DMATHRESHOLD. @@ -374,7 +378,7 @@ static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + spiinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -408,7 +412,7 @@ static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -431,7 +435,7 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index 3723a0bc837..980ecd5b037 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -57,6 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_SAMV7_RSWDT_REGDEBUG +#endif + /* The Watchdog Timer uses the Slow Clock divided by 128 to establish the * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of * 32768 kHz). @@ -104,7 +109,7 @@ struct sam_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else @@ -164,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev; * ****************************************************************************/ -#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr) { static uint32_t prevaddr = 0; @@ -185,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - _llerr("...\n"); + wdinfo("...\n"); } return regval; @@ -202,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - _llerr("%08x->%048\n", regaddr, regval); + wdinfo("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -227,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr) * ****************************************************************************/ -#if defined(CONFIG_SAMV7_RSWDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_RSWDT_REGDEBUG static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + wdinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -449,7 +454,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < RSWDT_MINTIMEOUT || timeout >= RSWDT_MAXTIMEOUT) { - wderr("Cannot represent timeout: %d < %d > %d\n", + wderr("ERROR: Cannot represent timeout: %d < %d > %d\n", RSWDT_MINTIMEOUT, timeout, RSWDT_MAXTIMEOUT); return -ERANGE; } diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index 7af29d3a70e..34caed374cd 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -105,6 +105,14 @@ # undef CONFIG_SAMV7_SPI_DMADEBUG #endif +#ifndef CONFIG_DEBUG_DMA_INFO +# undef CONFIG_SAMV7_SPI_DMADEBUG +#endif + +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMV7_SPI_REGDEBUG +#endif + /* Clocking *****************************************************************/ /* The SPI Baud rate clock is generated by dividing the peripheral clock by * a value between 1 and 255 @@ -428,7 +436,7 @@ static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", spi->ntimes); + spiinfo("...[Repeats %d times]...\n", spi->ntimes); } /* Save information about the new access */ @@ -462,7 +470,7 @@ static inline uint32_t spi_getreg(struct sam_spidev_s *spi, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -485,7 +493,7 @@ static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(spi, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif @@ -1089,7 +1097,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) spics->frequency = frequency; spics->actual = actual; - spierr("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %d->%d\n", frequency, actual); return actual; } diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index 574b5ab0bf0..d2856cd2e99 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -74,6 +74,10 @@ # define CONFIG_SAMV7_SPI_SLAVE_QSIZE 8 #endif +#ifndef CONFIG_DEBUG_SPI_INFO +# undef CONFIG_SAMV7_SPI_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -248,7 +252,7 @@ static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + spiinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -281,7 +285,7 @@ static uint32_t spi_getreg(struct sam_spidev_s *priv, unsigned int offset) #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + spiinfo("%08x->%08x\n", address, value); } #endif @@ -304,7 +308,7 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value, #ifdef CONFIG_SAMV7_SPI_REGDEBUG if (spi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + spiinfo("%08x<-%08x\n", address, value); } #endif @@ -442,7 +446,7 @@ static int spi_interrupt(struct sam_spidev_s *priv) { /* If debug is enabled, report any overrun errors */ - spierr("Error: Overrun (OVRES): %08x\n", pending); + spierr("ERROR: Overrun (OVRES): %08x\n", pending); /* OVRES was cleared by the status read. */ } @@ -509,7 +513,7 @@ static int spi_interrupt(struct sam_spidev_s *priv) { /* If debug is enabled, report any overrun errors */ - spierr("Error: Underrun (UNDEX): %08x\n", pending); + spierr("ERROR: Underrun (UNDEX): %08x\n", pending); /* UNDES was cleared by the status read. */ } diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index eb21113bd3d..c07d5542587 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -91,6 +91,10 @@ # define CONFIG_SAMV7_SSC_MAXINFLIGHT 16 #endif +#ifndef CONFIG_DEBUG_I2S_INFO +# undef CONFIG_SAMV7_SSC_REGDEBUG +#endif + /* Assume no RX/TX support until we learn better */ #undef SSC_HAVE_RX @@ -674,7 +678,7 @@ static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->count); + i2sinfo("...[Repeats %d times]...\n", priv->count); } /* Save information about the new access */ @@ -708,7 +712,7 @@ static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, false, regval, regaddr)) { - _llerr("%08x->%08x\n", regaddr, regval); + i2sinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -731,7 +735,7 @@ static inline void ssc_putreg(struct sam_ssc_s *priv, unsigned int offset, #ifdef CONFIG_SAMV7_SSC_REGDEBUG if (ssc_checkreg(priv, true, regval, regaddr)) { - _llerr("%08x<-%08x\n", regaddr, regval); + i2sinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1060,7 +1064,7 @@ static void ssc_dma_sampleinit(struct sam_ssc_s *priv, #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_RX) static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ @@ -1125,7 +1129,7 @@ static void ssc_rxdma_sampledone(struct sam_ssc_s *priv, int result) #if defined(CONFIG_SAMV7_SSC_DMADEBUG) && defined(SSC_HAVE_TX) static void ssc_txdma_sampledone(struct sam_ssc_s *priv, int result) { - _llerr("result: %d\n", result); + i2sinfo("result: %d\n", result); /* Sample the final registers */ diff --git a/arch/arm/src/samv7/sam_tc.c b/arch/arm/src/samv7/sam_tc.c index 4eba2f077b0..98c5347a8c6 100644 --- a/arch/arm/src/samv7/sam_tc.c +++ b/arch/arm/src/samv7/sam_tc.c @@ -77,6 +77,10 @@ * Pre-processor Definitions ****************************************************************************/ +#ifndef CONFIG_DEBUG_TIMER_INFO +# undef CONFIG_SAMV7_TC_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -643,19 +647,19 @@ static void sam_regdump(struct sam_chan_s *chan, const char *msg) uintptr_t base; base = tc->base; - _llerr("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); - _llerr(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", - getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), - getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); + tmrinfo("TC%d [%08x]: %s\n", tc->tc, (int)base, msg); + tmrinfo(" BMR: %08x QIMR: %08x QISR: %08x WPMR: %08x\n", + getreg32(base+SAM_TC_BMR_OFFSET), getreg32(base+SAM_TC_QIMR_OFFSET), + getreg32(base+SAM_TC_QISR_OFFSET), getreg32(base+SAM_TC_WPMR_OFFSET)); base = chan->base; - _llerr("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); - _llerr(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", - getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), - getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); - _llerr(" RA: %08x RB: %08x RC: %08x IMR: %08x\n", - getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), - getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_IMR_OFFSET)); + tmrinfo("TC%d Channel %d [%08x]: %s\n", tc->tc, chan->chan, (int)base, msg); + tmrinfo(" CMR: %08x SSMR: %08x RAB: %08x CV: %08x\n", + getreg32(base+SAM_TC_CMR_OFFSET), getreg32(base+SAM_TC_SMMR_OFFSET), + getreg32(base+SAM_TC_RAB_OFFSET), getreg32(base+SAM_TC_CV_OFFSET)); + tmrinfo(" RA: %08x RB: %08x RC: %08x IMR: %08x\n", + getreg32(base+SAM_TC_RA_OFFSET), getreg32(base+SAM_TC_RB_OFFSET), + getreg32(base+SAM_TC_RC_OFFSET), getreg32(base+SAM_TC_IMR_OFFSET)); } #endif @@ -698,7 +702,7 @@ static bool sam_checkreg(struct sam_tc_s *tc, bool wr, uint32_t regaddr, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", tc->ntimes); + tmrinfo("...[Repeats %d times]...\n", tc->ntimes); } /* Save information about the new access */ @@ -733,7 +737,7 @@ static inline uint32_t sam_tc_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tmrinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -757,7 +761,7 @@ static inline void sam_tc_putreg(struct sam_chan_s *chan, uint32_t regval, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tmrinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -781,7 +785,7 @@ static inline uint32_t sam_chan_getreg(struct sam_chan_s *chan, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, false, regaddr, regval)) { - _llerr("%08x->%08x\n", regaddr, regval); + tmrinfo("%08x->%08x\n", regaddr, regval); } #endif @@ -804,7 +808,7 @@ static inline void sam_chan_putreg(struct sam_chan_s *chan, unsigned int offset, #ifdef CONFIG_SAMV7_TC_REGDEBUG if (sam_checkreg(chan->tc, true, regaddr, regval)) { - _llerr("%08x<-%08x\n", regaddr, regval); + tmrinfo("%08x<-%08x\n", regaddr, regval); } #endif @@ -1066,7 +1070,7 @@ static int sam_tc_mcksrc(uint32_t frequency, uint32_t *tcclks, { /* If no divisor can be found, return -ERANGE */ - tmrerr("Lower bound search failed\n"); + tmrerr("ERROR: Lower bound search failed\n"); return -ERANGE; } @@ -1225,7 +1229,7 @@ static inline struct sam_chan_s *sam_tc_initialize(int channel) { /* Yes.. return a failure */ - tmrerr("Channel %d is in-use\n", channel); + tmrerr("ERROR: Channel %d is in-use\n", channel); sam_givesem(tc); return NULL; } diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 4dc6fcae9b4..93d59f2a87f 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -91,6 +91,10 @@ # define CONFIG_SAMV7_TWIHS2_FREQUENCY 100000 #endif +#ifndef CONFIG_DEBUG_I2C_INFO +# undef CONFIG_SAMV7_TWIHSHS_REGDEBUG +#endif + /* Driver internal definitions *************************************************/ /* If verbose I2C debug output is enable, then allow more time before we declare * a timeout. The debug output from twi_interrupt will really slow things down! @@ -349,7 +353,7 @@ static bool twi_checkreg(struct twi_dev_s *priv, bool wr, uint32_t value, { /* Yes... show how many times we did it */ - _llerr("...[Repeats %d times]...\n", priv->ntimes); + i2cinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -381,7 +385,7 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address) if (twi_checkreg(priv, false, value, address)) { - _llerr("%08x->%08x\n", address, value); + i2cinfo("%08x->%08x\n", address, value); } return value; @@ -402,7 +406,7 @@ static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, { if (twi_checkreg(priv, true, value, address)) { - _llerr("%08x<-%08x\n", address, value); + i2cinfo("%08x<-%08x\n", address, value); } putreg32(value, address); diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index 43a86c0e79a..e7660280b6e 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -90,6 +90,10 @@ # define CONFIG_USBDEV_EP0_MAXSIZE 64 #endif +#ifndef CONFIG_DEBUG_USB_INFO +# undef CONFIG_SAMV7_USBHS_REGDEBUG +#endif + /* Number of DMA transfer descriptors. Default: 8 */ #ifndef CONFIG_SAMV7_USBDEVHS_NDTDS @@ -108,14 +112,6 @@ # warning CONFIG_USBDEV_DUALSPEED should be defined for high speed support #endif -/* Extremely detailed register debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_SAMV7_USBHS_REGDEBUG -#endif - /* Not yet supported */ #undef CONFIG_SAMV7_USBDEVHS_SCATTERGATHER @@ -721,10 +717,6 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = }; #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Private Functions ****************************************************************************/ @@ -732,6 +724,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = /**************************************************************************** * Register Operations ****************************************************************************/ + /**************************************************************************** * Name: sam_printreg * @@ -743,7 +736,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = #ifdef CONFIG_SAMV7_USBHS_REGDEBUG static void sam_printreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { - _llerr("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); + uinfo("%p%s%08x\n", regaddr, iswrite ? "<-" : "->", regval); } #endif @@ -794,7 +787,7 @@ static void sam_checkreg(uintptr_t regaddr, uint32_t regval, bool iswrite) { /* No.. More than one. */ - _llerr("[repeats %d more times]\n", count); + uinfo("[repeats %d more times]\n", count); } } @@ -869,36 +862,36 @@ static inline void sam_putreg(uint32_t regval, uint32_t regaddr) * Name: sam_dumpep ****************************************************************************/ -#if defined(CONFIG_SAMV7_USBHS_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_USBHS_REGDEBUG static void sam_dumpep(struct sam_usbdev_s *priv, int epno) { /* Global Registers */ - _llerr("Global Register:\n"); - _llerr(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL)); - _llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR)); - _llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR)); - _llerr(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT)); - _llerr(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM)); + uinfo("Global Register:\n"); + uinfo(" CTRL: %08x\n", sam_getreg(SAM_USBHS_DEVCTRL)); + uinfo(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVISR)); + uinfo(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVIMR)); + uinfo(" EPT: %08x\n", sam_getreg(SAM_USBHS_DEVEPT)); + uinfo(" FNUM: %08x\n", sam_getreg(SAM_USBHS_DEVFNUM)); /* Endpoint registers */ - _llerr("Endpoint %d Register:\n", epno); - _llerr(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno))); - _llerr(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno))); - _llerr(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno))); + uinfo("Endpoint %d Register:\n", epno); + uinfo(" CFG: %08x\n", sam_getreg(SAM_USBHS_DEVEPTCFG(epno))); + uinfo(" ISR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTISR(epno))); + uinfo(" IMR: %08x\n", sam_getreg(SAM_USBHS_DEVEPTIMR(epno))); - _llerr("DMA %d Register:\n", epno); + uinfo("DMA %d Register:\n", epno); if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) { - _llerr(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno))); - _llerr(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno))); - _llerr(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno))); - _llerr(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno))); + uinfo(" NXTDSC: %08x\n", sam_getreg(SAM_USBHS_DEVDMANXTDSC(epno))); + uinfo(" ADDRESS: %08x\n", sam_getreg(SAM_USBHS_DEVDMAADDR(epno))); + uinfo(" CONTROL: %08x\n", sam_getreg(SAM_USBHS_DEVDMACTRL(epno))); + uinfo(" STATUS: %08x\n", sam_getreg(SAM_USBHS_DEVDMASTA(epno))); } else { - _llerr(" None\n"); + uinfo(" None\n"); } } #endif diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index d8c870b1f6d..d317bbd74d3 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -57,6 +57,11 @@ * Pre-processor Definitions ****************************************************************************/ /* Configuration ************************************************************/ + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_SAMV7_WDT_REGDEBUG +#endif + /* The Watchdog Timer uses the Slow Clock divided by 128 to establish the * maximum Watchdog period to be 16 seconds (with a typical Slow Clock of * 32768 kHz). @@ -104,7 +109,7 @@ struct sam_lowerhalf_s ****************************************************************************/ /* Register operations ******************************************************/ -#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else @@ -164,7 +169,7 @@ static struct sam_lowerhalf_s g_wdtdev; * ****************************************************************************/ -#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_WDT_REGDEBUG static uint32_t sam_getreg(uintptr_t regaddr) { static uint32_t prevaddr = 0; @@ -185,7 +190,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { if (count == 4) { - _llerr("...\n"); + wdinfo("...\n"); } return regval; @@ -202,7 +207,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) { /* Yes.. then show how many times the value repeated */ - _llerr("[repeats %d more times]\n", count-3); + wdinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -214,7 +219,7 @@ static uint32_t sam_getreg(uintptr_t regaddr) /* Show the register value read */ - _llerr("%08x->%048\n", regaddr, regval); + wdinfo("%08x->%048\n", regaddr, regval); return regval; } #endif @@ -227,12 +232,12 @@ static uint32_t sam_getreg(uintptr_t regaddr) * ****************************************************************************/ -#if defined(CONFIG_SAMV7_WDT_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#ifdef CONFIG_SAMV7_WDT_REGDEBUG static void sam_putreg(uint32_t regval, uintptr_t regaddr) { /* Show the register value being written */ - _llerr("%08x<-%08x\n", regaddr, regval); + wdinfo("%08x<-%08x\n", regaddr, regval); /* Write the value */ @@ -449,7 +454,7 @@ static int sam_settimeout(FAR struct watchdog_lowerhalf_s *lower, if (timeout < WDT_MINTIMEOUT || timeout >= WDT_MAXTIMEOUT) { - wderr("Cannot represent timeout: %d < %d > %d\n", + wderr("ERROR: Cannot represent timeout: %d < %d > %d\n", WDT_MINTIMEOUT, timeout, WDT_MAXTIMEOUT); return -ERANGE; } diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index 2666457a40a..8835b0386dd 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -551,7 +551,7 @@ static uint8_t sam_channel(uint8_t pid, const struct sam_pidmap_s *table, } } - dmaerr("No channel found for pid %d\n", pid); + dmaerr("ERROR: No channel found for pid %d\n", pid); DEBUGPANIC(); return 0x3f; } @@ -2017,7 +2017,7 @@ void sam_dmastop(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; @@ -2057,7 +2057,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) leave_critical_section(flags); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /**************************************************************************** * Name: sam_dmadump @@ -2070,34 +2070,34 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg) { struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; - dmaerr("%s\n", msg); - dmaerr(" DMA Global Registers:\n"); - dmaerr(" GTYPE[%08x]: %08x\n", SAM_XDMAC_GTYPE, regs->gtype); - dmaerr(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg); - dmaerr(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac); - dmaerr(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim); - dmaerr(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs); - dmaerr(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs); - dmaerr(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws); - dmaerr(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws); - dmaerr(" DMA Channel Registers:\n"); - dmaerr(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); - dmaerr(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); - dmaerr(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); - dmaerr(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); - dmaerr(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); - dmaerr(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); - dmaerr(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); - dmaerr(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); - dmaerr(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); - dmaerr(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); - dmaerr(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); + dmainfo("%s\n", msg); + dmainfo(" DMA Global Registers:\n"); + dmainfo(" GTYPE[%08x]: %08x\n", SAM_XDMAC_GTYPE, regs->gtype); + dmainfo(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg); + dmainfo(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac); + dmainfo(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim); + dmainfo(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs); + dmainfo(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs); + dmainfo(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws); + dmainfo(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws); + dmainfo(" DMA Channel Registers:\n"); + dmainfo(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim); + dmainfo(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa); + dmainfo(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda); + dmainfo(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda); + dmainfo(" CNDC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDC_OFFSET, regs->cndc); + dmainfo(" CUBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CUBC_OFFSET, regs->cubc); + dmainfo(" CBC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CBC_OFFSET, regs->cbc); + dmainfo(" CC[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CC_OFFSET, regs->cc); + dmainfo(" CDSMSP[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDSMSP_OFFSET, regs->cdsmsp); + dmainfo(" CSUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSUS_OFFSET, regs->csus); + dmainfo(" CDUS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDUS_OFFSET, regs->cdus); } -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ #endif /* CONFIG_SAMV7_XDMAC */ diff --git a/arch/arm/src/samv7/sam_xdmac.h b/arch/arm/src/samv7/sam_xdmac.h index 775591f94a5..cfbf14fe0dd 100644 --- a/arch/arm/src/samv7/sam_xdmac.h +++ b/arch/arm/src/samv7/sam_xdmac.h @@ -50,12 +50,6 @@ * Pre-processor Definitions ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_DEBUG_DMA -#endif - /* DMA ******************************************************************************/ /* Flags used to characterize the DMA channel. The naming convention is that one @@ -172,7 +166,7 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result); /* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO struct sam_dmaregs_s { /* Global Registers. @@ -210,7 +204,7 @@ struct sam_dmaregs_s uint32_t csus; /* Channel Source Microblock Stride */ uint32_t cdus; /* Channel Destination Microblock Stride */ }; -#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_DEBUG_DMA_INFO */ /************************************************************************************ * Inline Functions @@ -342,7 +336,7 @@ void sam_dmastop(DMA_HANDLE handle); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); #else # define sam_dmasample(handle,regs) @@ -356,7 +350,7 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_DMA +#ifdef CONFIG_DEBUG_DMA_INFO void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs, const char *msg); #else # define sam_dmadump(handle,regs,msg)