LM4F update from JP

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5586 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/lm/chip/lm3s_memorymap.h

@@ -137,7 +137,7 @@
                                                         /* -0x47fff: Reserved */
 #  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
                                                         /* -0xfcfff: Reserved */
-#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
 #  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                         /* -0x1ffffff: Reserved */
@@ -176,7 +176,7 @@
                                                         /* -0x47fff: Reserved */
 #  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
                                                         /* -0xfcfff: Reserved */
-#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
 #  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                         /* -0x1ffffff: Reserved */
@@ -223,7 +223,7 @@
                                                         /* -0x47fff: Reserved */
 #  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
                                                         /* -0xfcfff: Reserved */
-#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
 #  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                         /* -0x1ffffff: Reserved */

arch/arm/src/lm/chip/lm4f_memorymap.h

@@ -146,7 +146,12 @@
                                                         /* -0xaefff: Reserved */
 #  define LM_EEPROM_BASE    (LM_PERIPH_BASE + 0xaf000)  /* -0xaffff: EEPROM and Key Locker */
                                                         /* -0xf8fff: Reserved */
-/* @TODO */
+#  define LM_SYSEXC_BASE    (LM_PERIPH_BASE + 0xf9000)  /* -0xf9fff: System Exception Control */
+                                                        /* -0xfbfff: Reserved */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
+#  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+#  define LM_UDMA_BASE      (LM_PERIPH_BASE + 0xff000)  /* -0xfffff: Micro Direct Memory Access */
 #else
 #  error "Peripheral base addresses not specified for this Stellaris chip"
 #endif

arch/arm/src/stm32/stm32_otgfsdev.c

@@ -184,8 +184,9 @@
 #define STM32_TRACEERR_NOEP                 0x18
 #define STM32_TRACEERR_NOTCONFIGURED        0x19
 #define STM32_TRACEERR_EPOUTQEMPTY          0x1a
-#define STM32_TRACEERR_EPINQEMPTY           0x1b
+#define STM32_TRACEERR_EPINREQEMPTY         0x1b
 #define STM32_TRACEERR_NOOUTSETUP           0x1c
+#define STM32_TRACEERR_POLLTIMEOUT          0x1d
 
 /* Trace interrupt codes */
 
@@ -1084,6 +1085,7 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
   uint32_t regval;
 #ifdef ENABLE_DTXFSTS_POLLHACK
   int32_t timeout;
+  int avail;
 #endif
   uint8_t *buf;
   int nbytes;
@@ -1113,7 +1115,7 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
   privreq = stm32_rqpeek(privep);
   if (!privreq)
     {
-      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINQEMPTY), privep->epphy);
+      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy);
 
       /* There is no TX transfer in progress and no new pending TX
        * requests to send.  To stop transmitting any data on a particular
@@ -1221,18 +1223,28 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
 
 #ifdef ENABLE_DTXFSTS_POLLHACK
       /* If ENABLE_DTXFSTS_POLLHACK is enabled , then poll DTXFSTS until
-       * space in the TxFIFO is available.  If it doesn't become available,
+       * space in the TxFIFO is available.
-       * in a reasonable amount of time, then just pretend that it is.
        */
        
       for (timeout = 250000; timeout > 0; timeout--)
         {
-          regval  = stm32_getreg(regaddr);
+          avail = stm32_getreg(regaddr) & OTGFS_DTXFSTS_MASK;
-          if ((regval & OTGFS_DTXFSTS_MASK) >= nwords)
+          if (avail >= nwords)
             {
               break;
             }
         }
+
+      /* If it did not become available in a reasonable amount of time,
+       * then just return.  We should come back through this logic later
+       * anyway.
+       */
+
+      if (avail < nwords)
+        {
+          usbtrace(TRACE_DEVERROR(STM32_TRACEERR_POLLTIMEOUT), avail);
+          return;
+        }
 #else
       /* If ENABLE_DTXFSTS_POLLHACK is not enabled, then check once for
        * space in the TxFIFO.  If space in the TxFIFO is not available,
@@ -1290,11 +1302,12 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
   if (privreq->req.xfrd >= privreq->req.len && !privep->zlp)
     {
       usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
+
+      /* We are finished with the request (although the transfer has not
+       * yet completed).
+       */
+
       stm32_req_complete(privep, OK);
-
-      /* The endpoint is no longer transferring data */
-
-      privep->active = false;
     }
 }
 

include/nuttx/usb/usbdev_trace.h

@@ -104,6 +104,7 @@
 #define TRACE_DEVUNINIT          TRACE_EVENT(TRACE_INIT_ID, 0x0002)
 #define TRACE_DEVREGISTER        TRACE_EVENT(TRACE_INIT_ID, 0x0003)
 #define TRACE_DEVUNREGISTER      TRACE_EVENT(TRACE_INIT_ID, 0x0004)
+#define TRACE_DEVINIT_USER       TRACE_EVENT(TRACE_INIT_ID, 0x0005) /* First user-defined */
 
 /* API calls (see usbdev.h) */
 
@@ -117,6 +118,7 @@
 #define TRACE_EPCANCEL           TRACE_EVENT(TRACE_EP_ID, 0x0008)
 #define TRACE_EPSTALL            TRACE_EVENT(TRACE_EP_ID, 0x0009)
 #define TRACE_EPRESUME           TRACE_EVENT(TRACE_EP_ID, 0x000a)
+#define TRACE_EPAPI_USER         TRACE_EVENT(TRACE_EP_ID, 0x000b) /* First user-defined */
 
 #define TRACE_DEVALLOCEP         TRACE_EVENT(TRACE_DEV_ID, 0x0001)
 #define TRACE_DEVFREEEP          TRACE_EVENT(TRACE_DEV_ID, 0x0002)
@@ -124,6 +126,7 @@
 #define TRACE_DEVWAKEUP          TRACE_EVENT(TRACE_DEV_ID, 0x0004)
 #define TRACE_DEVSELFPOWERED     TRACE_EVENT(TRACE_DEV_ID, 0x0005)
 #define TRACE_DEVPULLUP          TRACE_EVENT(TRACE_DEV_ID, 0x0006)
+#define TRACE_DEVAPI_USER        TRACE_EVENT(TRACE_DEV_ID, 0x0007) /* First user-defined */
 
 #define TRACE_CLASSBIND          TRACE_EVENT(TRACE_CLASS_ID, 0x0001)
 #define TRACE_CLASSUNBIND        TRACE_EVENT(TRACE_CLASS_ID, 0x0002)
@@ -135,6 +138,8 @@
 #define TRACE_CLASSRDCOMPLETE    TRACE_EVENT(TRACE_CLASS_ID, 0x0007)
 #define TRACE_CLASSWRCOMPLETE    TRACE_EVENT(TRACE_CLASS_ID, 0x0008)
 
+#define TRACE_CLASSAPI_USER      TRACE_EVENT(TRACE_CLASS_ID, 0x0009) /* First user-defined */
+
 #define TRACE_CLASSAPI(id)       TRACE_EVENT(TRACE_CLASSAPI_ID, id)
 
 #define TRACE_CLASSSTATE(id)     TRACE_EVENT(TRACE_CLASSSTATE_ID, id)