LM4F update from JP

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5586 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/lm/chip/lm3s_memorymap.h

@@ -137,7 +137,7 @@
                                                         /* -0x47fff: Reserved */
 #  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
                                                         /* -0xfcfff: Reserved */
-#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
 #  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                         /* -0x1ffffff: Reserved */
@@ -176,7 +176,7 @@
                                                         /* -0x47fff: Reserved */
 #  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
                                                         /* -0xfcfff: Reserved */
-#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
 #  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                         /* -0x1ffffff: Reserved */
@@ -223,7 +223,7 @@
                                                         /* -0x47fff: Reserved */
 #  define LM_ETHCON_BASE    (LM_PERIPH_BASE + 0x48000)  /* -0x48fff: Ethernet Controller */
                                                         /* -0xfcfff: Reserved */
-#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Ethernet Controller */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
 #  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
 #  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
                                                         /* -0x1ffffff: Reserved */

arch/arm/src/lm/chip/lm4f_memorymap.h

@@ -146,7 +146,12 @@
                                                         /* -0xaefff: Reserved */
 #  define LM_EEPROM_BASE    (LM_PERIPH_BASE + 0xaf000)  /* -0xaffff: EEPROM and Key Locker */
                                                         /* -0xf8fff: Reserved */
-/* @TODO */
+#  define LM_SYSEXC_BASE    (LM_PERIPH_BASE + 0xf9000)  /* -0xf9fff: System Exception Control */
+                                                        /* -0xfbfff: Reserved */
+#  define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000)  /* -0xfcfff: Hibernation Controller */
+#  define LM_FLASHCON_BASE  (LM_PERIPH_BASE + 0xfd000)  /* -0xfdfff: FLASH Control */
+#  define LM_SYSCON_BASE    (LM_PERIPH_BASE + 0xfe000)  /* -0xfefff: System Control */
+#  define LM_UDMA_BASE      (LM_PERIPH_BASE + 0xff000)  /* -0xfffff: Micro Direct Memory Access */
 #else
 #  error "Peripheral base addresses not specified for this Stellaris chip"
 #endif

arch/arm/src/lm/chip/lm_gpio.h

@@ -2,7 +2,8 @@
  * arch/arm/src/lm/chip/lm_gpio.h
  *
  *   Copyright (C) 2009-2010, 2013 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            Jose Pablo Carballo <jcarballo@nx-engineering.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -68,6 +69,14 @@
 #define LM_GPIO_DEN_OFFSET          0x51C /* GPIO Digital Enable */
 #define LM_GPIO_LOCK_OFFSET         0x520 /* GPIO Lock */
 #define LM_GPIO_CR_OFFSET           0x524 /* GPIO Commit */
+
+#ifdef LM4F
+#  define LM_GPIO_AMSEL_OFFSET      0x528 /* GPIO Analog Mode Select */
+#  define LM_GPIO_PCTL_OFFSET       0x52c /* GPIO Port Control */
+#  define LM_GPIO_ADCCTL_OFFSET     0x530 /* GPIO ADC Control */
+#  define LM_GPIO_DMACTL_OFFSET     0x534 /* GPIO DMA Control */
+#endif
+
 #define LM_GPIO_PERIPHID4_OFFSET    0xfd0 /* GPIO Peripheral Identification 4 */
 #define LM_GPIO_PERIPHID5_OFFSET    0xfd4 /* GPIO Peripheral Identification 5 */
 #define LM_GPIO_PERIPHID6_OFFSET    0xfd8 /* GPIO Peripheral Identification 6 */
@@ -83,6 +92,8 @@
 
 /* GPIO Register Addresses **********************************************************/
 
+#if LM_NPORTS > 0
+
 #  define LM_GPIOA_DATA             (LM_GPIOA_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOA_DIR              (LM_GPIOA_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOA_IS               (LM_GPIOA_BASE + LM_GPIO_IS_OFFSET)
@@ -103,6 +114,14 @@
 #  define LM_GPIOA_DEN              (LM_GPIOA_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOA_LOCK             (LM_GPIOA_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOA_CR               (LM_GPIOA_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOA_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOA_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOA_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOA_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOA_PERIPHID4        (LM_GPIOA_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOA_PERIPHID5        (LM_GPIOA_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOA_PERIPHID6        (LM_GPIOA_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -116,6 +135,8 @@
 #  define LM_GPIOA_PCELLID2         (LM_GPIOA_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOA_PCELLID3         (LM_GPIOA_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 1
+
 #  define LM_GPIOB_DATA             (LM_GPIOB_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOB_DIR              (LM_GPIOB_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOB_IS               (LM_GPIOB_BASE + LM_GPIO_IS_OFFSET)
@@ -136,6 +157,14 @@
 #  define LM_GPIOB_DEN              (LM_GPIOB_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOB_LOCK             (LM_GPIOB_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOB_CR               (LM_GPIOB_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOB_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOB_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOB_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOB_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOB_PERIPHID4        (LM_GPIOB_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOB_PERIPHID5        (LM_GPIOB_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOB_PERIPHID6        (LM_GPIOB_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -149,6 +178,8 @@
 #  define LM_GPIOB_PCELLID2         (LM_GPIOB_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOB_PCELLID3         (LM_GPIOB_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 2
+
 #  define LM_GPIOC_DATA             (LM_GPIOC_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOC_DIR              (LM_GPIOC_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOC_IS               (LM_GPIOC_BASE + LM_GPIO_IS_OFFSET)
@@ -169,6 +200,14 @@
 #  define LM_GPIOC_DEN              (LM_GPIOC_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOC_LOCK             (LM_GPIOC_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOC_CR               (LM_GPIOC_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOC_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOC_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOC_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOC_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOC_PERIPHID4        (LM_GPIOC_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOC_PERIPHID5        (LM_GPIOC_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOC_PERIPHID6        (LM_GPIOC_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -182,6 +221,8 @@
 #  define LM_GPIOC_PCELLID2         (LM_GPIOC_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOC_PCELLID3         (LM_GPIOC_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 3
+
 #  define LM_GPIOD_DATA             (LM_GPIOD_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOD_DIR              (LM_GPIOD_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOD_IS               (LM_GPIOD_BASE + LM_GPIO_IS_OFFSET)
@@ -202,6 +243,14 @@
 #  define LM_GPIOD_DEN              (LM_GPIOD_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOD_LOCK             (LM_GPIOD_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOD_CR               (LM_GPIOD_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOD_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOD_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOD_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOD_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOD_PERIPHID4        (LM_GPIOD_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOD_PERIPHID5        (LM_GPIOD_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOD_PERIPHID6        (LM_GPIOD_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -215,6 +264,8 @@
 #  define LM_GPIOD_PCELLID2         (LM_GPIOD_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOD_PCELLID3         (LM_GPIOD_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 4
+
 #  define LM_GPIOE_DATA             (LM_GPIOE_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOE_DIR              (LM_GPIOE_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOE_IS               (LM_GPIOE_BASE + LM_GPIO_IS_OFFSET)
@@ -235,6 +286,14 @@
 #  define LM_GPIOE_DEN              (LM_GPIOE_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOE_LOCK             (LM_GPIOE_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOE_CR               (LM_GPIOE_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOE_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOE_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOE_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOE_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOE_PERIPHID4        (LM_GPIOE_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOE_PERIPHID5        (LM_GPIOE_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOE_PERIPHID6        (LM_GPIOE_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -248,6 +307,8 @@
 #  define LM_GPIOE_PCELLID2         (LM_GPIOE_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOE_PCELLID3         (LM_GPIOE_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 5
+
 #  define LM_GPIOF_DATA             (LM_GPIOF_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOF_DIR              (LM_GPIOF_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOF_IS               (LM_GPIOF_BASE + LM_GPIO_IS_OFFSET)
@@ -268,6 +329,14 @@
 #  define LM_GPIOF_DEN              (LM_GPIOF_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOF_LOCK             (LM_GPIOF_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOF_CR               (LM_GPIOF_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOF_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOF_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOF_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOF_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOF_PERIPHID4        (LM_GPIOF_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOF_PERIPHID5        (LM_GPIOF_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOF_PERIPHID6        (LM_GPIOF_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -281,6 +350,8 @@
 #  define LM_GPIOF_PCELLID2         (LM_GPIOF_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOF_PCELLID3         (LM_GPIOF_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 6
+
 #  define LM_GPIOG_DATA             (LM_GPIOG_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOG_DIR              (LM_GPIOG_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOG_IS               (LM_GPIOG_BASE + LM_GPIO_IS_OFFSET)
@@ -301,6 +372,14 @@
 #  define LM_GPIOG_DEN              (LM_GPIOG_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOG_LOCK             (LM_GPIOG_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOG_CR               (LM_GPIOG_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOG_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOG_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOG_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOG_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOG_PERIPHID4        (LM_GPIOG_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOG_PERIPHID5        (LM_GPIOG_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOG_PERIPHID6        (LM_GPIOG_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -314,6 +393,8 @@
 #  define LM_GPIOG_PCELLID2         (LM_GPIOG_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOG_PCELLID3         (LM_GPIOG_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 7
+
 #  define LM_GPIOH_DATA             (LM_GPIOH_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOH_DIR              (LM_GPIOH_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOH_IS               (LM_GPIOH_BASE + LM_GPIO_IS_OFFSET)
@@ -334,6 +415,14 @@
 #  define LM_GPIOH_DEN              (LM_GPIOH_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOH_LOCK             (LM_GPIOH_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOH_CR               (LM_GPIOH_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOH_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOH_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOH_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOH_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOH_PERIPHID4        (LM_GPIOH_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOH_PERIPHID5        (LM_GPIOH_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOH_PERIPHID6        (LM_GPIOH_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -347,6 +436,8 @@
 #  define LM_GPIOH_PCELLID2         (LM_GPIOH_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOH_PCELLID3         (LM_GPIOH_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#elif LM_NPORTS > 8
+
 #  define LM_GPIOJ_DATA             (LM_GPIOJ_BASE + LM_GPIO_DATA_OFFSET)
 #  define LM_GPIOJ_DIR              (LM_GPIOJ_BASE + LM_GPIO_DIR_OFFSET)
 #  define LM_GPIOJ_IS               (LM_GPIOJ_BASE + LM_GPIO_IS_OFFSET)
@@ -367,6 +458,14 @@
 #  define LM_GPIOJ_DEN              (LM_GPIOJ_BASE + LM_GPIO_DEN_OFFSET)
 #  define LM_GPIOJ_LOCK             (LM_GPIOJ_BASE + LM_GPIO_LOCK_OFFSET)
 #  define LM_GPIOJ_CR               (LM_GPIOJ_BASE + LM_GPIO_CR_OFFSET)
+
+#  ifdef LM4F
+#    define LM_GPIOJ_AMSEL          (LM_GPIOA_BASE + LM_GPIO_AMSEL_OFFSET)
+#    define LM_GPIOJ_PCTL           (LM_GPIOA_BASE + LM_GPIO_PCTL_OFFSET)
+#    define LM_GPIOJ_ADCCTL         (LM_GPIOA_BASE + LM_GPIO_ADCCTL_OFFSET)
+#    define LM_GPIOJ_DMACTL         (LM_GPIOA_BASE + LM_GPIO_DMACTL_OFFSET)
+#  endif
+
 #  define LM_GPIOJ_PERIPHID4        (LM_GPIOJ_BASE + LM_GPIO_PERIPHID4_OFFSET)
 #  define LM_GPIOJ_PERIPHID5        (LM_GPIOJ_BASE + LM_GPIO_PERIPHID5_OFFSET)
 #  define LM_GPIOJ_PERIPHID6        (LM_GPIOJ_BASE + LM_GPIO_PERIPHID6_OFFSET)
@@ -380,6 +479,8 @@
 #  define LM_GPIOJ_PCELLID2         (LM_GPIOJ_BASE + LM_GPIO_PCELLID2_OFFSET)
 #  define LM_GPIOJ_PCELLID3         (LM_GPIOJ_BASE + LM_GPIO_PCELLID3_OFFSET)
 
+#endif /* LM_NPORTS */
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/

arch/arm/src/stm32/stm32_otgfsdev.c

@@ -184,8 +184,9 @@
 #define STM32_TRACEERR_NOEP                 0x18
 #define STM32_TRACEERR_NOTCONFIGURED        0x19
 #define STM32_TRACEERR_EPOUTQEMPTY          0x1a
-#define STM32_TRACEERR_EPINQEMPTY           0x1b
+#define STM32_TRACEERR_EPINREQEMPTY         0x1b
 #define STM32_TRACEERR_NOOUTSETUP           0x1c
+#define STM32_TRACEERR_POLLTIMEOUT          0x1d
 
 /* Trace interrupt codes */
 
@@ -1084,6 +1085,7 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
   uint32_t regval;
 #ifdef ENABLE_DTXFSTS_POLLHACK
   int32_t timeout;
+  int avail;
 #endif
   uint8_t *buf;
   int nbytes;
@@ -1113,7 +1115,7 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
   privreq = stm32_rqpeek(privep);
   if (!privreq)
     {
-      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINQEMPTY), privep->epphy);
+      usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy);
 
       /* There is no TX transfer in progress and no new pending TX
        * requests to send.  To stop transmitting any data on a particular
@@ -1221,18 +1223,28 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
 
 #ifdef ENABLE_DTXFSTS_POLLHACK
       /* If ENABLE_DTXFSTS_POLLHACK is enabled , then poll DTXFSTS until
-       * space in the TxFIFO is available.  If it doesn't become available,
+       * space in the TxFIFO is available.
-       * in a reasonable amount of time, then just pretend that it is.
        */
        
       for (timeout = 250000; timeout > 0; timeout--)
         {
-          regval  = stm32_getreg(regaddr);
+          avail = stm32_getreg(regaddr) & OTGFS_DTXFSTS_MASK;
-          if ((regval & OTGFS_DTXFSTS_MASK) >= nwords)
+          if (avail >= nwords)
             {
               break;
             }
         }
+
+      /* If it did not become available in a reasonable amount of time,
+       * then just return.  We should come back through this logic later
+       * anyway.
+       */
+
+      if (avail < nwords)
+        {
+          usbtrace(TRACE_DEVERROR(STM32_TRACEERR_POLLTIMEOUT), avail);
+          return;
+        }
 #else
       /* If ENABLE_DTXFSTS_POLLHACK is not enabled, then check once for
        * space in the TxFIFO.  If space in the TxFIFO is not available,
@@ -1290,11 +1302,12 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
   if (privreq->req.xfrd >= privreq->req.len && !privep->zlp)
     {
       usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd);
+
+      /* We are finished with the request (although the transfer has not
+       * yet completed).
+       */
+
       stm32_req_complete(privep, OK);
-
-      /* The endpoint is no longer transferring data */
-
-      privep->active = false;
     }
 }
 

include/nuttx/usb/usbdev_trace.h

@@ -104,6 +104,7 @@
 #define TRACE_DEVUNINIT          TRACE_EVENT(TRACE_INIT_ID, 0x0002)
 #define TRACE_DEVREGISTER        TRACE_EVENT(TRACE_INIT_ID, 0x0003)
 #define TRACE_DEVUNREGISTER      TRACE_EVENT(TRACE_INIT_ID, 0x0004)
+#define TRACE_DEVINIT_USER       TRACE_EVENT(TRACE_INIT_ID, 0x0005) /* First user-defined */
 
 /* API calls (see usbdev.h) */
 
@@ -117,6 +118,7 @@
 #define TRACE_EPCANCEL           TRACE_EVENT(TRACE_EP_ID, 0x0008)
 #define TRACE_EPSTALL            TRACE_EVENT(TRACE_EP_ID, 0x0009)
 #define TRACE_EPRESUME           TRACE_EVENT(TRACE_EP_ID, 0x000a)
+#define TRACE_EPAPI_USER         TRACE_EVENT(TRACE_EP_ID, 0x000b) /* First user-defined */
 
 #define TRACE_DEVALLOCEP         TRACE_EVENT(TRACE_DEV_ID, 0x0001)
 #define TRACE_DEVFREEEP          TRACE_EVENT(TRACE_DEV_ID, 0x0002)
@@ -124,6 +126,7 @@
 #define TRACE_DEVWAKEUP          TRACE_EVENT(TRACE_DEV_ID, 0x0004)
 #define TRACE_DEVSELFPOWERED     TRACE_EVENT(TRACE_DEV_ID, 0x0005)
 #define TRACE_DEVPULLUP          TRACE_EVENT(TRACE_DEV_ID, 0x0006)
+#define TRACE_DEVAPI_USER        TRACE_EVENT(TRACE_DEV_ID, 0x0007) /* First user-defined */
 
 #define TRACE_CLASSBIND          TRACE_EVENT(TRACE_CLASS_ID, 0x0001)
 #define TRACE_CLASSUNBIND        TRACE_EVENT(TRACE_CLASS_ID, 0x0002)
@@ -135,6 +138,8 @@
 #define TRACE_CLASSRDCOMPLETE    TRACE_EVENT(TRACE_CLASS_ID, 0x0007)
 #define TRACE_CLASSWRCOMPLETE    TRACE_EVENT(TRACE_CLASS_ID, 0x0008)
 
+#define TRACE_CLASSAPI_USER      TRACE_EVENT(TRACE_CLASS_ID, 0x0009) /* First user-defined */
+
 #define TRACE_CLASSAPI(id)       TRACE_EVENT(TRACE_CLASSAPI_ID, id)
 
 #define TRACE_CLASSSTATE(id)     TRACE_EVENT(TRACE_CLASSSTATE_ID, id)