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SAMA5 GMAC: Various fixes from initial debug

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This commit is contained in:
Gregory Nutt
2013-09-29 15:03:57 -06:00
parent dc4c6bcb57
commit 7ee6ded1c2
5 changed files with 37 additions and 39 deletions
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include/nuttx/net/gmii.h
+3 -3
View File
@@ -134,7 +134,7 @@
#define GMII_PHYID2_REV_MASK MII_PHYID2_REV_MASK
#define GMII_PHYID2_REV(n) MII_PHYID2_REV(n)
#define GMII_PHYID2_MODEL_SHIFT MII_PHYID2_MODEL_SHIFT
#define GMII_PHYID2_MODEL_MASK MII_PHYID2_MODEL
#define GMII_PHYID2_MODEL_MASK MII_PHYID2_MODEL_MASK
# define GMII_PHYID2_MODEL(n) MII_PHYID2_MODEL(n)
#define GMII_PHYID2_OUI_SHIFT MII_PHYID2_OUI_SHIFT
#define GMII_PHYID2_OUI_MASK MII_PHYID2_OUI_MASK
@@ -242,7 +242,7 @@
#define GMII_1000BTCR_TESTMODE_SHIFT (13) /* Bits 13-15: Test Mode */
#define GMII_1000BTCR_TESTMODE_MASK (7 << GMII_1000BTCR_TESTMODE_SHIFT)
# define GMII_1000BTCR_MODE_NORMAL (0 << GMII_1000BTCR_TESTMODE_SHIFT)
# define GMII_1000BTCR_TESTMODE(n) ((n) << GMII_1000BTCR_TESTMODE_SHIFT) /* n=1-4 */
# define GMII_1000BTCR_TESTMODE(n) ((uint16_t)(n) << GMII_1000BTCR_TESTMODE_SHIFT) /* n=1-4 */
/* 1000BASE-T Status Register */
@@ -260,7 +260,7 @@
#define GMII_ERCR_ADDR_SHIFT (0) /* Bits 0-7: Select extended register address */
#define GMII_ERCR_ADDR_MASK (0xff << GMII_ERCR_ADDR_SHIFT)
# define GMII_ERCR_ADDR(n) ((n) << GMII_ERCR_ADDR_SHIFT)
# define GMII_ERCR_ADDR(n) ((uint16_t)(n) << GMII_ERCR_ADDR_SHIFT)
#define GMII_ERCR_PAGE (1 << 8) /* Bit 8: Select page for extended register */
/* Bits 9-14: Reserved */
#define GMII_ERCR_READ (0) /* Bit 15: 0=Read extended register */
include/nuttx/net/mii.h
+6 -6
View File
@@ -204,13 +204,13 @@
#define MII_PHYID2_REV_SHIFT (0) /* Bits 0-3: Revision number mask */
#define MII_PHYID2_REV_MASK (15 << MII_PHYID2_REV_SHIFT)
# define MII_PHYID2_REV(n) ((n) << MII_PHYID2_REV_SHIFT)
# define MII_PHYID2_REV(n) ((uint16_t)(n) << MII_PHYID2_REV_SHIFT)
#define MII_PHYID2_MODEL_SHIFT (4) /* Bits 4-9: Model number mask */
#define MII_PHYID2_MODEL_MASK (0x3f << MII_PHYID2_MODEL_SHIFT)
# define MII_PHYID2_MODEL(n) ((n) << MII_PHYID2_MODEL_SHIFT)
# define MII_PHYID2_MODEL(n) ((uint16_t)(n) << MII_PHYID2_MODEL_SHIFT)
#define MII_PHYID2_OUI_SHIFT (10) /* Bits 10-15: OUI mask [24:19] */
#define MII_PHYID2_OUI_MASK (0x3f << MII_PHYID2_OUI_SHIFT)
# define MII_PHYID2_OUI(n) ((n) << MII_PHYID2_OUI_SHIFT)
# define MII_PHYID2_OUI(n) ((uint16_t)(n) << MII_PHYID2_OUI_SHIFT)
/* Advertisement control register bit definitions */
@@ -285,9 +285,9 @@
/* MMD access control register */
#define MII_MMDCONTROL_DEVAD_SHIFT (0) /* Bits 0-4: Device address */
#define MII_MMDCONTROL_DEVAD_MASK (31 << MII_MMDCONTROL_DEVAD_SHIFT)
# define MII_MMDCONTROL_DEVAD(n) ((n) << MII_MMDCONTROL_DEVAD_SHIFT)
#define MII_MMDCONTROL_DEVAD_SHIFT (0) /* Bits 0-4: Device address */
#define MII_MMDCONTROL_DEVAD_MASK (31 << MII_MMDCONTROL_DEVAD_SHIFT)
# define MII_MMDCONTROL_DEVAD(n) ((uint16_t)(n) << MII_MMDCONTROL_DEVAD_SHIFT)
/* Bits 5-13: Reserved */
#define MII_MMDCONTROL_FUNC_SHIFT (14) /* Bits 14-15: Function */
#define MII_MMDCONTROL_FUNC_MASK (3 << MII_MMDCONTROL_FUNC_SHIFT)