diff --git a/boards/Kconfig b/boards/Kconfig index 9ff85f9b492..5c57c809996 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1915,6 +1915,15 @@ config ARCH_BOARD_WEACT_STM32H750 ---help--- This is WeAct MiniSTM32H7xx (STM32H750VB) board. +config ARCH_BOARD_NUCLEO_H723ZG + bool "STM32H723 Nucleo H723ZG" + depends on ARCH_CHIP_STM32H723ZG + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + STMicro Nucleo H723ZG board based on the STMicro STM32H723ZG MCU. + config ARCH_BOARD_NUCLEO_H743ZI bool "STM32H743 Nucleo H743ZI" depends on ARCH_CHIP_STM32H743ZI @@ -3699,6 +3708,7 @@ config ARCH_BOARD default "nucleo-g0b1re" if ARCH_BOARD_NUCLEO_G0B1RE default "weact-stm32h743" if ARCH_BOARD_WEACT_STM32H743 default "weact-stm32h750" if ARCH_BOARD_WEACT_STM32H750 + default "nucleo-h723zg" if ARCH_BOARD_NUCLEO_H723ZG default "nucleo-h743zi" if ARCH_BOARD_NUCLEO_H743ZI default "nucleo-h743zi2" if ARCH_BOARD_NUCLEO_H743ZI2 default "nucleo-h745zi" if ARCH_BOARD_NUCLEO_H745ZI @@ -4435,6 +4445,9 @@ endif if ARCH_BOARD_WEACT_STM32H750 source "boards/arm/stm32h7/weact-stm32h750/Kconfig" endif +if ARCH_BOARD_NUCLEO_H723ZG +source "boards/arm/stm32h7/nucleo-h723zg/Kconfig" +endif if ARCH_BOARD_NUCLEO_H743ZI source "boards/arm/stm32h7/nucleo-h743zi/Kconfig" endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h723zg/CMakeLists.txt new file mode 100644 index 00000000000..e7c95cc604b --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32h7/nucleo-h723zg/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32h7/nucleo-h723zg/Kconfig b/boards/arm/stm32h7/nucleo-h723zg/Kconfig new file mode 100644 index 00000000000..706098f5184 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NUCLEO_H723ZG + +endif # ARCH_BOARD_NUCLEO_H723ZG diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig new file mode 100644 index 00000000000..e12cf45c78a --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig @@ -0,0 +1,91 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h723zg" +CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H723ZG=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=79943 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=4 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x24000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_DTCMEXCLUDE=y +CONFIG_STM32H7_ETHMAC=y +CONFIG_STM32H7_FLASH_OVERRIDE_G=y +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_PHYSR=31 +CONFIG_STM32H7_PHYSR_100FD=0x0018 +CONFIG_STM32H7_PHYSR_100HD=0x0008 +CONFIG_STM32H7_PHYSR_10FD=0x0014 +CONFIG_STM32H7_PHYSR_10HD=0x0004 +CONFIG_STM32H7_PHYSR_ALTCONFIG=y +CONFIG_STM32H7_PHYSR_ALTMODE=0x001c +CONFIG_STM32H7_SRAM4EXCLUDE=y +CONFIG_STM32H7_USART3=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST=y +CONFIG_USBHOST_MSC=y +CONFIG_USBHOST_MSC_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig new file mode 100644 index 00000000000..69b4aabb4e6 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h723zg" +CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H723ZG=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=66627 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXPERIMENTAL=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LINE_MAX=64 +CONFIG_MM_REGIONS=4 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=131072 +CONFIG_RAM_START=0x24000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_DTCMEXCLUDE=y +CONFIG_STM32H7_FLASH_OVERRIDE_G=y +CONFIG_STM32H7_SRAM4EXCLUDE=y +CONFIG_STM32H7_USART3=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/include/board.h b/boards/arm/stm32h7/nucleo-h723zg/include/board.h new file mode 100644 index 00000000000..3e152e45dca --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/include/board.h @@ -0,0 +1,521 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Do not include STM32 H7 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Nucleo-144 board provides the following clock sources: + * + * MCO: 8 MHz from MCO output of ST-LINK is used as input clock (default) + * X2: 32.768 KHz crystal for LSE + * X3: HSE crystal oscillator (not provided) + * + * So we have these clock source available within the STM32 + * + * HSI: 16 MHz RC factory-trimmed + * LSI: 32 KHz RC + * HSE: 8 MHz from MCO output of ST-LINK + * LSE: 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul /* ST-LINK MCO */ + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE = 8,000,000 + * + * To use HSE, configure the solder bridges on the board: + * + * - SB148, SB8 and SB9 OFF + * - SB112 and SB149 ON + * + * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected. + * VCOH otherwise. + * + * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * Subject to: + * + * 1 <= PLLM <= 63 + * 4 <= PLLN <= 512 + * 150 MHz <= PLL_VCOL <= 420MHz + * 192 MHz <= PLL_VCOH <= 836MHz + * + * SYSCLK = PLL_VCO / PLLP + * CPUCLK = SYSCLK / D1CPRE + * Subject to + * + * PLLP1 = {2, 4, 6, 8, ..., 128} + * PLLP2,3 = {2, 3, 4, ..., 128} + * CPUCLK <= 400 MHz + */ + +#define STM32_BOARD_USEHSE +#define STM32_HSEBYP_ENABLE + +#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE + +/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR + * + * PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz + * + * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz + * PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz + * PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz + */ + +#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \ + RCC_PLLCFGR_DIVP1EN | \ + RCC_PLLCFGR_DIVQ1EN | \ + RCC_PLLCFGR_DIVR1EN) +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200) +#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) + +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200) +#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) + +/* PLL2 */ + +#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \ + RCC_PLLCFGR_DIVP2EN) +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(200) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(40) +#define STM32_PLLCFG_PLL2Q 0 +#define STM32_PLLCFG_PLL2R 0 + +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2) +#define STM32_PLL2Q_FREQUENCY +#define STM32_PLL2R_FREQUENCY + +/* PLL3 */ + +#define STM32_PLLCFG_PLL3CFG 0 +#define STM32_PLLCFG_PLL3M 0 +#define STM32_PLLCFG_PLL3N 0 +#define STM32_PLLCFG_PLL3P 0 +#define STM32_PLLCFG_PLL3Q 0 +#define STM32_PLLCFG_PLL3R 0 + +#define STM32_VCO3_FREQUENCY +#define STM32_PLL3P_FREQUENCY +#define STM32_PLL3Q_FREQUENCY +#define STM32_PLL3R_FREQUENCY + +/* SYSCLK = PLL1P = 400 MHz + * CPUCLK = SYSCLK / 1 = 400 MHz + */ + +#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) +#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) +#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) + +/* Configure Clock Assignments */ + +/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max) + * HCLK1 = HCLK2 = HCLK3 = HCLK4 + */ + +#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ +#define STM32_ACLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ +#define STM32_HCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ + +/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK2 = HCLK / 4 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB3 clock (PCLK3) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK3 = HCLK / 4 */ +#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB4 clock (PCLK4) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK4 = HCLK / 4 */ +#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timer clock frequencies */ + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Kernel Clock Configuration + * + * Note: look at Table 54 in ST Manual + */ + +/* I2C123 clock source - HSI */ + +#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI + +/* I2C4 clock source - HSI */ + +#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI + +/* SPI123 clock source - PLL1Q */ + +#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1 + +/* SPI45 clock source - APB (PCLK2?) */ + +#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB + +/* SPI6 clock source - APB (PCLK4) */ + +#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PCLK4 + +/* USB 1 and 2 clock source - HSI48 */ + +#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48 + +/* ADC 1 2 3 clock source - pll2_pclk */ + +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 + +/* FLASH wait states + * + * ------------ ---------- ----------- + * Vcore MAX ACLK WAIT STATES + * ------------ ---------- ----------- + * 1.15-1.26 V 70 MHz 0 + * (VOS1 level) 140 MHz 1 + * 210 MHz 2 + * 1.05-1.15 V 55 MHz 0 + * (VOS2 level) 110 MHz 1 + * 165 MHz 2 + * 220 MHz 3 + * 0.95-1.05 V 45 MHz 0 + * (VOS3 level) 90 MHz 1 + * 135 MHz 2 + * 180 MHz 3 + * 225 MHz 4 + * ------------ ---------- ----------- + */ + +#define BOARD_FLASH_WAITSTATES 4 + +/* SDMMC definitions ********************************************************/ + +/* Init 400kHz, PLL1Q/(2*250) */ + +#define STM32_SDMMC_INIT_CLKDIV (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* Just set these to 25 MHz for now, + * PLL1Q/(2*4), for default speed 12.5MB/s + */ + +#define STM32_SDMMC_MMCXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE + +/* Ethernet definitions *****************************************************/ + +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2 | GPIO_SPEED_100MHz) /* PG13 */ +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHz) /* PB13 */ +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2 | GPIO_SPEED_100MHz) /* PG11 */ +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0 | GPIO_SPEED_100MHz) /* PC1 */ +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0 | GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0 | GPIO_SPEED_100MHz) /* PC4 */ +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0 | GPIO_SPEED_100MHz) /* PC5 */ +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHz) /* PA7 */ +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHz) /* PA1 */ + +/* LED definitions **********************************************************/ + +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Yellow LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_NLEDS 3 + +#define BOARD_LED_GREEN BOARD_LED1 +#define BOARD_LED_YELLOW BOARD_LED2 +#define BOARD_LED_RED BOARD_LED3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_autoleds.c. + * The LEDs are used to encode OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Green Yellow Red + * ---------------------- -------------------------- ----- ------ --- + */ +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled ON OFF OFF */ +#define LED_STACKCREATED 3 /* Idle stack created ON ON OFF */ +#define LED_INIRQ 4 /* In an interrupt N/C GLOW N/C */ +#define LED_SIGNAL 5 /* In a signal handler GLOW N/C N/C */ +#define LED_ASSERTION 6 /* An assertion failed N/C GLOW GLOW */ +#define LED_PANIC 7 /* The system has crashed OFF N/C Blink */ +#define LED_IDLE 8 /* MCU is is sleep mode OFF OFF ON */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions *******************************************************/ + +/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is + * connected to GPIO PI11. + * A high value will be sensed when the button is depressed. + */ + +#define BUTTON_USER 0 +#define NUM_BUTTONS 1 +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +/* ADC */ + +#define GPIO_ADC12_INP5 GPIO_ADC12_INP5_0 /* PB1, channel 5 */ +#define GPIO_ADC123_INP10 GPIO_ADC123_INP10_0 /* PC0, channel 10 */ +#define GPIO_ADC123_INP12 GPIO_ADC123_INP12_0 /* PC2, channel 12 */ +#define GPIO_ADC12_INP13 GPIO_ADC12_INP13_0 /* PC3, channel 13 */ +#define GPIO_ADC12_INP15 GPIO_ADC12_INP15_0 /* PA3, channel 15 */ +#define GPIO_ADC12_INP18 GPIO_ADC12_INP18_0 /* PA4, channel 18 */ +#define GPIO_ADC12_INP19 GPIO_ADC12_INP19_0 /* PA5, channel 19 */ +#define GPIO_ADC123_INP7 GPIO_ADC12_INP7_0 /* PA7, channel 7 */ +#define GPIO_ADC123_INP11 GPIO_ADC123_INP11_0 /* PC1, channel 11 */ +#define GPIO_ADC2_INP2 GPIO_ADC2_INP2_0 /* PF13, channel 2 */ +#define GPIO_ADC12_INP3 GPIO_ADC12_INP3_0 /* PA6, channel 3 */ +#define GPIO_ADC12_INP14 GPIO_ADC12_INP14_0 /* PA2, channel 14 */ +#define GPIO_ADC12_INP4 GPIO_ADC12_INP4_0 /* PC4, channel 4 */ +#define GPIO_ADC12_INP8 GPIO_ADC12_INP8_0 /* PC5, channel 8 */ + +/* USART3 (Nucleo Virtual Console) */ + +#define GPIO_USART3_RX (GPIO_USART3_RX_3 | GPIO_SPEED_100MHz) /* PD9 */ +#define GPIO_USART3_TX (GPIO_USART3_TX_3 | GPIO_SPEED_100MHz) /* PD8 */ + +#define DMAMAP_USART3_RX DMAMAP_DMA12_USART3RX_0 +#define DMAMAP_USART3_TX DMAMAP_DMA12_USART3TX_1 + +/* USART6 (Arduino Serial Shield) */ + +#define GPIO_USART6_RX (GPIO_USART6_RX_2 | GPIO_SPEED_100MHz) /* PG9 */ +#define GPIO_USART6_TX (GPIO_USART6_TX_2 | GPIO_SPEED_100MHz) /* PG14 */ + +/* I2C1 Use Nucleo I2C1 pins */ + +#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2 | GPIO_SPEED_50MHz) /* PB8 - D15 */ +#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2 | GPIO_SPEED_50MHz) /* PB9 - D14 */ + +/* I2C2 Use Nucleo I2C2 pins */ + +#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_2 | GPIO_SPEED_50MHz) /* PF1 - D69 */ +#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2 | GPIO_SPEED_50MHz) /* PF0 - D68 */ +#define GPIO_I2C2_SMBA (GPIO_I2C2_SMBA_2 | GPIO_SPEED_50MHz) /* PF2 - D70 */ + +/* SPI3 */ + +#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1 | GPIO_SPEED_50MHz) /* PB4 */ +#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_4 | GPIO_SPEED_50MHz) /* PB5 */ +#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1 | GPIO_SPEED_50MHz) /* PB3 */ +#define GPIO_SPI3_NSS (GPIO_SPI3_NSS_2 | GPIO_SPEED_50MHz) /* PA4 */ + +/* TIM1 - Advanced Timer 16-bit (4 channels) */ +#define GPIO_TIM1_CH1IN (GPIO_TIM1_CH1IN_2) /* PE9 */ +#define GPIO_TIM1_CH2IN (GPIO_TIM1_CH2IN_2) /* PE11 */ +#define GPIO_TIM1_CH3IN (GPIO_TIM1_CH3IN_2) /* PE13 */ +#define GPIO_TIM1_CH4IN (GPIO_TIM1_CH4IN_2) /* PE14 */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2) /* PE9 - D6 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_3) /* PE8 - D42 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2) /* PE11 - D5 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_3) /* PE10 - D40 */ +#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2) /* PE13 - D3 */ +#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_3) /* PE12 - D39 */ +#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2) /* PE14 - D38 */ + +/* TIM2 - General Purpose 32-bit Timer (4 channels) */ +#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2) /* PA15 */ +#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1) /* PB3 */ +#define GPIO_TIM2_CH3IN (GPIO_TIM2_CH3IN_1) /* PB10 */ +#define GPIO_TIM2_CH4IN (GPIO_TIM2_CH4IN_1) /* PB11 */ + +/* TIM3 - General Purpose 16-bit Timer (4 channels) */ +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_1) /* PA6 */ +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_1) /* PA7 */ +#define GPIO_TIM3_CH3IN (GPIO_TIM3_CH3IN_1) /* PB0 */ +#define GPIO_TIM3_CH4IN (GPIO_TIM3_CH4IN_1) /* PB1 */ + +/* TIM4 - General Purpose 16-bit Timer (4 channels) */ +#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2) /* PD12 */ +#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2) /* PD13 */ +#define GPIO_TIM4_CH3IN (GPIO_TIM4_CH3IN_2) /* PD14 */ +#define GPIO_TIM4_CH4IN (GPIO_TIM4_CH4IN_2) /* PD15 */ + +/* TIM5 - General Purpose 32-bit Timer (4 channels) */ +#define GPIO_TIM5_CH1IN (GPIO_TIM5_CH1IN_2) +#define GPIO_TIM5_CH2IN (GPIO_TIM5_CH2IN_2) +#define GPIO_TIM5_CH3IN (GPIO_TIM5_CH3IN_2) +#define GPIO_TIM5_CH4IN (GPIO_TIM5_CH4IN_2) + +/* TIM6 - Basic 16-bit Timer (0 channels) */ + +/* TIM7 - Basic 16-bit Timer (0 channels) */ + +/* TIM8 - Advanced 16-bit Timer (4 channels) */ +#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1) +#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1) +#define GPIO_TIM8_CH3IN (GPIO_TIM8_CH3IN_1) +#define GPIO_TIM8_CH4IN (GPIO_TIM8_CH4IN_1) + +/* TIM12 - General purpose 16-bit Timer (2 channels) */ +#define GPIO_TIM12_CH1IN (GPIO_TIM12_CH1IN_1) +#define GPIO_TIM12_CH2IN (GPIO_TIM12_CH2IN_1) + +/* TIM13 - General purpose 16-bit Timer (1 channels) */ +#define GPIO_TIM13_CH1IN (GPIO_TIM13_CH1IN_1) + +/* TIM14 - General purpose 16-bit Timer (1 channels) */ +#define GPIO_TIM14_CH1IN (GPIO_TIM14_CH1IN_1) + +/* TIM15 - General purpose 16-bit Timer (2 channels) */ +#define GPIO_TIM15_CH1IN (GPIO_TIM15_CH1IN_1) +#define GPIO_TIM15_CH2IN (GPIO_TIM15_CH2IN_1) + +/* TIM16 - General purpose 16-bit Timer (1 channels) */ +#define GPIO_TIM16_CH1IN (GPIO_TIM16_CH1IN_1) + +/* TIM17 - General purpose 16-bit Timer (1 channels) */ +#define GPIO_TIM17_CH1IN (GPIO_TIM17_CH1IN_1) + +/* OTGHS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0 | GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0 | GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0 | GPIO_SPEED_100MHz) + +#define GPIO_OTGHS_DM GPIO_OTGFS_DM +#define GPIO_OTGHS_DP GPIO_OTGFS_DP +#define GPIO_OTGHS_ID GPIO_OTGFS_ID + +/* DMA **********************************************************************/ + +#define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_0 /* DMA1 */ +#define DMAMAP_SPI3_TX DMAMAP_DMA12_SPI3TX_0 /* DMA1 */ + +#define DMAMAP_USART6_RX DMAMAP_DMA12_USART6RX_1 +#define DMAMAP_USART6_TX DMAMAP_DMA12_USART6TX_0 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/kernel/Makefile b/boards/arm/stm32h7/nucleo-h723zg/kernel/Makefile new file mode 100644 index 00000000000..19132edcb5a --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/kernel/Makefile @@ -0,0 +1,94 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h723zg/kernel/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)memory.ld) +USER_LDSCRIPT += -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = stm32_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec nuttx_user.elf $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) nuttx_user.elf >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size nuttx_user.elf + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/arm/stm32h7/nucleo-h723zg/kernel/stm32_userspace.c b/boards/arm/stm32h7/nucleo-h723zg/kernel/stm32_userspace.c new file mode 100644 index 00000000000..efeccb94388 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/kernel/stm32_userspace.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/kernel/stm32_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +#if CONFIG_NUTTX_USERSPACE != 0x08020000 +# error "CONFIG_NUTTX_USERSPACE must be 0x08020000 to match memory.ld" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + /* Memory manager heap structure */ + + .us_heap = &g_mmheap, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/scripts/Make.defs b/boards/arm/stm32h7/nucleo-h723zg/scripts/Make.defs new file mode 100644 index 00000000000..ca1ed34e8c1 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/scripts/Make.defs @@ -0,0 +1,50 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h723zg/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_APP_FORMAT_MCUBOOT),y) + ifeq ($(CONFIG_MCUBOOT_BOOTLOADER),y) + LDSCRIPT = flash-mcuboot-loader.ld + else + LDSCRIPT = flash-mcuboot-app.ld + endif +else + LDSCRIPT = flash.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-app.ld b/boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-app.ld new file mode 100644 index 00000000000..4c2299e01a4 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-app.ld @@ -0,0 +1,199 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-app.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32H723ZG has 1024Kb of main FLASH memory. The flash memory is + * partitioned into a User Flash memory and a System Flash memory. Each + * of these memories has single bank only: + * + * 1) User Flash memory: + * + * Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each + * + * 2) System Flash memory: + * + * Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 64Kb sector + * + * 3) User option bytes for user configuration, only in Bank 1. + * + * In the STM32H723ZG, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash memory at 0x0800:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x1FF0:0000 + * + * TODO: Check next paragraph with nucleo schematics + * + * NuttX does not modify these option bytes. On the unmodified NUCLEO-H723ZG + * board, the BOOT0 pin is at ground so by default, the STM32 will boot + * to address 0x0800:0000 in FLASH. + * + * The STM32H723ZG also has 564Kb of data SRAM. + * SRAM is split up into several blocks and into three power domains: + * + * 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with + * 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus + * + * 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000 + * + * The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit + * DTCM ports. The DTCM-RAM could be used for critical real-time + * data, such as interrupt service routines or stack / heap memory. + * Both DTCM-RAMs can be used in parallel (for load/store operations) + * thanks to the Cortex-M7 dual issue capability. + * + * 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000 + * + * This RAM is connected to ITCM 64-bit interface designed for + * execution of critical real-times routines by the CPU. + * + * 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA + * through D1 domain AXI bus matrix + * + * 2.1) 320Kb of SRAM beginning at address 0x2400:0000 + * + * 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA + * through D2 domain AHB bus matrix + * + * 3.1) 16Kb of SRAM1 beginning at address 0x3000:0000 + * 3.2) 16Kb of SRAM2 beginning at address 0x3000:4000 + * + * SRAM1 and SRAM2 are one contiguous block: 32Kb at address 0x3000:0000 + * + * 4) AHB SRAM (D3 domain) accessible by most of system masters + * through D3 domain AHB bus matrix + * + * 4.1) 16Kb of SRAM4 beginning at address 0x3800:0000 + * 4.1) 4Kb of backup RAM beginning at address 0x3880:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + flash (rx) : ORIGIN = 0x08040200, LENGTH = 768K - 256K + dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x24000000, LENGTH = 320K + sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 16K + sram2 (rwx) : ORIGIN = 0x30004000, LENGTH = 16K + sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 16K + bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Emit the the D3 power domain section for locating BDMA data + * + * Static data with locate_data(".sram4") will be located + * at start of SRAM4; the rest of SRAM4 will be added to the heap. + */ + + .sram4_reserve (NOLOAD) : + { + *(.sram4) + . = ALIGN(4); + _sram4_heap_start = ABSOLUTE(.); + } > sram4 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-loader.ld b/boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-loader.ld new file mode 100644 index 00000000000..6a3d98a9866 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-loader.ld @@ -0,0 +1,199 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/scripts/flash-mcuboot-laoder.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32H723ZG has 1024Kb of main FLASH memory. The flash memory is + * partitioned into a User Flash memory and a System Flash memory. Each + * of these memories has single bank only: + * + * 1) User Flash memory: + * + * Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each + * + * 2) System Flash memory: + * + * Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 64Kb sector + * + * 3) User option bytes for user configuration, only in Bank 1. + * + * In the STM32H723ZG, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash memory at 0x0800:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x1FF0:0000 + * + * TODO: Check next paragraph with nucleo schematics + * + * NuttX does not modify these option bytes. On the unmodified NUCLEO-H723ZG + * board, the BOOT0 pin is at ground so by default, the STM32 will boot + * to address 0x0800:0000 in FLASH. + * + * The STM32H723ZG also has 564Kb of data SRAM. + * SRAM is split up into several blocks and into three power domains: + * + * 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with + * 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus + * + * 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000 + * + * The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit + * DTCM ports. The DTCM-RAM could be used for critical real-time + * data, such as interrupt service routines or stack / heap memory. + * Both DTCM-RAMs can be used in parallel (for load/store operations) + * thanks to the Cortex-M7 dual issue capability. + * + * 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000 + * + * This RAM is connected to ITCM 64-bit interface designed for + * execution of critical real-times routines by the CPU. + * + * 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA + * through D1 domain AXI bus matrix + * + * 2.1) 320Kb of SRAM beginning at address 0x2400:0000 + * + * 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA + * through D2 domain AHB bus matrix + * + * 3.1) 16Kb of SRAM1 beginning at address 0x3000:0000 + * 3.2) 16Kb of SRAM2 beginning at address 0x3000:4000 + * + * SRAM1 and SRAM2 are one contiguous block: 32Kb at address 0x3000:0000 + * + * 4) AHB SRAM (D3 domain) accessible by most of system masters + * through D3 domain AHB bus matrix + * + * 4.1) 16Kb of SRAM4 beginning at address 0x3800:0000 + * 4.1) 4Kb of backup RAM beginning at address 0x3880:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K + dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x24000000, LENGTH = 320K + sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 16K + sram2 (rwx) : ORIGIN = 0x30004000, LENGTH = 16K + sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 16K + bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Emit the the D3 power domain section for locating BDMA data + * + * Static data with locate_data(".sram4") will be located + * at start of SRAM4; the rest of SRAM4 will be added to the heap. + */ + + .sram4_reserve (NOLOAD) : + { + *(.sram4) + . = ALIGN(4); + _sram4_heap_start = ABSOLUTE(.); + } > sram4 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/scripts/flash.ld b/boards/arm/stm32h7/nucleo-h723zg/scripts/flash.ld new file mode 100644 index 00000000000..e59ce91703f --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/scripts/flash.ld @@ -0,0 +1,199 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/scripts/flash.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32H723ZG has 1024Kb of main FLASH memory. The flash memory is + * partitioned into a User Flash memory and a System Flash memory. Each + * of these memories has single bank only: + * + * 1) User Flash memory: + * + * Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each + * + * 2) System Flash memory: + * + * Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 64Kb sector + * + * 3) User option bytes for user configuration, only in Bank 1. + * + * In the STM32H723ZG, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash memory at 0x0800:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x1FF0:0000 + * + * TODO: Check next paragraph with nucleo schematics + * + * NuttX does not modify these option bytes. On the unmodified NUCLEO-H723ZG + * board, the BOOT0 pin is at ground so by default, the STM32 will boot + * to address 0x0800:0000 in FLASH. + * + * The STM32H723ZG also has 564Kb of data SRAM. + * SRAM is split up into several blocks and into three power domains: + * + * 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with + * 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus + * + * 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000 + * + * The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit + * DTCM ports. The DTCM-RAM could be used for critical real-time + * data, such as interrupt service routines or stack / heap memory. + * Both DTCM-RAMs can be used in parallel (for load/store operations) + * thanks to the Cortex-M7 dual issue capability. + * + * 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000 + * + * This RAM is connected to ITCM 64-bit interface designed for + * execution of critical real-times routines by the CPU. + * + * 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA + * through D1 domain AXI bus matrix + * + * 2.1) 320Kb of SRAM beginning at address 0x2400:0000 + * + * 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA + * through D2 domain AHB bus matrix + * + * 3.1) 16Kb of SRAM1 beginning at address 0x3000:0000 + * 3.2) 16Kb of SRAM2 beginning at address 0x3000:4000 + * + * SRAM1 and SRAM2 are one contiguous block: 32Kb at address 0x3000:0000 + * + * 4) AHB SRAM (D3 domain) accessible by most of system masters + * through D3 domain AHB bus matrix + * + * 4.1) 16Kb of SRAM4 beginning at address 0x3800:0000 + * 4.1) 4Kb of backup RAM beginning at address 0x3880:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY /* TODO: define according to spec */ +{ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x24000000, LENGTH = 320K + sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 16K + sram2 (rwx) : ORIGIN = 0x30004000, LENGTH = 16K + sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 16K + bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Emit the the D3 power domain section for locating BDMA data + * + * Static data with locate_data(".sram4") will be located + * at start of SRAM4; the rest of SRAM4 will be added to the heap. + */ + + .sram4_reserve (NOLOAD) : + { + *(.sram4) + . = ALIGN(4); + _sram4_heap_start = ABSOLUTE(.); + } > sram4 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/scripts/kernel.space.ld b/boards/arm/stm32h7/nucleo-h723zg/scripts/kernel.space.ld new file mode 100644 index 00000000000..8a5c1775847 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/scripts/kernel.space.ld @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/scripts/kernel.space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > ksram + + /* Emit the the D3 power domain section for locating BDMA data + * + * Static data with locate_data(".sram4") will be located + * at start of SRAM4; the rest of SRAM4 will be added to the heap. + */ + + .sram4_reserve (NOLOAD) : + { + *(.sram4) + . = ALIGN(4); + _sram4_heap_start = ABSOLUTE(.); + } > sram4 + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/scripts/memory.ld b/boards/arm/stm32h7/nucleo-h723zg/scripts/memory.ld new file mode 100644 index 00000000000..1b7ae4f26b7 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/scripts/memory.ld @@ -0,0 +1,54 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/scripts/memory.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* TODO: Add description for memory organisation */ + +MEMORY +{ + /* ITCM boot address */ + + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 32Kb SRAM123 */ + + ksram (rwx) : ORIGIN = 0x30000000, LENGTH = 16K + usram (rwx) : ORIGIN = 0x30004000, LENGTH = 16K + xsram (rwx) : ORIGIN = 0x30008000, LENGTH = 288K - 32K + + /* 320Kb of contiguous AXI SRAM */ + + sram (rwx) : ORIGIN = 0x24000000, LENGTH = 320K + + /* DTCM SRAM */ + + dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K + + sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 16K + bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/scripts/user-space.ld b/boards/arm/stm32h7/nucleo-h723zg/scripts/user-space.ld new file mode 100644 index 00000000000..6071d0c8ccb --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/scripts/user-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/scripts/user-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt new file mode 100644 index 00000000000..fbb68cf142c --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt @@ -0,0 +1,88 @@ +# ############################################################################## +# boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_ARCH_BUTTONS) + list(APPEND SRCS stm32_buttons.c) +endif() + +if(CONFIG_STM32H7_SPI) + list(APPEND SRCS stm32_spi.c) +endif() + +if(CONFIG_STM32H7_OTGHS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_BOARDCTL_UNIQUEID) + list(APPEND SRCS stm32_uid.c) +endif() + +if(CONFIG_BOARDCTL) + list(APPEND SRCS stm32_appinitialize.c) +endif() + +if(CONFIG_DEV_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS stm32_reset.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_STM32_APP_FORMAT_MCUBOOT) + if(CONFIG_MCUBOOT_BOOTLOADER) + set_property( + GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/flash-mcuboot-loader.ld") + else() + set_property( + GLOBAL PROPERTY LD_SCRIPT + "${NUTTX_BOARD_DIR}/scripts/flash-mcuboot-app.ld") + endif() +else() + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") +endif() + +if(NOT CONFIG_BUILD_FLAT) + add_subdirectory(${NUTTX_BOARD_DIR}/kernel) + set_property( + GLOBAL PROPERTY LD_SCRIPT_USER ${NUTTX_BOARD_DIR}/scripts/memory.ld + ${NUTTX_BOARD_DIR}/scripts/user-space.ld) +endif() diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile new file mode 100644 index 00000000000..06395d868cf --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile @@ -0,0 +1,69 @@ +############################################################################ +# boards/arm/stm32h7/nucleo-h723zg/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_STM32H7_SPI),y) +CSRCS += stm32_spi.c +endif + +ifeq ($(CONFIG_STM32H7_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) +CSRCS += stm32_uid.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += stm32_appinitialize.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += stm32_reset.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h new file mode 100644 index 00000000000..04f3a47cb27 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h @@ -0,0 +1,260 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H +#define __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PROC 1 +#define HAVE_USBDEV 1 +#define HAVE_USBMONITOR 1 +#define HAVE_MTDCONFIG 1 +#define HAVE_PROGMEM_CHARDEV 1 + +/* Can't support USB host or device features if USB OTG HS is not enabled */ + +#ifndef CONFIG_STM32H7_OTGHS +# undef HAVE_USBDEV +#endif + +/* Can't support USB device if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#ifndef CONFIG_USBMONITOR +# undef HAVE_USBMONITOR +#endif + +#ifndef HAVE_USBDEV +# undef CONFIG_USBDEV_TRACE +#endif + +#ifndef HAVE_USBHOST +# undef CONFIG_USBHOST_TRACE +#endif + +#if !defined(CONFIG_USBDEV_TRACE) && !defined(CONFIG_USBHOST_TRACE) +# undef HAVE_USBMONITOR +#endif + +#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +# undef HAVE_PROGMEM_CHARDEV +#endif + +/* This is the on-chip progmem memory driver minor number */ + +#define PROGMEM_MTD_MINOR 0 + +/* flash */ +#if defined(CONFIG_MMCSD) +# define FLASH_BASED_PARAMS +#endif + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define STM32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +/* Check if we can support the RTC driver */ + +#define HAVE_RTC_DRIVER 1 +#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER) +# undef HAVE_RTC_DRIVER +#endif + +/* LED + * + * The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Yellow LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. + */ + +#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0) +#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTE | GPIO_PIN1) +#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN14) + +#define GPIO_LED_GREEN GPIO_LD1 +#define GPIO_LED_YELLOW GPIO_LD2 +#define GPIO_LED_RED GPIO_LD3 + +#define LED_DRIVER_PATH "/dev/userleds" + +/* BUTTONS + * + * The Blue pushbutton B1, labeled "User", is connected to GPIO PC13. + * A high value will be sensed when the button is depressed. + * Note: + * 1) That the EXTI is included in the definition to enable an interrupt + * on this IO. + * 2) The following definitions assume the default Solder Bridges are + * installed. + */ + +#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13) + +/* USB OTG HS + * + * PA9 OTG_HS_VBUS VBUS sensing (also connected to the green LED) + * PG6 OTG_HS_PowerSwitchOn + * PG7 OTG_HS_Overcurrent + */ + +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) + +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10) + +#define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7) + +#define GPIO_OTGHS_VBUS GPIO_OTGFS_VBUS +#define GPIO_OTGHS_PWRON GPIO_OTGFS_PWRON +#define GPIO_OTGHS_OVER GPIO_OTGFS_OVER + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +/* Example, used free Ports on the board */ + +#define GPIO_IN1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN2) +#define GPIO_OUT1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN4) +#define GPIO_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN5) + +/* PWM */ + +#define NUCLEOH723ZG_PWMTIMER 1 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y && + * CONFIG_NSH_ARCHINIT: + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the + * Nucleo-H723ZG board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_SPI +void stm32_spidev_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO-Driver. + * + ****************************************************************************/ + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) +int stm32_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the NUCLEO-H723ZG board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_OTGHS +void weak_function stm32_usbinitialize(void); +#endif + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + +#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H723ZG_SRC_NUCLEO_H723ZG_H */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c new file mode 100644 index 00000000000..46324e83f31 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c @@ -0,0 +1,269 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "nucleo-h723zg.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ + defined(CONFIG_STM32H7_ADC3) + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 7 +#define ADC2_NCHANNELS 5 +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_ADC1 +/* Identifying number of each ADC channel: Variable Resistor. + * + * ADC1: {5, 10, 15, 18, 19, 7, 12}; + */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 5, 10, 15, 18, 19, 7, 12 +}; + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = + { + GPIO_ADC12_INP5, + GPIO_ADC123_INP10, + GPIO_ADC12_INP15, + GPIO_ADC12_INP18, + GPIO_ADC12_INP19, + GPIO_ADC123_INP7, + GPIO_ADC123_INP12 + }; + +#endif /* CONFIG_STM32H7_ADC1 */ + +/**************************************************************************** + * ADC2 + ****************************************************************************/ +#ifdef CONFIG_STM32H7_ADC2 + +static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = +{ + 2, 3, 14, 4, 8 +}; + +static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = +{ + GPIO_ADC2_INP2, + GPIO_ADC12_INP3, + GPIO_ADC12_INP14, + GPIO_ADC12_INP4, + GPIO_ADC12_INP8 +}; +#endif /* CONFIG_STM32H7_ADC2 */ + +#ifdef CONFIG_STM32H7_ADC3 +/* Identifying number of each ADC channel: Variable Resistor. + * + * ADC3: {6,}; + */ + +static const uint8_t g_adc3_chanlist[ADC1_NCHANNELS] = +{ + 11 +}; + +/* Configurations of pins used by each ADC channels + * + * + * ADC3: {GPIO_ADC3_INP6} + */ + +static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC123_INP11, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ +#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + char devname[] = "/dev/adc0"; + + /* Check if we have already initialized */ + + if (!initialized) + { +#endif +#if defined(CONFIG_STM32H7_ADC1) + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + if (g_adc1_pinlist[i] != 0) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC1 interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register(devname, adc); + if (ret < 0) + { + aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret); + return ret; + } + + devname[8]++; +#endif + +#ifdef CONFIG_STM32H7_ADC2 + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC2_NCHANNELS; i++) + { + if (g_adc2_pinlist[i] != 0) + { + stm32_configgpio(g_adc2_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC2 interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc[0-1]" */ + + ret = adc_register(devname, adc); + if (ret < 0) + { + aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret); + return ret; + } + + devname[8]++; +#endif + +#if defined(CONFIG_STM32H7_ADC3) + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC3_NCHANNELS; i++) + { + if (g_adc3_pinlist[i] != 0) + { + stm32_configgpio(g_adc3_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC3 interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc[0-2]" */ + + ret = adc_register(devname, adc); + if (ret < 0) + { + aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ + defined(CONFIG_STM32H7_ADC3) + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_appinitialize.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_appinitialize.c new file mode 100644 index 00000000000..c988b0079f4 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_appinitialize.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_appinitialize.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "nucleo-h723zg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return stm32_bringup(); +#endif +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_autoleds.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_autoleds.c new file mode 100644 index 00000000000..98e4d30f0a1 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_autoleds.c @@ -0,0 +1,171 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_autoleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-h723zg.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Indexed by BOARD_LED_ */ + +static const uint32_t g_ledmap[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_YELLOW, + GPIO_LED_RED, +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void phy_set_led(int led, bool state) +{ + /* Active High */ + + stm32_gpiowrite(g_ledmap[led], state); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LD1 GPIO for output. Initial state is OFF */ + + for (i = 0; i < nitems(g_ledmap); i++) + { + stm32_configgpio(g_ledmap[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + phy_set_led(BOARD_LED_YELLOW, true); + break; + + case LED_IRQSENABLED: + phy_set_led(BOARD_LED_YELLOW, false); + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_STACKCREATED: + phy_set_led(BOARD_LED_GREEN, true); + phy_set_led(BOARD_LED_YELLOW, true); + g_initialized = true; + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_YELLOW, true); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, true); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, true); + phy_set_led(BOARD_LED_YELLOW, true); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, true); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_INIRQ: + phy_set_led(BOARD_LED_YELLOW, false); + break; + + case LED_SIGNAL: + phy_set_led(BOARD_LED_GREEN, false); + break; + + case LED_ASSERTION: + phy_set_led(BOARD_LED_RED, false); + phy_set_led(BOARD_LED_YELLOW, false); + break; + + case LED_PANIC: + phy_set_led(BOARD_LED_RED, false); + break; + + case LED_IDLE : /* IDLE */ + phy_set_led(BOARD_LED_RED, false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c new file mode 100644 index 00000000000..a89f8e64f50 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_start.h" +#include "nucleo-h723zg.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) + /* Initialize USB */ + + stm32_usbinitialize(); +#endif + +#ifdef CONFIG_STM32H7_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c new file mode 100644 index 00000000000..d049bc43f3b --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c @@ -0,0 +1,504 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_CDCACM +# include +#endif + +#include "nucleo-h723zg.h" + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) +# include +#endif + +#ifdef HAVE_RTC_DRIVER +# include +# include "stm32_rtc.h" +#endif + +#ifdef CONFIG_STM32_ROMFS +# include "stm32_romfs.h" +#endif + +#ifdef CONFIG_CAPTURE +# include +# include "stm32_capture.h" +#endif + +#ifdef CONFIG_STM32H7_IWDG +# include "stm32_wdg.h" +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#include "stm32_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_capture_setup + * + * Description: + * Initialize and register capture drivers. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_CAPTURE +static int stm32_capture_setup(void) +{ + int ret; + struct cap_lowerhalf_s *lower[] = + { +#if defined(CONFIG_STM32H7_TIM1_CAP) + stm32_cap_initialize(1), +#endif +#if defined(CONFIG_STM32H7_TIM2_CAP) + stm32_cap_initialize(2), +#endif +#if defined(CONFIG_STM32H7_TIM3_CAP) + stm32_cap_initialize(3), +#endif +#if defined(CONFIG_STM32H7_TIM4_CAP) + stm32_cap_initialize(4), +#endif +#if defined(CONFIG_STM32H7_TIM5_CAP) + stm32_cap_initialize(5), +#endif +#if defined(CONFIG_STM32H7_TIM8_CAP) + stm32_cap_initialize(8), +#endif +#if defined(CONFIG_STM32H7_TIM12_CAP) + stm32_cap_initialize(12), +#endif +#if defined(CONFIG_STM32H7_TIM13_CAP) + stm32_cap_initialize(13), +#endif +#if defined(CONFIG_STM32H7_TIM14_CAP) + stm32_cap_initialize(14), +#endif +#if defined(CONFIG_STM32H7_TIM15_CAP) + stm32_cap_initialize(15), +#endif +#if defined(CONFIG_STM32H7_TIM16_CAP) + stm32_cap_initialize(16), +#endif +#if defined(CONFIG_STM32H7_TIM17_CAP) + stm32_cap_initialize(17), +#endif + /* TODO: LPTIMy_CAP */ + }; + + size_t count = sizeof(lower) / sizeof(lower[0]); + + /* Nothing to do if no timers enabled */ + + if (count == 0) + { + return OK; + } + + /* This will register “/dev/cap0” ... “/dev/cap” */ + + ret = cap_register_multiple("/dev/cap", lower, count); + if (ret == EINVAL) + { + syslog(LOG_ERR, + "ERROR: cap_register_multiple path is invalid\n"); + } + else if (ret == EEXIST) + { + syslog(LOG_ERR, "ERROR: cap_register_multiple an inode " + "already exists at this path\n"); + } + else if (ret == ENOMEM) + { + syslog(LOG_ERR, "ERROR: cap_register_multiple not enough " + "memory to register capture drivers\n"); + } + else if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: cap_register_multiple failed: %d\n", + ret); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32H7_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32H7_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32H7_I2C3 + stm32_i2c_register(3); +#endif +#ifdef CONFIG_STM32H7_I2C4 + stm32_i2c_register(4); +#endif +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y && + * CONFIG_NSH_ARCHINIT: + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; +#ifdef HAVE_RTC_DRIVER + struct rtc_lowerhalf_s *lower; +#endif + + UNUSED(ret); + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_STM32_ROMFS + /* Mount the romfs partition */ + + ret = stm32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifdef HAVE_RTC_DRIVER + /* Instantiate the STM32 lower-half RTC driver */ + + lower = stm32_rtc_lowerhalf(); + if (!lower) + { + syslog(LOG_ERR, + "ERROR: Failed to instantiate the RTC lower-half driver\n"); + return -ENOMEM; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to bind/register the RTC driver: %d\n", ret); + return ret; + } + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif /* CONFIG_INPUT_BUTTONS */ + +#if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) + /* Register the USERLED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif /* CONFIG_USERLED */ + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() + * starts a thread will monitor for USB connection and + * disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize USB host: %d\n", + ret); + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to start USB monitor: %d\n", + ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif /* CONFIG_ADC */ + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_SENSORS_LSM6DSL + ret = stm32_lsm6dsl_initialize("/dev/lsm6dsl0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize LSM6DSL driver: %d\n", + ret); + } +#endif /* CONFIG_SENSORS_LSM6DSL */ + +#ifdef CONFIG_SENSORS_LSM9DS1 + ret = stm32_lsm9ds1_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize LSM9DS1 driver: %d\n", + ret); + } +#endif /* CONFIG_SENSORS_LSM6DSL */ + +#ifdef CONFIG_SENSORS_LSM303AGR + ret = stm32_lsm303agr_initialize("/dev/lsm303mag0"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize LSM303AGR driver: %d\n", + ret); + } +#endif /* CONFIG_SENSORS_LSM303AGR */ + +#ifdef CONFIG_PCA9635PW + /* Initialize the PCA9635 chip */ + + ret = stm32_pca9635_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pca9635_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_WL_NRF24L01 + ret = stm32_wlinitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", + ret); + } +#endif /* CONFIG_WL_NRF24L01 */ + +#if defined(CONFIG_CDCACM) && !defined(CONFIG_CDCACM_CONSOLE) && \ + !defined(CONFIG_CDCACM_COMPOSITE) + /* Initialize CDCACM */ + + syslog(LOG_INFO, "Initialize CDCACM device\n"); + + ret = cdcacm_initialize(0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: cdcacm_initialize failed: %d\n", ret); + } +#endif /* CONFIG_CDCACM & !CONFIG_CDCACM_CONSOLE */ + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#ifdef CONFIG_MMCSD_SPI + /* Initialize the MMC/SD SPI driver (SPI3 is used) */ + + ret = stm32_mmcsd_initialize(CONFIG_NSH_MMCSDMINOR); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", + CONFIG_NSH_MMCSDMINOR, ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAPTURE + /* Initialize the capture driver */ + + ret = stm32_capture_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_capture_setup() failed: %d\\n", ret); + } +#endif + +#ifdef CONFIG_MTD +#ifdef HAVE_PROGMEM_CHARDEV + ret = stm32_progmem_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize MTD progmem: %d\n", ret); + } +#endif /* HAVE_PROGMEM_CHARDEV */ +#endif /* CONFIG_MTD */ + +#ifdef CONFIG_STM32H7_IWDG + /* Initialize the watchdog timer */ + + stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); +#endif + + return OK; +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_buttons.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_buttons.c new file mode 100644 index 00000000000..fa5e6051aaf --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_buttons.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_buttons.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-h723zg.h" +#include + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + stm32_configgpio(GPIO_BTN_USER); + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + if (id == BUTTON_USER) + { + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, + irqhandler, arg); + } + + return ret; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_gpio.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_gpio.c new file mode 100644 index 00000000000..a190e6d563d --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_gpio.c @@ -0,0 +1,323 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "nucleo-h723zg.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpin_read(struct gpio_dev_s *dev, bool *value); +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} + +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} + +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c new file mode 100644 index 00000000000..0b7126a5616 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-h723zg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32H7_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32H7_TIM1_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOH723ZG_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c new file mode 100644 index 00000000000..63b6ff97c86 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_reset.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c new file mode 100644 index 00000000000..9dd4e75b1e9 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c @@ -0,0 +1,258 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-h723zg.h" +#include + +#ifdef CONFIG_STM32H7_SPI + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32H7_SPI3 + spiinfo("Configure GPIO for SPI3/CS\n"); +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32H7_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32H7_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + switch (devid) + { + default: + break; + } +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + switch (devid) + { + default: + break; + } + + return status; +} +#endif + +#ifdef CONFIG_STM32H7_SPI4 +void stm32_spi4select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32H7_SPI5 +void stm32_spi5select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32H7_SPI6 +void stm32_spi6select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32H7_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32H7_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32H7_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32H7_SPI4 +int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32H7_SPI5 +int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32H7_SPI6 +int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ +#endif /* CONFIG_STM32H7_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_uid.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_uid.c new file mode 100644 index 00000000000..4c43237e9aa --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_uid.c @@ -0,0 +1,69 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_uid.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. + * SPDX-FileContributor: Marawan Ragab + * SPDX-FileContributor: David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include "stm32_uid.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + stm32_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c new file mode 100644 index 00000000000..2c6fadbf2ef --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "nucleo-h723zg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBHOST) +# error "USB host mode is not supported" +#endif +#if defined(CONFIG_USBDEV) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the nucleo-144 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG HS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG HS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32H7_OTGHS + stm32_configgpio(GPIO_OTGHS_VBUS); + stm32_configgpio(GPIO_OTGHS_PWRON); + stm32_configgpio(GPIO_OTGHS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usbmsc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usbmsc.c new file mode 100644 index 00000000000..8ad08805e1b --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usbmsc.c @@ -0,0 +1,61 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_usbmsc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + stm32_mmcsd_initialize(0); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_userleds.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_userleds.c new file mode 100644 index 00000000000..877bd2bf992 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_userleds.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h723zg/src/stm32_userleds.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "nucleo-h723zg.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration and is indexed by + * BOARD_LED_ + */ + +static const uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_GREEN, + GPIO_LED_YELLOW, + GPIO_LED_RED, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_configgpio(g_ledcfg[i]); + } + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_ledcfg)) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_ledcfg); i++) + { + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */