diff --git a/arch/arm/src/common/up_initialize.c b/arch/arm/src/common/up_initialize.c index 82669eace87..87012c1c60f 100644 --- a/arch/arm/src/common/up_initialize.c +++ b/arch/arm/src/common/up_initialize.c @@ -258,9 +258,11 @@ void up_initialize(void) (void)telnet_initialize(); #endif +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) /* Initialize USB -- device and/or host */ up_usbinitialize(); +#endif /* Initialize the L2 cache if present and selected */ diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index fd0dc4a3041..6a609a813eb 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -95,6 +95,7 @@ config ARCH_CHIP_STM32F723RE config ARCH_CHIP_STM32F723VC bool "STM32F723VC" select STM32F7_STM32F723XX + select STM32F7_HAVE_INTERNAL_ULPI select STM32F7_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- @@ -103,6 +104,7 @@ config ARCH_CHIP_STM32F723VC config ARCH_CHIP_STM32F723VE bool "STM32F723VE" select STM32F7_STM32F723XX + select STM32F7_HAVE_INTERNAL_ULPI select STM32F7_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- @@ -111,6 +113,7 @@ config ARCH_CHIP_STM32F723VE config ARCH_CHIP_STM32F723ZC bool "STM32F723ZC" select STM32F7_STM32F723XX + select STM32F7_HAVE_INTERNAL_ULPI select STM32F7_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- @@ -119,6 +122,7 @@ config ARCH_CHIP_STM32F723ZC config ARCH_CHIP_STM32F723ZE bool "STM32F723ZE" select STM32F7_STM32F723XX + select STM32F7_HAVE_INTERNAL_ULPI select STM32F7_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- @@ -127,6 +131,7 @@ config ARCH_CHIP_STM32F723ZE config ARCH_CHIP_STM32F723IC bool "STM32F723IC" select STM32F7_STM32F723XX + select STM32F7_HAVE_INTERNAL_ULPI select STM32F7_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- @@ -135,6 +140,7 @@ config ARCH_CHIP_STM32F723IC config ARCH_CHIP_STM32F723IE bool "STM32F723IE" select STM32F7_STM32F723XX + select STM32F7_HAVE_INTERNAL_ULPI select STM32F7_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- @@ -666,6 +672,7 @@ config STM32F7_STM32F722XX select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) select STM32F7_HAVE_CRYP select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32F7_HAVE_EXTERNAL_ULPI config STM32F7_STM32F723XX bool @@ -724,6 +731,7 @@ config STM32F7_STM32F746XX select STM32F7_HAVE_DMA2D select STM32F7_HAVE_CAN2 select STM32F7_HAVE_SPI4 + select STM32F7_HAVE_EXTERNAL_ULPI config STM32F7_STM32F756XX bool @@ -1199,6 +1207,14 @@ config STM32F7_HAVE_DFSDM1 bool default n +config STM32F7_HAVE_INTERNAL_ULPI + bool + default n + +config STM32F7_HAVE_EXTERNAL_ULPI + bool + default n + # These "hidden" settings are the OR of individual peripheral selections # indicating that the general capability is required. @@ -1427,8 +1443,8 @@ config STM32F7_OTGFS default n select USBHOST_HAVE_ASYNCH if USBHOST -config STM32F7_OTGHS - bool "OTG HS" +config STM32F7_OTGFSHS + bool "OTG FS/HS" default n select USBHOST_HAVE_ASYNCH if USBHOST @@ -1953,6 +1969,36 @@ endif endmenu # U[S]ART Configuration +menu "STM32F7_OTG_HS Configuration" + depends on STM32F7_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32F7_NO_ULPI + +config STM32F7_NO_ULPI + bool "No External ULPI" + default y + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32F7_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32F7_HAVE_EXTERNAL_ULPI + default n + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32F7_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32F7_HAVE_INTERNAL_ULPI + default y + ---help--- + Select to enable the internal ULPI for USB HS +endchoice #"ULPI Selection" + +endmenu # OTG_HS Config + menu "QuadSPI Configuration" depends on STM32F7_QUADSPI @@ -2103,7 +2149,7 @@ config STM32F7_SPI_DMA default n ---help--- Use DMA to improve SPI transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - + config STM32F7_SPI1_DMA bool "SPI1 DMA" default n diff --git a/arch/arm/src/stm32f7/chip/stm32_otg.h b/arch/arm/src/stm32f7/chip/stm32_otg.h index b69ef1a9ddc..5834cfb4fea 100644 --- a/arch/arm/src/stm32f7/chip/stm32_otg.h +++ b/arch/arm/src/stm32f7/chip/stm32_otg.h @@ -149,6 +149,11 @@ #define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) #define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +/* USB PHY OFFSET */ + +#define STM32_USBPHYC_PLL1_OFFSET 0x0000 /* USBPHYC PLL1 control register */ +#define STM32_USBPHYC_TUNE_OFFSET 0x000c /* USBPHYC tuning control register */ +#define STM32_USBPHYC_LDO_OFFSET 0x0018 /* USBPHYC LDO control and status register */ /* Register Addresses *******************************************************************************/ @@ -231,6 +236,11 @@ #define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n)) #define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n)) +/* USB PHY Registers */ + +#define STM32_USBPHYC_PLL1 (STM32_USBPHYC_BASE+STM32_USBPHYC_PLL1_OFFSET) +#define STM32_USBPHYC_TUNE (STM32_USBPHYC_BASE+STM32_USBPHYC_TUNE_OFFSET) +#define STM32_USBPHYC_LDO (STM32_USBPHYC_BASE+STM32_USBPHYC_LDO_OFFSET) /* Register Bitfield Definitions ********************************************************************/ /* Core global control and status registers */ @@ -250,56 +260,68 @@ #define OTG_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ #define OTG_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ #define OTG_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */ - /* Bits 13-15: Reserved, must be kept at reset value */ + /* Bits 13-15: Reserved, must be kept at reset value */ #define OTG_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ #define OTG_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ #define OTG_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ #define OTG_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ #define OTG_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */ - /* Bits 21-31: Reserved, must be kept at reset value */ + /* Bits 21-31: Reserved, must be kept at reset value */ /* Interrupt register */ - /* Bits 1:0 Reserved, must be kept at reset value */ + /* Bits 1:0 Reserved, must be kept at reset value */ #define OTG_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ - /* Bits 3-7: Reserved, must be kept at reset value */ + /* Bits 3-7: Reserved, must be kept at reset value */ #define OTG_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ #define OTG_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ - /* Bits 16:10 Reserved, must be kept at reset value */ + /* Bits 16:10 Reserved, must be kept at reset value */ #define OTG_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ #define OTG_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ #define OTG_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ #define OTG_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */ - /* Bits 21-31: Reserved, must be kept at reset value */ + /* Bits 21-31: Reserved, must be kept at reset value */ /* AHB configuration register */ #define OTG_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ - /* Bits 1-6: Reserved, must be kept at reset value */ + /* Bits 1-6: Reserved, must be kept at reset value */ #define OTG_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ #define OTG_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ - /* Bits 20-31: Reserved, must be kept at reset value */ + /* Bits 20-31: Reserved, must be kept at reset value */ /* USB configuration register */ #define OTG_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ #define OTG_GUSBCFG_TOCAL_MASK (7 << OTG_GUSBCFG_TOCAL_SHIFT) - /* Bits 3-5: Reserved, must be kept at reset value */ + /* Bits 3-5: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_ULPISEL (1 << 4) /* Bit 4: Select which high speed interface is to be used STM32F7x3 only*/ #define OTG_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ - /* Bit 7: Reserved, must be kept at reset value */ + /* Bit 7: Reserved, must be kept at reset value */ #define OTG_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ #define OTG_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ #define OTG_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ #define OTG_GUSBCFG_TRDT_MASK (15 << OTG_GUSBCFG_TRDT_SHIFT) # define OTG_GUSBCFG_TRDT(n) ((n) << OTG_GUSBCFG_TRDT_SHIFT) - /* Bits 14-28: Reserved, must be kept at reset value */ + /* Bit 14: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_PHYLPC (1 << 15) /* Bit 15: PHY Low-power clock select for USB OTG HS */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_ULPIFSLS (1 << 17) /* Bit 17: ULPI FS/LS select for USB OTG HS */ +#define OTG_GUSBCFG_ULPIAR (1 << 18) /* Bit 18: ULPI Auto-resume for USB OTG HS */ +#define OTG_GUSBCFG_ULPICSM (1 << 19) /* Bit 19: ULPI clock SuspendM for USB OTG HS */ +#define OTG_GUSBCFG_ULPIEVBUSD (1 << 20) /* Bit 20: ULPI External VBUS Drive for USB OTG HS */ +#define OTG_GUSBCFG_ULPIEVBUSI (1 << 21) /* Bit 21: ULPI external VBUS indicator for USB OTG HS */ +#define OTG_GUSBCFG_TSDPS (1 << 22) /* Bit 22: TermSel DLine pulsing selection for USB OTG HS */ +#define OTG_GUSBCFG_PCCI (1 << 23) /* Bit 23: Indicator complement for USB OTG HS */ +#define OTG_GUSBCFG_PTCI (1 << 24) /* Bit 24: Indicator pass through for USB OTG HS */ +#define OTG_GUSBCFG_ULPIIPD (1 << 25) /* Bit 24: ULPI interface protect disable for USB OTG HS */ + /* Bit 26-28: Reserved, must be kept at reset value */ #define OTG_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ #define OTG_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ -#define OTG_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ - /* Bits 20-31: Reserved, must be kept at reset value */ + /* Bits 20-31: Reserved, must be kept at reset value */ /* Reset register */ #define OTG_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ #define OTG_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ #define OTG_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ - /* Bit 3 Reserved, must be kept at reset value */ + /* Bit 3 Reserved, must be kept at reset value */ #define OTG_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ #define OTG_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ #define OTG_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */ @@ -337,12 +359,15 @@ #define OTG_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ #define OTG_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */ #define OTG_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ -#define OTG_GINT_RES22 (1 << 22) /* Bits 22: Reserved, must be kept at reset value */ +#define OTG_GINT_RES22 (1 << 22) /* Bit 22: Reserved, must be kept at reset value */ +#define OTG_GINT_DATAFSUSP (1 << 22) /* Bit 22: Data fetch suspended for USB OTG HS */ +#define OTG_GINT_RES23 (1 << 23) /* Bit 23: Reserved, must be kept at reset value */ #define OTG_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */ #define OTG_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ #define OTG_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ #define OTG_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ #define OTG_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */ +#define OTG_GINT_RES27 (1 << 27) /* Bit 27: Reserved, must be kept at reset value */ #define OTG_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ #define OTG_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ #define OTG_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ @@ -388,7 +413,7 @@ # define OTG_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ #define OTG_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ #define OTG_GRXSTSD_FRMNUM_MASK (15 << OTG_GRXSTSD_FRMNUM_SHIFT) - /* Bits 25-31: Reserved, must be kept at reset value */ + /* Bits 25-31: Reserved, must be kept at reset value */ /* Receive FIFO size register */ #define OTG_GRXFSIZ_MASK (0xffff) @@ -431,13 +456,14 @@ # define OTG_HNPTXSTS_CHNUM_MASK (15 << OTG_HNPTXSTS_CHNUM_SHIFT) # define OTG_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ # define OTG_HNPTXSTS_EPNUM_MASK (15 << OTG_HNPTXSTS_EPNUM_SHIFT) - /* Bit 31 Reserved, must be kept at reset value */ + /* Bit 31 Reserved, must be kept at reset value */ /* General core configuration register */ - /* Bits 0-15: Reserved, must be kept at reset value */ + /* Bits 0-15: Reserved, must be kept at reset value */ #define OTG_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ - /* Bit 17 Reserved, must be kept at reset value */ + /* Bit 17 Reserved, must be kept at reset value */ #define OTG_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */ - /* Bits 22-31: Reserved, must be kept at reset value */ +#define OTG_GCCFG_PHYHSEN (1 << 23) /* Bit 21: NOT In datasheet but in STMCube.. */ + /* Bits 22-31: Reserved, must be kept at reset value */ /* Core ID register (32-bit product ID) */ /* Host periodic transmit FIFO size register */ @@ -465,7 +491,7 @@ # define OTG_HCFG_FSLSPCS_LS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ # define OTG_HCFG_FSLSPCS_LS6MHz (2 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ #define OTG_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ - /* Bits 31:3 Reserved, must be kept at reset value */ + /* Bits 31:3 Reserved, must be kept at reset value */ /* Host frame interval register */ #define OTG_HFIR_MASK (0xffff) @@ -514,7 +540,7 @@ #define OTG_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ #define OTG_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ #define OTG_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ - /* Bit 9: Reserved, must be kept at reset value */ + /* Bit 9: Reserved, must be kept at reset value */ #define OTG_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ #define OTG_HPRT_PLSTS_MASK (3 << OTG_HPRT_PLSTS_SHIFT) # define OTG_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ @@ -532,7 +558,7 @@ #define OTG_HPRT_PSPD_MASK (3 << OTG_HPRT_PSPD_SHIFT) # define OTG_HPRT_PSPD_FS (1 << OTG_HPRT_PSPD_SHIFT) /* Full speed */ # define OTG_HPRT_PSPD_LS (2 << OTG_HPRT_PSPD_SHIFT) /* Low speed */ - /* Bits 19-31: Reserved, must be kept at reset value */ + /* Bits 19-31: Reserved, must be kept at reset value */ /* Host channel-n characteristics register */ @@ -543,7 +569,7 @@ #define OTG_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ # define OTG_HCCHAR_EPDIR_OUT (0) # define OTG_HCCHAR_EPDIR_IN OTG_HCCHAR_EPDIR - /* Bit 16 Reserved, must be kept at reset value */ + /* Bit 16 Reserved, must be kept at reset value */ #define OTG_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ #define OTG_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ #define OTG_HCCHAR_EPTYP_MASK (3 << OTG_HCCHAR_EPTYP_SHIFT) @@ -563,7 +589,7 @@ #define OTG_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ #define OTG_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ - /* Bit 2: Reserved, must be kept at reset value */ + /* Bit 2: Reserved, must be kept at reset value */ #define OTG_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ #define OTG_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ #define OTG_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ @@ -572,7 +598,7 @@ #define OTG_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ #define OTG_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ #define OTG_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ - /* Bits 11-31 Reserved, must be kept at reset value */ + /* Bits 11-31 Reserved, must be kept at reset value */ /* Host channel-n interrupt register */ #define OTG_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ @@ -586,16 +612,18 @@ # define OTG_HCTSIZ_DPID_DATA1 (2 << OTG_HCTSIZ_DPID_SHIFT) # define OTG_HCTSIZ_DPID_MDATA (3 << OTG_HCTSIZ_DPID_SHIFT) /* Non-control */ # define OTG_HCTSIZ_PID_SETUP (3 << OTG_HCTSIZ_DPID_SHIFT) /* Control */ - /* Bit 31 Reserved, must be kept at reset value */ + /* Bit 31 Reserved, must be kept at reset value */ /* Device-mode control and status registers */ /* Device configuration register */ #define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ #define OTG_DCFG_DSPD_MASK (3 << OTG_DCFG_DSPD_SHIFT) +# define OTG_DCFG_DSPD_HS (0 << OTG_DCFG_DSPD_SHIFT) /* High Speed */ +# define OTG_DCFG_DSPD_FS_USING_HS (1 << OTG_DCFG_DSPD_SHIFT) /* Full speed using High Speed*/ # define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed */ #define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ - /* Bit 3: Reserved, must be kept at reset value */ + /* Bit 3: Reserved, must be kept at reset value */ #define OTG_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ #define OTG_DCFG_DAD_MASK (0x7f << OTG_DCFG_DAD_SHIFT) #define OTG_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ @@ -604,7 +632,7 @@ # define OTG_DCFG_PFIVL_85PCT (1 << OTG_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ # define OTG_DCFG_PFIVL_90PCT (2 << OTG_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ # define OTG_DCFG_PFIVL_95PCT (3 << OTG_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ - /* Bits 13-31 Reserved, must be kept at reset value */ + /* Bits 13-31 Reserved, must be kept at reset value */ /* Device control register */ #define OTG_TESTMODE_DISABLED (0) /* Test mode disabled */ @@ -631,42 +659,47 @@ #define OTG_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ #define OTG_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ #define OTG_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ - /* Bits 12-31: Reserved, must be kept at reset value */ + /* Bits 12-31: Reserved, must be kept at reset value */ /* Device status register */ #define OTG_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ #define OTG_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ #define OTG_DSTS_ENUMSPD_MASK (3 << OTG_DSTS_ENUMSPD_SHIFT) # define OTG_DSTS_ENUMSPD_FS (3 << OTG_DSTS_ENUMSPD_MASK) /* Full speed */ - /* Bits 4-7: Reserved, must be kept at reset value */ + /* Bits 4-7: Reserved, must be kept at reset value */ #define OTG_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ #define OTG_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ #define OTG_DSTS_SOFFN_MASK (0x3fff << OTG_DSTS_SOFFN_SHIFT) #define OTG_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ #define OTG_DSTS_SOFFN_EVEN 0 #define OTG_DSTS_SOFFN_ODD OTG_DSTS_SOFFN0 - /* Bits 22-31: Reserved, must be kept at reset value */ + /* Bits 22-31: Reserved, must be kept at reset value */ /* Device IN endpoint common interrupt mask register */ #define OTG_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ #define OTG_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DIEPMSK_AHBERRM (1 << 2) /* Bit 2: AHB error mask for USB OTG HS */ #define OTG_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ #define OTG_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ #define OTG_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ #define OTG_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ - /* Bits 7-31: Reserved, must be kept at reset value */ + /* Bit 7: Reserved, must be kept at reset value */ +#define OTG_DIEPMSK_TXFURM (1 << 8) /* Bit 8: FIFO underrun mask */ + /* Bits 9-12: Reserved, must be kept at reset value */ +#define OTG_DIEPMSK_NAKM (1 << 13) /* Bit 13: NAK interrupt mask */ + /* Bits 14-31: Reserved, must be kept at reset value */ + /* Device OUT endpoint common interrupt mask register */ #define OTG_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ #define OTG_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ - /* Bit 2: Reserved, must be kept at reset value */ + /* Bit 2: Reserved, must be kept at reset value */ #define OTG_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ #define OTG_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ - /* Bits 5-31: Reserved, must be kept at reset value */ + /* Bits 5-31: Reserved, must be kept at reset value */ /* Device all endpoints interrupt and All endpoints interrupt mask registers */ -#define OTG_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ +#define OTG_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ #define OTG_DAINT_IEP_MASK (0xffff << OTG_DAINT_IEP_SHIFT) # define OTG_DAINT_IEP(n) (1 << (n)) #define OTG_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ @@ -693,20 +726,20 @@ # define OTG_DIEPCTL0_MPSIZ_32 (1 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ # define OTG_DIEPCTL0_MPSIZ_16 (2 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ # define OTG_DIEPCTL0_MPSIZ_8 (3 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - /* Bits 2-14: Reserved, must be kept at reset value */ + /* Bits 2-14: Reserved, must be kept at reset value */ #define OTG_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ + /* Bit 16: Reserved, must be kept at reset value */ #define OTG_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ #define OTG_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ #define OTG_DIEPCTL0_EPTYP_MASK (3 << OTG_DIEPCTL0_EPTYP_SHIFT) # define OTG_DIEPCTL0_EPTYP_CTRL (0 << OTG_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ - /* Bit 20: Reserved, must be kept at reset value */ + /* Bit 20: Reserved, must be kept at reset value */ #define OTG_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ #define OTG_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ #define OTG_DIEPCTL0_TXFNUM_MASK (15 << OTG_DIEPCTL0_TXFNUM_SHIFT) #define OTG_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ #define OTG_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ + /* Bits 28-29: Reserved, must be kept at reset value */ #define OTG_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ #define OTG_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ @@ -714,7 +747,7 @@ #define OTG_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ #define OTG_DIEPCTL_MPSIZ_MASK (0x7ff << OTG_DIEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ + /* Bits 11-14: Reserved, must be kept at reset value */ #define OTG_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ #define OTG_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ # define OTG_DIEPCTL_EVEN (0) @@ -728,7 +761,7 @@ # define OTG_DIEPCTL_EPTYP_ISOC (1 << OTG_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ # define OTG_DIEPCTL_EPTYP_BULK (2 << OTG_DIEPCTL_EPTYP_SHIFT) /* Bulk */ # define OTG_DIEPCTL_EPTYP_INTR (3 << OTG_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ - /* Bit 20: Reserved, must be kept at reset value */ + /* Bit 20: Reserved, must be kept at reset value */ #define OTG_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ #define OTG_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ #define OTG_DIEPCTL_TXFNUM_MASK (15 << OTG_DIEPCTL_TXFNUM_SHIFT) @@ -744,21 +777,21 @@ #define OTG_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ #define OTG_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ + /* Bit 2: Reserved, must be kept at reset value */ #define OTG_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ #define OTG_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ - /* Bit 5: Reserved, must be kept at reset value */ + /* Bit 5: Reserved, must be kept at reset value */ #define OTG_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ #define OTG_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ - /* Bits 8-31: Reserved, must be kept at reset value */ + /* Bits 8-31: Reserved, must be kept at reset value */ /* Device IN endpoint 0 transfer size register */ #define OTG_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ #define OTG_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DIEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ + /* Bits 7-18: Reserved, must be kept at reset value */ #define OTG_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ #define OTG_DIEPTSIZ0_PKTCNT_MASK (3 << OTG_DIEPTSIZ0_PKTCNT_SHIFT) - /* Bits 21-31: Reserved, must be kept at reset value */ + /* Bits 21-31: Reserved, must be kept at reset value */ /* Device IN endpoint n transfer size register */ #define OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ @@ -767,7 +800,7 @@ #define OTG_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DIEPTSIZ_PKTCNT_SHIFT) #define OTG_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ #define OTG_DIEPTSIZ_MCNT_MASK (3 << OTG_DIEPTSIZ_MCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ + /* Bit 31: Reserved, must be kept at reset value */ /* Device OUT endpoint TxFIFO status register */ #define OTG_DTXFSTS_MASK (0xffff) @@ -780,19 +813,19 @@ # define OTG_DOEPCTL0_MPSIZ_32 (1 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ # define OTG_DOEPCTL0_MPSIZ_16 (2 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ # define OTG_DOEPCTL0_MPSIZ_8 (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ - /* Bits 2-14: Reserved, must be kept at reset value */ + /* Bits 2-14: Reserved, must be kept at reset value */ #define OTG_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ - /* Bit 16: Reserved, must be kept at reset value */ + /* Bit 16: Reserved, must be kept at reset value */ #define OTG_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ #define OTG_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ #define OTG_DOEPCTL0_EPTYP_MASK (3 << OTG_DOEPCTL0_EPTYP_SHIFT) # define OTG_DOEPCTL0_EPTYP_CTRL (0 << OTG_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ #define OTG_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ #define OTG_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ + /* Bits 22-25: Reserved, must be kept at reset value */ #define OTG_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ #define OTG_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ - /* Bits 28-29: Reserved, must be kept at reset value */ + /* Bits 28-29: Reserved, must be kept at reset value */ #define OTG_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ #define OTG_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ @@ -800,7 +833,7 @@ #define OTG_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ #define OTG_DOEPCTL_MPSIZ_MASK (0x7ff << OTG_DOEPCTL_MPSIZ_SHIFT) - /* Bits 11-14: Reserved, must be kept at reset value */ + /* Bits 11-14: Reserved, must be kept at reset value */ #define OTG_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ #define OTG_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */ # define OTG_DOEPCTL_DATA0 (0) @@ -817,7 +850,7 @@ # define OTG_DOEPCTL_EPTYP_INTR (3 << OTG_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ #define OTG_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ #define OTG_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ - /* Bits 22-25: Reserved, must be kept at reset value */ + /* Bits 22-25: Reserved, must be kept at reset value */ #define OTG_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ #define OTG_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ #define OTG_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ @@ -831,22 +864,22 @@ #define OTG_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ #define OTG_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ - /* Bit 2: Reserved, must be kept at reset value */ + /* Bit 2: Reserved, must be kept at reset value */ #define OTG_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ #define OTG_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ - /* Bit 5: Reserved, must be kept at reset value */ + /* Bit 5: Reserved, must be kept at reset value */ #define OTG_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ - /* Bits 7-31: Reserved, must be kept at reset value */ + /* Bits 7-31: Reserved, must be kept at reset value */ /* Device OUT endpoint-0 transfer size register */ #define OTG_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ #define OTG_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) - /* Bits 7-18: Reserved, must be kept at reset value */ + /* Bits 7-18: Reserved, must be kept at reset value */ #define OTG_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ - /* Bits 20-28: Reserved, must be kept at reset value */ + /* Bits 20-28: Reserved, must be kept at reset value */ #define OTG_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ #define OTG_DOEPTSIZ0_STUPCNT_MASK (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT) - /* Bit 31: Reserved, must be kept at reset value */ + /* Bit 31: Reserved, must be kept at reset value */ /* Device OUT endpoint-n transfer size register */ #define OTG_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ @@ -866,8 +899,57 @@ #define OTG_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ #define OTG_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ - /* Bits 2-3: Reserved, must be kept at reset value */ + /* Bits 2-3: Reserved, must be kept at reset value */ #define OTG_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ - /* Bits 5-31: Reserved, must be kept at reset value */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +/* USB PHYC Registers */ +/* USBPHYC PLL1 control register */ + +#define USBPHYC_PLL1_EN (1 << 0) /* Bit 0: Enable the PLL1 inside PHY */ +#define USBPHYC_PLL1_SEL_SHIFT (1) /* Bits 1-3: Controls the PHY PLL1 input clock frequency selection */ +#define USBPHYC_PLL1_SEL_MASK (7 << USBPHYC_PLL1SEL_SHIFT) +# define USBPHYC_PLL1_SEL_12MHz (0 << USBPHYC_PLL1_SEL_SHIFT) /* 12 MHz */ +# define USBPHYC_PLL1_SEL_12_5MHz (1 << USBPHYC_PLL1_SEL_SHIFT) /* 12.5 MHz */ +# define USBPHYC_PLL1_SEL_12_5bMHz (2 << USBPHYC_PLL1_SEL_SHIFT) /* 12.5 MHz */ +# define USBPHYC_PLL1_SEL_16MHz (3 << USBPHYC_PLL1_SEL_SHIFT) /* 16 MHz */ +# define USBPHYC_PLL1_SEL_24MHz (4 << USBPHYC_PLL1_SEL_SHIFT) /* 24 MHz */ +# define USBPHYC_PLL1_SEL_25MHz (5 << USBPHYC_PLL1_SEL_SHIFT) /* 25 MHz */ +# define USBPHYC_PLL1_SEL_25bMHz (6 << USBPHYC_PLL1_SEL_SHIFT) /* 25 MHz */ + +/* USBPHYC tuning control register */ + +#define USBPHYC_TUNE_INCURREN (1 << 0) /* Bit 0: Controls the current boosting function */ +#define USBPHYC_TUNE_INCURRINT (1 << 1) /* Bit 1: Controls PHY current boosting */ +#define USBPHYC_TUNE_LFSCAPEN (1 << 2) /* Bit 2: Enables the Low Full Speed feedback capacitor */ +#define USBPHYC_TUNE_HSDRVSLEW (1 << 3) /* Bit 3: Controls the HS driver slew rate */ +#define USBPHYC_TUNE_HSDRVDCLEV (1 << 4) /* Bit 4: Decreases the HS driver DC level */ +#define USBPHYC_TUNE_HSDRVDCCUR (1 << 5) /* Bit 5: Increases the HS Driver DC level. Not applicable + * during the HS Test J and Test K data transfer */ +#define USBPHYC_TUNE_HSDRVCURINCR (1 << 6) /* Bit 6: Enable the HS driver current increase feature */ +#define USBPHYC_TUNE_FSDRVRFADJ (1 << 7) /* Bit 7: Tuning pin to adjust the full speed rise/fall time */ +#define USBPHYC_TUNE_HSDRVRFRED (1 << 8) /* Bit 8: High Speed rise-fall reduction enable */ +#define USBPHYC_TUNE_HSDRVCHKITRM_SHIFT (9) /* Bits 9-12 : HS Driver current trimming pins for choke compensation */ +#define USBPHYC_TUNE_HSDRVCHKITRM_MASK (0xF << USBPHYC_TUNE_HSDRVCHKITRM_SHIFT) +#define USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT (13) /* Bits 13-14 : Controls the PHY bus HS driver impedance tuning for choke */ +#define USBPHYC_TUNE_HSDRVCHKZTRM_MASK (3 << USBPHYC_TUNE_HSDRVCHKZTRM_SHIFT) +#define USBPHYC_TUNE_SQLCHCTL_SHIFT (15) /* Bits 15-16 : Adjust the squelch DC threshold value */ +#define USBPHYC_TUNE_SQLCHCTL_MASK (3 << USBPHYC_TUNE_SQLCHCTL_SHIFT) +#define USBPHYC_TUNE_HDRXGNEQEN (1 << 17) /* Bit 17: Enables the HS Rx Gain Equalizer */ +#define USBPHYC_TUNE_STAGSEL (1 << 18) /* Bit 18: HS Tx staggering enable */ +#define USBPHYC_TUNE_HSFALLPREEM (1 << 19) /* Bit 19: HS Fall time control of single ended signals during pre-emphasis */ +#define USBPHYC_TUNE_HSRXOFF_SHIFT (20) /* Bits 20-21 : HS Receiver Offset adjustment */ +#define USBPHYC_TUNE_HSRXOFF_MASK (3 << USBPHYC_TUNE_HSRXOFF_SHIFT) +#define USBPHYC_TUNE_SHTCCTCTLPROT (1 << 22) /* Bit 22: Enables the short circuit protection circuitry in LS/FS driver */ +#define USBPHYC_TUNE_SQLBYP (1 << 23) /* Bit 23: This pin is used to bypass the squelch inter-locking circuitry */ + +/* USBPHYC LDO control and status register */ + +#define USBPHYC_LDO_USED (1 << 0) /* Bit 0: Indicates the presence of the LDO in the chip. */ +#define USBPHYC_LDO_STATUS (1 << 1) /* Bit 1: Monitors the status of the PHY's LDO. */ + +/* It looks like they made a mistake, is it ENABLE or DISABLE? */ + +#define USBPHYC_LDO_ENABLE (1 << 2) /* Bit 2: Controls disable of the High Speed PHY's LDO. */ #endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h index c421d72e8e7..904d9107365 100644 --- a/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h @@ -900,8 +900,11 @@ #define GPIO_UART4_RTS (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN15) #define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1) #define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11) +#define GPIO_UART4_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14) +#define GPIO_UART4_RX_4 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9) #define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0) #define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10) +#define GPIO_UART4_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13) #define GPIO_UART5_CTS (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN9) #define GPIO_UART5_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN8) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h index c5cbbaee4a2..439d3b7d6fc 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h @@ -732,20 +732,20 @@ #define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4) -#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5) -#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3) -#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0) -#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN1) -#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN10) -#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN11) -#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN12) -#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN13) -#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN5) -#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN2) -#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTI|GPIO_PIN11) -#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN3) -#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_PORTH|GPIO_PIN4) -#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_PORTC|GPIO_PIN0) +#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) +#define GPIO_OTGHS_ULPI_D2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#define GPIO_OTGHS_ULPI_D3 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10) +#define GPIO_OTGHS_ULPI_D4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_D5 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12) +#define GPIO_OTGHS_ULPI_D6 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) +#define GPIO_OTGHS_ULPI_D7 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5) +#define GPIO_OTGHS_ULPI_DIR_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) +#define GPIO_OTGHS_ULPI_DIR_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN11) +#define GPIO_OTGHS_ULPI_NXT_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3) +#define GPIO_OTGHS_ULPI_NXT_2 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN4) +#define GPIO_OTGHS_ULPI_STP (GPIO_ALT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN0) /* QuadSPI */ diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index 26ed5f824b0..62def82427f 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -47,13 +47,18 @@ #include "chip.h" #include "chip/stm32_otg.h" -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS) +#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS) /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ + /* Configuration ********************************************************************/ +#ifndef CONFIG_OTG_PRI +# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT +#endif + #if defined(CONFIG_STM32F7_OTGFS) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_USBOTGFS_BASE @@ -62,17 +67,19 @@ # define GPIO_OTG_DP GPIO_OTGFS_DP # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF +# define GPIO_OTG_VBUS GPIO_OTGFS_VBUS # define STM32_OTG_FIFO_SIZE 1280 #endif -#if defined(CONFIG_STM32F7_OTGHS) +#if defined(CONFIG_STM32F7_OTGFSHS) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_USBOTGHS_BASE # define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ -# define GPIO_OTG_DM GPIO_OTGHS_DM -# define GPIO_OTG_DP GPIO_OTGHS_DP -# define GPIO_OTG_ID GPIO_OTGHS_ID -# define GPIO_OTG_SOF GPIO_OTGHS_SOF +# define GPIO_OTG_DM GPIO_OTGHSFS_DM +# define GPIO_OTG_DP GPIO_OTGHSFS_DP +# define GPIO_OTG_ID GPIO_OTGHSFS_ID +# define GPIO_OTG_SOF GPIO_OTGHSFS_SOF +# define GPIO_OTG_VBUS GPIO_OTGHSFS_VBUS # define STM32_OTG_FIFO_SIZE 4096 #endif diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 65dea7403fd..8bfe7f026eb 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -63,9 +63,8 @@ #include "up_arch.h" #include "up_internal.h" - #if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \ - defined(CONFIG_STM32F7_OTGHS)) + defined(CONFIG_STM32F7_OTGFSHS)) /**************************************************************************** * Pre-processor Definitions @@ -73,17 +72,17 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_USBDEV_EP0_MAXSIZE -# define CONFIG_USBDEV_EP0_MAXSIZE 64 -#endif +# ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +# endif -#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE -# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE -#endif +# ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +# endif -#ifndef CONFIG_USBDEV_MAXPOWER -# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ -#endif +# ifndef CONFIG_USBDEV_MAXPOWER +# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ +# endif /* There is 1.25Kb of FIFO memory. The default partitions this memory * so that there is a TxFIFO allocated for each endpoint and with more @@ -91,271 +90,311 @@ * configuration would not allocate any TxFIFO space to OUT endpoints. */ -#ifndef CONFIG_USBDEV_RXFIFO_SIZE -# define CONFIG_USBDEV_RXFIFO_SIZE (STM32_OTG_FIFO_SIZE - STM32_OTG_FIFO_SIZE/4/2/STM32_NENDPOINTS*4*STM32_NENDPOINTS) -#endif - -#if STM32_NENDPOINTS > 0 -# ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE -# define CONFIG_USBDEV_EP0_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# ifndef CONFIG_USBDEV_RXFIFO_SIZE +# define CONFIG_USBDEV_RXFIFO_SIZE 2048 # endif -#else -# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 1 -# ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE -# define CONFIG_USBDEV_EP1_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 0 +# ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 2 -# ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE -# define CONFIG_USBDEV_EP2_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 1 +# ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 3 -# ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE -# define CONFIG_USBDEV_EP3_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 2 +# ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 4 -# ifndef CONFIG_USBDEV_EP4_TXFIFO_SIZE -# define CONFIG_USBDEV_EP4_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 3 +# ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 5 -# ifndef CONFIG_USBDEV_EP5_TXFIFO_SIZE -# define CONFIG_USBDEV_EP5_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 4 +# ifndef CONFIG_USBDEV_EP4_TXFIFO_SIZE +# define CONFIG_USBDEV_EP4_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 6 -# ifndef CONFIG_USBDEV_EP6_TXFIFO_SIZE -# define CONFIG_USBDEV_EP6_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 5 +# ifndef CONFIG_USBDEV_EP5_TXFIFO_SIZE +# define CONFIG_USBDEV_EP5_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP6_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 7 -# ifndef CONFIG_USBDEV_EP7_TXFIFO_SIZE -# define CONFIG_USBDEV_EP7_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 6 +# ifndef CONFIG_USBDEV_EP6_TXFIFO_SIZE +# define CONFIG_USBDEV_EP6_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP6_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP7_TXFIFO_SIZE 0 -#endif -#if STM32_NENDPOINTS > 8 -# ifndef CONFIG_USBDEV_EP8_TXFIFO_SIZE -# define CONFIG_USBDEV_EP8_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# if STM32_NENDPOINTS > 7 +# ifndef CONFIG_USBDEV_EP7_TXFIFO_SIZE +# define CONFIG_USBDEV_EP7_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP7_TXFIFO_SIZE 0 +# endif + +# if STM32_NENDPOINTS > 8 +# ifndef CONFIG_USBDEV_EP8_TXFIFO_SIZE +# define CONFIG_USBDEV_EP8_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +# else +# define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0 # endif -#else -# define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0 -#endif /* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; * FIFO sizes must be provided in units of 32-bit words. */ -#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) -#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) +# define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +# define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) -#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP6_TXFIFO_BYTES ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP6_TXFIFO_WORDS ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP6_TXFIFO_BYTES ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP6_TXFIFO_WORDS ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP7_TXFIFO_BYTES ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP7_TXFIFO_WORDS ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP7_TXFIFO_BYTES ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP7_TXFIFO_WORDS ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) >> 2) -#define STM32_EP8_TXFIFO_BYTES ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) & ~3) -#define STM32_EP8_TXFIFO_WORDS ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) >> 2) +# define STM32_EP8_TXFIFO_BYTES ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) & ~3) +# define STM32_EP8_TXFIFO_WORDS ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) >> 2) - -#if (STM32_RXFIFO_BYTES + \ +# if (STM32_RXFIFO_BYTES + \ STM32_EP0_TXFIFO_BYTES + STM32_EP1_TXFIFO_BYTES + STM32_EP2_TXFIFO_BYTES + STM32_EP3_TXFIFO_BYTES + \ STM32_EP4_TXFIFO_BYTES + STM32_EP5_TXFIFO_BYTES + STM32_EP6_TXFIFO_BYTES + STM32_EP7_TXFIFO_BYTES + CONFIG_USBDEV_EP8_TXFIFO_SIZE \ ) > STM32_OTG_FIFO_SIZE -# error "FIFO allocations exceed FIFO memory size" -#endif +# error "FIFO allocations exceed FIFO memory size" +# endif -#define OTG_GINT_RESERVED (OTG_GINT_RES89 | \ - OTG_GINT_RES1617 | \ - OTG_GINT_RES22) +# define OTG_GINT_RESERVED_FS (OTG_GINT_RES89 | \ + OTG_GINT_RES1617 | \ + OTG_GINT_RES22) +# define OTG_GINT_RESERVED_HS (OTG_GINT_RES89 | \ + OTG_GINT_RES1617 | \ + OTG_GINT_RES23 | \ + OTG_GINT_RES27) -#define OTG_GINT_RC_W1 (OTG_GINT_MMIS | \ - OTG_GINT_SOF | \ - OTG_GINT_ESUSP | \ - OTG_GINT_USBSUSP | \ - OTG_GINT_USBRST | \ - OTG_GINT_ENUMDNE | \ - OTG_GINT_ISOODRP | \ - OTG_GINT_EOPF | \ - OTG_GINT_IISOIXFR | \ - OTG_GINT_IISOOXFR | \ - OTG_GINT_RSTDET | \ - OTG_GINT_LPMINT | \ - OTG_GINT_CIDSCHG | \ - OTG_GINT_DISC | \ - OTG_GINT_SRQ | \ - OTG_GINT_WKUP) +# define OTG_GINT_RC_W1_FS (OTG_GINT_MMIS | \ + OTG_GINT_SOF | \ + OTG_GINT_ESUSP | \ + OTG_GINT_USBSUSP | \ + OTG_GINT_USBRST | \ + OTG_GINT_ENUMDNE | \ + OTG_GINT_ISOODRP | \ + OTG_GINT_EOPF | \ + OTG_GINT_IISOIXFR | \ + OTG_GINT_IISOOXFR | \ + OTG_GINT_RSTDET | \ + OTG_GINT_LPMINT | \ + OTG_GINT_CIDSCHG | \ + OTG_GINT_DISC | \ + OTG_GINT_SRQ | \ + OTG_GINT_WKUP) +# define OTG_GINT_RC_W1_HS (OTG_GINT_MMIS | \ + OTG_GINT_SOF | \ + OTG_GINT_ESUSP | \ + OTG_GINT_USBSUSP | \ + OTG_GINT_USBRST | \ + OTG_GINT_ENUMDNE | \ + OTG_GINT_ISOODRP | \ + OTG_GINT_EOPF | \ + OTG_GINT_IISOIXFR | \ + OTG_GINT_IISOOXFR | \ + OTG_GINT_DATAFSUSP| \ + OTG_GINT_CIDSCHG | \ + OTG_GINT_DISC | \ + OTG_GINT_SRQ | \ + OTG_GINT_WKUP) + +/* Only stm32F723 has internal ULPI. We consider in HS only if a ULPI is present */ + +# ifdef CONFIG_STM32F7_OTGFSHS +# define OTG_GINT_RESERVED OTG_GINT_RESERVED_HS +# define OTG_GINT_RC_W1 OTG_GINT_RC_W1_HS +# else +# define OTG_GINT_RESERVED OTG_GINT_RESERVED_FS +# define OTG_GINT_RC_W1 OTG_GINT_RC_W1_FS +# endif /* Debug ***********************************************************************/ + /* Trace error codes */ -#define STM32_TRACEERR_ALLOCFAIL 0x01 -#define STM32_TRACEERR_BADCLEARFEATURE 0x02 -#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 -#define STM32_TRACEERR_BADEPNO 0x04 -#define STM32_TRACEERR_BADEPGETSTATUS 0x05 -#define STM32_TRACEERR_BADGETCONFIG 0x06 -#define STM32_TRACEERR_BADGETSETDESC 0x07 -#define STM32_TRACEERR_BADGETSTATUS 0x08 -#define STM32_TRACEERR_BADSETADDRESS 0x09 -#define STM32_TRACEERR_BADSETCONFIG 0x0a -#define STM32_TRACEERR_BADSETFEATURE 0x0b -#define STM32_TRACEERR_BADTESTMODE 0x0c -#define STM32_TRACEERR_BINDFAILED 0x0d -#define STM32_TRACEERR_DISPATCHSTALL 0x0e -#define STM32_TRACEERR_DRIVER 0x0f -#define STM32_TRACEERR_DRIVERREGISTERED 0x10 -#define STM32_TRACEERR_EP0NOSETUP 0x11 -#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 -#define STM32_TRACEERR_EPINNULLPACKET 0x13 -#define STM32_TRACEERR_EPINUNEXPECTED 0x14 -#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 -#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 -#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 -#define STM32_TRACEERR_INVALIDPARMS 0x18 -#define STM32_TRACEERR_IRQREGISTRATION 0x19 -#define STM32_TRACEERR_NOEP 0x1a -#define STM32_TRACEERR_NOTCONFIGURED 0x1b -#define STM32_TRACEERR_EPOUTQEMPTY 0x1c -#define STM32_TRACEERR_EPINREQEMPTY 0x1d -#define STM32_TRACEERR_NOOUTSETUP 0x1e -#define STM32_TRACEERR_POLLTIMEOUT 0x1f +# define STM32_TRACEERR_ALLOCFAIL 0x01 +# define STM32_TRACEERR_BADCLEARFEATURE 0x02 +# define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +# define STM32_TRACEERR_BADEPNO 0x04 +# define STM32_TRACEERR_BADEPGETSTATUS 0x05 +# define STM32_TRACEERR_BADGETCONFIG 0x06 +# define STM32_TRACEERR_BADGETSETDESC 0x07 +# define STM32_TRACEERR_BADGETSTATUS 0x08 +# define STM32_TRACEERR_BADSETADDRESS 0x09 +# define STM32_TRACEERR_BADSETCONFIG 0x0a +# define STM32_TRACEERR_BADSETFEATURE 0x0b +# define STM32_TRACEERR_BADTESTMODE 0x0c +# define STM32_TRACEERR_BINDFAILED 0x0d +# define STM32_TRACEERR_DISPATCHSTALL 0x0e +# define STM32_TRACEERR_DRIVER 0x0f +# define STM32_TRACEERR_DRIVERREGISTERED 0x10 +# define STM32_TRACEERR_EP0NOSETUP 0x11 +# define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +# define STM32_TRACEERR_EPINNULLPACKET 0x13 +# define STM32_TRACEERR_EPINUNEXPECTED 0x14 +# define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +# define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +# define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +# define STM32_TRACEERR_INVALIDPARMS 0x18 +# define STM32_TRACEERR_IRQREGISTRATION 0x19 +# define STM32_TRACEERR_NOEP 0x1a +# define STM32_TRACEERR_NOTCONFIGURED 0x1b +# define STM32_TRACEERR_EPOUTQEMPTY 0x1c +# define STM32_TRACEERR_EPINREQEMPTY 0x1d +# define STM32_TRACEERR_NOOUTSETUP 0x1e +# define STM32_TRACEERR_POLLTIMEOUT 0x1f /* Trace interrupt codes */ -#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ -#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ +# define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +# define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the + * loop */ -#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ -#define STM32_TRACEINTID_EPIN (10 + 1) -#define STM32_TRACEINTID_MISMATCH (10 + 2) -#define STM32_TRACEINTID_WAKEUP (10 + 3) -#define STM32_TRACEINTID_SUSPEND (10 + 4) -#define STM32_TRACEINTID_SOF (10 + 5) -#define STM32_TRACEINTID_RXFIFO (10 + 6) -#define STM32_TRACEINTID_DEVRESET (10 + 7) -#define STM32_TRACEINTID_ENUMDNE (10 + 8) -#define STM32_TRACEINTID_IISOIXFR (10 + 9) -#define STM32_TRACEINTID_IISOOXFR (10 + 10) -#define STM32_TRACEINTID_SRQ (10 + 11) -#define STM32_TRACEINTID_OTG (10 + 12) +# define STM32_TRACEINTID_EPOUT (10 + 0) /* First level + * interrupt decode */ +# define STM32_TRACEINTID_EPIN (10 + 1) +# define STM32_TRACEINTID_MISMATCH (10 + 2) +# define STM32_TRACEINTID_WAKEUP (10 + 3) +# define STM32_TRACEINTID_SUSPEND (10 + 4) +# define STM32_TRACEINTID_SOF (10 + 5) +# define STM32_TRACEINTID_RXFIFO (10 + 6) +# define STM32_TRACEINTID_DEVRESET (10 + 7) +# define STM32_TRACEINTID_ENUMDNE (10 + 8) +# define STM32_TRACEINTID_IISOIXFR (10 + 9) +# define STM32_TRACEINTID_IISOOXFR (10 + 10) +# define STM32_TRACEINTID_SRQ (10 + 11) +# define STM32_TRACEINTID_OTG (10 + 12) -#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ -#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) -#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) -#define STM32_TRACEINTID_DISPATCH (40 + 3) +# define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level + * decode */ +# define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +# define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +# define STM32_TRACEINTID_DISPATCH (40 + 3) -#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ -#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) -#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) -#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) -#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) -#define STM32_TRACEINTID_SETFEATURE (50 + 5) -#define STM32_TRACEINTID_SETADDRESS (50 + 6) -#define STM32_TRACEINTID_GETSETDESC (50 + 7) -#define STM32_TRACEINTID_GETCONFIG (50 + 8) -#define STM32_TRACEINTID_SETCONFIG (50 + 9) -#define STM32_TRACEINTID_GETSETIF (50 + 10) -#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) +# define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level + * decode */ +# define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +# define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +# define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +# define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +# define STM32_TRACEINTID_SETFEATURE (50 + 5) +# define STM32_TRACEINTID_SETADDRESS (50 + 6) +# define STM32_TRACEINTID_GETSETDESC (50 + 7) +# define STM32_TRACEINTID_GETCONFIG (50 + 8) +# define STM32_TRACEINTID_SETCONFIG (50 + 9) +# define STM32_TRACEINTID_GETSETIF (50 + 10) +# define STM32_TRACEINTID_SYNCHFRAME (50 + 11) -#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ -#define STM32_TRACEINTID_EPIN_TOC (70 + 1) -#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) -#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) -#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) +# define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level + * decode */ +# define STM32_TRACEINTID_EPIN_TOC (70 + 1) +# define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +# define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +# define STM32_TRACEINTID_EPIN_TXFE (70 + 4) -#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ +# define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level + * decode */ -#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ -#define STM32_TRACEINTID_OUTRECVD (90 + 1) -#define STM32_TRACEINTID_OUTDONE (90 + 2) -#define STM32_TRACEINTID_SETUPDONE (90 + 3) -#define STM32_TRACEINTID_SETUPRECVD (90 + 4) +# define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level + * decode */ +# define STM32_TRACEINTID_OUTRECVD (90 + 1) +# define STM32_TRACEINTID_OUTDONE (90 + 2) +# define STM32_TRACEINTID_SETUPDONE (90 + 3) +# define STM32_TRACEINTID_SETUPRECVD (90 + 4) /* Endpoints ******************************************************************/ /* Odd physical endpoint numbers are IN; even are OUT */ -#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) -#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) +# define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +# define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) /* Endpoint 0 */ -#define EP0 (0) +# define EP0 (0) /* The set of all enpoints available to the class implementation (1-3) */ -#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */ +# define STM32_EP_AVAILABLE (0xfe) /* All available endpoints */ /* Maximum packet sizes for full speed endpoints */ -#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ +# ifdef CONFIG_STM32F7_OTGFSHS +# define STM32_MAXPACKET (512) /* Max packet size (1-512) */ +# else +# define STM32_MAXPACKET (64) /* Max packet size (1-64) */ +# endif /* Delays **********************************************************************/ -#define STM32_READY_DELAY 200000 -#define STM32_FLUSH_DELAY 200000 +# define STM32_READY_DELAY 200000 +# define STM32_FLUSH_DELAY 200000 /* Request queue operations ****************************************************/ -#define stm32_rqempty(ep) ((ep)->head == NULL) -#define stm32_rqpeek(ep) ((ep)->head) +# define stm32_rqempty(ep) ((ep)->head == NULL) +# define stm32_rqpeek(ep) ((ep)->head) /* Standard stuff **************************************************************/ -#ifndef MIN -# define MIN(a,b) ((a) < (b) ? (a) : (b)) -#endif +# ifndef MIN +# define MIN(a,b) ((a) < (b) ? (a) : (b)) +# endif -#ifndef MAX -# define MAX(a,b) ((a) > (b) ? (a) : (b)) -#endif +# ifndef MAX +# define MAX(a,b) ((a) > (b) ? (a) : (b)) +# endif /**************************************************************************** * Private Types @@ -365,91 +404,78 @@ enum stm32_devstate_e { - DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply - * means that the device is not yet been given an - * address. - * SET: At initialization, uninitialization, - * reset, and whenever the device address - * is set to zero - * TESTED: Never - */ - DEVSTATE_ADDRESSED, /* Device address has been assigned, not no - * configuration has yet been selected. - * SET: When either a non-zero device address - * is first assigned or when the device - * is unconfigured (with configuration == 0) - * TESTED: never - */ - DEVSTATE_CONFIGURED, /* Address assigned and configured: - * SET: When the device has been addressed and - * an non-zero configuration has been selected. - * TESTED: In many places to assure that the USB device - * has been properly configured by the host. - */ + DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state + * simply means that the device is not yet been + * given an address. SET: At initialization, + * uninitialization, reset, and whenever the + * device address is set to zero TESTED: Never */ + DEVSTATE_ADDRESSED, /* Device address has been assigned, not no + * configuration has yet been selected. SET: + * When either a non-zero device address is + * first assigned or when the device is + * unconfigured (with configuration == 0) + * TESTED: never */ + DEVSTATE_CONFIGURED, /* Address assigned and configured: SET: When + * the device has been addressed and an + * non-zero configuration has been selected. + * TESTED: In many places to assure that the + * USB device has been properly configured by + * the host. */ }; /* Endpoint 0 states */ enum stm32_ep0state_e { - EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or - * epsubmit: - * SET: In stm32_epin() and stm32_epout() when - * we revert from request processing to - * SETUP processing. - * TESTED: Never - */ - EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA - * OUT phase of SETUP Packet to complete before - * processing a SETUP command (without a USB request): - * SET: Set in stm32_rxinterrupt() when SETUP OUT - * packet is received. - * TESTED: In stm32_ep0out_receive() - */ - EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and - * accompanying data have been received. Processing - * of SETUP command will happen soon. - * SET: (1) stm32_ep0out_receive() when the OUT - * SETUP data phase completes, or (2) - * stm32_rxinterrupt() when an IN SETUP is - * packet received. - * TESTED: Tested in stm32_epout_interrupt() when - * SETUP phase is done to see if the SETUP - * command is ready to be processed. Also - * tested in stm32_ep0out_setup() just to - * double-check that we have a SETUP request - * and any accompanying data. - */ - EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): - * SET: When SETUP packet received in EP0 OUT - * TESTED: Never - */ - EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): - * SET: When SETUP response is sent by - * stm32_ep0in_setupresponse() - * TESTED: Never - */ - EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): - * SET: In stm32_epin_request() when a write - * request is processed on EP0. - * TESTED: In stm32_epin() to see if we should - * revert to SETUP processing. - */ - EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a - * USB request) - * SET: In stm32_epout_request() when a read - * request is processed on EP0. - * TESTED: In stm32_epout() to see if we should - * revert to SETUP processing - */ + EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP + * packet or epsubmit: SET: In stm32_epin() and + * stm32_epout() when we revert from request + * processing to SETUP processing. TESTED: + * Never */ + EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the + * DATA OUT phase of SETUP Packet to complete + * before processing a SETUP command (without a + * USB request): SET: Set in + * stm32_rxinterrupt() when SETUP OUT packet is + * received. TESTED: In stm32_ep0out_receive() */ + EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP + * packet and accompanying data have been + * received. Processing of SETUP command will + * happen soon. SET: (1) + * stm32_ep0out_receive() when the OUT SETUP + * data phase completes, or (2) + * stm32_rxinterrupt() when an IN SETUP is + * packet received. TESTED: Tested in + * stm32_epout_interrupt() when SETUP phase is + * done to see if the SETUP command is ready to + * be processed. Also tested in + * stm32_ep0out_setup() just to double-check + * that we have a SETUP request and any + * accompanying data. */ + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by + * stm32_ep0out_setup(): SET: When SETUP packet + * received in EP0 OUT TESTED: Never */ + EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB + * request): SET: When SETUP response is sent + * by stm32_ep0in_setupresponse() TESTED: Never */ + EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB + * request): SET: In stm32_epin_request() when + * a write request is processed on EP0. + * TESTED: In stm32_epin() to see if we should + * revert to SETUP processing. */ + EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with + * a USB request) SET: In stm32_epout_request() + * when a read request is processed on EP0. + * TESTED: In stm32_epout() to see if we should + * revert to SETUP processing */ }; /* Parsed control request */ struct stm32_ctrlreq_s { - uint8_t type; - uint8_t req; + uint8_t type; + uint8_t req; uint16_t value; uint16_t index; uint16_t len; @@ -459,8 +485,8 @@ struct stm32_ctrlreq_s struct stm32_req_s { - struct usbdev_req_s req; /* Standard USB request */ - struct stm32_req_s *flink; /* Supports a singly linked list */ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ @@ -472,20 +498,21 @@ struct stm32_ep_s * to struct stm32_ep_s. */ - struct usbdev_ep_s ep; /* Standard endpoint structure */ + struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STM32-specific fields */ - struct stm32_usbdev_s *dev; /* Reference to private driver data */ - struct stm32_req_s *head; /* Request list for this endpoint */ - struct stm32_req_s *tail; - uint8_t epphy; /* Physical EP address */ - uint8_t eptype:2; /* Endpoint type */ - uint8_t active:1; /* 1: A request is being processed */ - uint8_t stalled:1; /* 1: Endpoint is stalled */ - uint8_t isin:1; /* 1: IN Endpoint */ - uint8_t odd:1; /* 1: Odd frame */ - uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */ + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t epphy; /* Physical EP address */ + uint8_t eptype:2; /* Endpoint type */ + uint8_t active:1; /* 1: A request is being processed */ + uint8_t stalled:1; /* 1: Endpoint is stalled */ + uint8_t isin:1; /* 1: IN Endpoint */ + uint8_t odd:1; /* 1: Odd frame */ + uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs + * only) */ }; /* This structure retains the state of the USB device controller */ @@ -493,11 +520,11 @@ struct stm32_ep_s struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the - * structure so that it is possible to simply cast from struct usbdev_s - * to struct stm32_usbdev_s. + * structure so that it is possible to simply cast from struct usbdev_s to + * struct stm32_usbdev_s. */ - struct usbdev_s usbdev; + struct usbdev_s usbdev; /* The bound device class driver */ @@ -505,46 +532,37 @@ struct stm32_usbdev_s /* STM32-specific fields */ - uint8_t stalled:1; /* 1: Protocol stalled */ - uint8_t selfpowered:1; /* 1: Device is self powered */ - uint8_t addressed:1; /* 1: Peripheral address has been set */ - uint8_t configured:1; /* 1: Class driver has been configured */ - uint8_t wakeup:1; /* 1: Device remote wake-up */ - uint8_t dotest:1; /* 1: Test mode selected */ + uint8_t stalled:1; /* 1: Protocol stalled */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t addressed:1; /* 1: Peripheral address has been set */ + uint8_t configured:1; /* 1: Class driver has been configured */ + uint8_t wakeup:1; /* 1: Device remote wake-up */ + uint8_t dotest:1; /* 1: Test mode selected */ - uint8_t devstate:4; /* See enum stm32_devstate_e */ - uint8_t ep0state:4; /* See enum stm32_ep0state_e */ - uint8_t testmode:4; /* Selected test mode */ - uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ + uint8_t testmode:4; /* Selected test mode */ + uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ - /* E0 SETUP data buffering. - * - * ctrlreq: - * The 8-byte SETUP request is received on the EP0 OUT endpoint and is - * saved. - * - * ep0data - * For OUT SETUP requests, the SETUP data phase must also complete before - * the SETUP command can be processed. The pack receipt logic will save - * the accompanying EP0 IN data in ep0data[] before the SETUP command is - * processed. - * - * For IN SETUP requests, the DATA phase will occur AFTER the SETUP - * control request is processed. In that case, ep0data[] may be used as - * the response buffer. - * - * ep0datlen - * Length of OUT DATA received in ep0data[] (Not used with OUT data) + /* E0 SETUP data buffering. ctrlreq: The 8-byte SETUP request is received + * on the EP0 OUT endpoint and is saved. ep0data For OUT SETUP requests, + * the SETUP data phase must also complete before the SETUP command can be + * processed. The pack receipt logic will save the accompanying EP0 IN + * data in ep0data[] before the SETUP command is processed. For IN SETUP + * requests, the DATA phase will occur AFTER the SETUP control request is + * processed. In that case, ep0data[] may be used as the response buffer. + * ep0datlen Length of OUT DATA received in ep0data[] (Not used with OUT + * data) */ - struct usb_ctrlreq_s ctrlreq; - uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; - uint16_t ep0datlen; + struct usb_ctrlreq_s ctrlreq; + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; /* The endpoint lists */ - struct stm32_ep_s epin[STM32_NENDPOINTS]; - struct stm32_ep_s epout[STM32_NENDPOINTS]; + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -553,76 +571,76 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32_getreg(uint32_t addr); -static void stm32_putreg(uint32_t val, uint32_t addr); -#else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -#endif +# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); +# else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +# endif /* Request queue operations **************************************************/ -static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep); -static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, - FAR struct stm32_req_s *req); +static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s + *privep); +static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, + FAR struct stm32_req_s *req); /* Low level data transfers and request operations ***************************/ + /* Special endpoint 0 data transfer logic */ -static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv, - FAR uint8_t *data, uint32_t nbytes); +static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv, + FAR uint8_t * data, uint32_t nbytes); static inline void stm32_ep0in_transmitzlp(FAR struct stm32_usbdev_s *priv); -static void stm32_ep0in_activate(void); +static void stm32_ep0in_activate(void); -static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv); +static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv); /* IN request and TxFIFO handling */ -static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, - FAR uint8_t *buf, int nbytes); -static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, - FAR uint8_t *buf, int nbytes); -static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, - FAR struct stm32_ep_s *privep); +static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, + FAR uint8_t * buf, int nbytes); +static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, + FAR uint8_t * buf, int nbytes); +static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); /* OUT request and RxFIFO handling */ -static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, - FAR uint8_t *dest, uint16_t len); -static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len); -static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, - FAR struct stm32_ep_s *privep); -static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt); +static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, + FAR uint8_t * dest, uint16_t len); +static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len); +static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, + int bcnt); static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt); -static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, - FAR struct stm32_ep_s *privep); +static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); /* General request handling */ -static void stm32_ep_flush(FAR struct stm32_ep_s *privep); -static void stm32_req_complete(FAR struct stm32_ep_s *privep, - int16_t result); -static void stm32_req_cancel(FAR struct stm32_ep_s *privep, - int16_t status); +static void stm32_ep_flush(FAR struct stm32_ep_s *privep); +static void stm32_req_complete(FAR struct stm32_ep_s *privep, int16_t result); +static void stm32_req_cancel(FAR struct stm32_ep_s *privep, int16_t status); /* Interrupt handling ********************************************************/ -static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, - uint16_t eplog); -static int stm32_req_dispatch(FAR struct stm32_usbdev_s *priv, - FAR const struct usb_ctrlreq_s *ctrl); -static void stm32_usbreset(FAR struct stm32_usbdev_s *priv); +static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, + uint16_t eplog); +static int stm32_req_dispatch(FAR struct stm32_usbdev_s *priv, + FAR const struct usb_ctrlreq_s *ctrl); +static void stm32_usbreset(FAR struct stm32_usbdev_s *priv); /* Second level OUT endpoint interrupt processing */ static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, - uint16_t index); + uint16_t index); static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, - FAR struct stm32_ctrlreq_s *ctrlreq); + FAR struct stm32_ctrlreq_s *ctrlreq); static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); -static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, - uint8_t epno); +static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno); static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv); /* Second level IN endpoint interrupt processing */ @@ -630,7 +648,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv); static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv); static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno); static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, - int epno); + int epno); static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv); /* Other second level interrupt processing */ @@ -639,97 +657,95 @@ static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv); static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv); static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv); static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv); -#ifdef CONFIG_USBDEV_ISOCHRONOUS +# ifdef CONFIG_USBDEV_ISOCHRONOUS static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv); static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv); -#endif -#ifdef CONFIG_USBDEV_VBUSSENSING +# endif +# ifdef CONFIG_USBDEV_VBUSSENSING static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv); static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); -#endif +# endif /* First level interrupt processing */ -static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); +static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg); /* Endpoint operations *********************************************************/ + /* Global OUT NAK controls */ -static void stm32_enablegonak(FAR struct stm32_ep_s *privep); -static void stm32_disablegonak(FAR struct stm32_ep_s *privep); +static void stm32_enablegonak(FAR struct stm32_ep_s *privep); +static void stm32_disablegonak(FAR struct stm32_ep_s *privep); /* Endpoint configuration */ -static int stm32_epout_configure(FAR struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket); -static int stm32_epin_configure(FAR struct stm32_ep_s *privep, - uint8_t eptype, uint16_t maxpacket); -static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, - FAR const struct usb_epdesc_s *desc, bool last); -static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv); +static int stm32_epout_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_epin_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, + FAR const struct usb_epdesc_s *desc, bool last); +static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv); /* Endpoint disable */ -static void stm32_epout_disable(FAR struct stm32_ep_s *privep); -static void stm32_epin_disable(FAR struct stm32_ep_s *privep); -static int stm32_ep_disable(FAR struct usbdev_ep_s *ep); +static void stm32_epout_disable(FAR struct stm32_ep_s *privep); +static void stm32_epin_disable(FAR struct stm32_ep_s *privep); +static int stm32_ep_disable(FAR struct usbdev_ep_s *ep); /* Endpoint request management */ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep); -static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, - FAR struct usbdev_req_s *); +static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *); /* Endpoint buffer management */ -#ifdef CONFIG_USBDEV_DMA -static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, - uint16_t bytes); -static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, - FAR void *buf); -#endif +# ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes); +static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf); +# endif /* Endpoint request submission */ -static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, - struct usbdev_req_s *req); +static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, + struct usbdev_req_s *req); /* Endpoint request cancellation */ -static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, - struct usbdev_req_s *req); +static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, + struct usbdev_req_s *req); /* Stall handling */ -static int stm32_epout_setstall(FAR struct stm32_ep_s *privep); -static int stm32_epin_setstall(FAR struct stm32_ep_s *privep); -static int stm32_ep_setstall(FAR struct stm32_ep_s *privep); -static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep); -static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume); -static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv); +static int stm32_epout_setstall(FAR struct stm32_ep_s *privep); +static int stm32_epin_setstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_setstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv); /* Endpoint allocation */ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, - uint8_t epno, bool in, uint8_t eptype); -static void stm32_ep_free(FAR struct usbdev_s *dev, - FAR struct usbdev_ep_s *ep); + uint8_t epno, bool in, + uint8_t eptype); +static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep); /* USB device controller operations ********************************************/ -static int stm32_getframe(struct usbdev_s *dev); -static int stm32_wakeup(struct usbdev_s *dev); -static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32_pullup(struct usbdev_s *dev, bool enable); -static void stm32_setaddress(struct stm32_usbdev_s *priv, - uint16_t address); -static int stm32_txfifo_flush(uint32_t txfnum); -static int stm32_rxfifo_flush(void); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); /* Initialization **************************************************************/ -static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv); -static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv); +static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -743,123 +759,123 @@ static struct stm32_usbdev_s g_otghsdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32_ep_configure, - .disable = stm32_ep_disable, - .allocreq = stm32_ep_allocreq, - .freereq = stm32_ep_freereq, -#ifdef CONFIG_USBDEV_DMA + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, +# ifdef CONFIG_USBDEV_DMA .allocbuffer = stm32_ep_allocbuffer, - .freebuffer = stm32_ep_freebuffer, -#endif - .submit = stm32_ep_submit, - .cancel = stm32_ep_cancel, - .stall = stm32_ep_stall, + .freebuffer = stm32_ep_freebuffer, +# endif + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32_ep_alloc, - .freeep = stm32_ep_free, - .getframe = stm32_getframe, - .wakeup = stm32_wakeup, + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, .selfpowered = stm32_selfpowered, - .pullup = stm32_pullup, + .pullup = stm32_pullup, }; /* Device error strings that may be enabled for more descriptive USB trace * output. */ -#ifdef CONFIG_USBDEV_TRACE_STRINGS +# ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32_TRACEERR_ALLOCFAIL ), - TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE ), - TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS ), - TRACE_STR(STM32_TRACEERR_BADEPNO ), - TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS ), - TRACE_STR(STM32_TRACEERR_BADGETCONFIG ), - TRACE_STR(STM32_TRACEERR_BADGETSETDESC ), - TRACE_STR(STM32_TRACEERR_BADGETSTATUS ), - TRACE_STR(STM32_TRACEERR_BADSETADDRESS ), - TRACE_STR(STM32_TRACEERR_BADSETCONFIG ), - TRACE_STR(STM32_TRACEERR_BADSETFEATURE ), - TRACE_STR(STM32_TRACEERR_BADTESTMODE ), - TRACE_STR(STM32_TRACEERR_BINDFAILED ), - TRACE_STR(STM32_TRACEERR_DISPATCHSTALL ), - TRACE_STR(STM32_TRACEERR_DRIVER ), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32_TRACEERR_EP0NOSETUP ), - TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED ), - TRACE_STR(STM32_TRACEERR_EPINNULLPACKET ), - TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED ), - TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET ), - TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED ), - TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ ), - TRACE_STR(STM32_TRACEERR_INVALIDPARMS ), - TRACE_STR(STM32_TRACEERR_IRQREGISTRATION ), - TRACE_STR(STM32_TRACEERR_NOEP ), - TRACE_STR(STM32_TRACEERR_NOTCONFIGURED ), - TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY ), - TRACE_STR(STM32_TRACEERR_EPINREQEMPTY ), - TRACE_STR(STM32_TRACEERR_NOOUTSETUP ), - TRACE_STR(STM32_TRACEERR_POLLTIMEOUT ), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), TRACE_STR_END }; -#endif +# endif /* Interrupt event strings that may be enabled for more descriptive USB trace * output. */ -#ifdef CONFIG_USBDEV_TRACE_STRINGS +# ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32_TRACEINTID_USB ), - TRACE_STR(STM32_TRACEINTID_INTPENDING ), - TRACE_STR(STM32_TRACEINTID_EPOUT ), - TRACE_STR(STM32_TRACEINTID_EPIN ), - TRACE_STR(STM32_TRACEINTID_MISMATCH ), - TRACE_STR(STM32_TRACEINTID_WAKEUP ), - TRACE_STR(STM32_TRACEINTID_SUSPEND ), - TRACE_STR(STM32_TRACEINTID_SOF ), - TRACE_STR(STM32_TRACEINTID_RXFIFO ), - TRACE_STR(STM32_TRACEINTID_DEVRESET ), - TRACE_STR(STM32_TRACEINTID_ENUMDNE ), - TRACE_STR(STM32_TRACEINTID_IISOIXFR ), - TRACE_STR(STM32_TRACEINTID_IISOOXFR ), - TRACE_STR(STM32_TRACEINTID_SRQ ), - TRACE_STR(STM32_TRACEINTID_OTG ), - TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC ), + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP ), - TRACE_STR(STM32_TRACEINTID_DISPATCH ), - TRACE_STR(STM32_TRACEINTID_GETSTATUS ), - TRACE_STR(STM32_TRACEINTID_EPGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32_TRACEINTID_IFGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32_TRACEINTID_SETFEATURE ), - TRACE_STR(STM32_TRACEINTID_SETADDRESS ), - TRACE_STR(STM32_TRACEINTID_GETSETDESC ), - TRACE_STR(STM32_TRACEINTID_GETCONFIG ), - TRACE_STR(STM32_TRACEINTID_SETCONFIG ), - TRACE_STR(STM32_TRACEINTID_GETSETIF ), - TRACE_STR(STM32_TRACEINTID_SYNCHFRAME ), - TRACE_STR(STM32_TRACEINTID_EPIN_XFRC ), - TRACE_STR(STM32_TRACEINTID_EPIN_TOC ), - TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE ), - TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD ), - TRACE_STR(STM32_TRACEINTID_EPIN_TXFE ), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32_TRACEINTID_OUTNAK ), - TRACE_STR(STM32_TRACEINTID_OUTRECVD ), - TRACE_STR(STM32_TRACEINTID_OUTDONE ), - TRACE_STR(STM32_TRACEINTID_SETUPDONE ), - TRACE_STR(STM32_TRACEINTID_SETUPRECVD ), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), TRACE_STR_END }; -#endif +# endif /**************************************************************************** * Private Functions @@ -873,7 +889,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -884,8 +900,8 @@ static uint32_t stm32_getreg(uint32_t addr) uint32_t val = getreg32(addr); - /* Is this the same value that we read from the same register last time? Are - * we polling the register? If so, suppress some of the output. + /* Is this the same value that we read from the same register last time? Are + * we polling the register? If so, suppress some of the output. */ if (addr == prevaddr && val == preval) @@ -911,14 +927,14 @@ static uint32_t stm32_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - uinfo("[repeats %d more times]\n", count-3); + uinfo("[repeats %d more times]\n", count - 3); } /* Save the new address, value, and count */ prevaddr = addr; - preval = val; - count = 1; + preval = val; + count = 1; } /* Show the register value read */ @@ -926,7 +942,7 @@ static uint32_t stm32_getreg(uint32_t addr) uinfo("%08x->%08x\n", addr, val); return val; } -#endif +# endif /**************************************************************************** * Name: stm32_putreg @@ -936,7 +952,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -947,7 +963,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) putreg32(val, addr); } -#endif +# endif /**************************************************************************** * Name: stm32_req_remfirst @@ -997,7 +1013,7 @@ static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, else { privep->tail->flink = req; - privep->tail = req; + privep->tail = req; } return is_empty; @@ -1012,7 +1028,7 @@ static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, ****************************************************************************/ static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv, - FAR uint8_t *buf, uint32_t nbytes) + FAR uint8_t * buf, uint32_t nbytes) { stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); priv->ep0state = EP0STATE_SETUPRESPONSE; @@ -1044,28 +1060,28 @@ static void stm32_ep0in_activate(void) { uint32_t regval; - /* Set the max packet size of the IN EP. */ + /* Set the max packet size of the IN EP. */ - regval = stm32_getreg(STM32_OTG_DIEPCTL(0)); + regval = stm32_getreg(STM32_OTG_DIEPCTL(0)); regval &= ~OTG_DIEPCTL0_MPSIZ_MASK; -#if CONFIG_USBDEV_EP0_MAXSIZE == 8 +# if CONFIG_USBDEV_EP0_MAXSIZE == 8 regval |= OTG_DIEPCTL0_MPSIZ_8; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 16 +# elif CONFIG_USBDEV_EP0_MAXSIZE == 16 regval |= OTG_DIEPCTL0_MPSIZ_16; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 32 +# elif CONFIG_USBDEV_EP0_MAXSIZE == 32 regval |= OTG_DIEPCTL0_MPSIZ_32; -#elif CONFIG_USBDEV_EP0_MAXSIZE == 64 +# elif CONFIG_USBDEV_EP0_MAXSIZE == 64 regval |= OTG_DIEPCTL0_MPSIZ_64; -#else -# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" -#endif +# else +# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" +# endif stm32_putreg(regval, STM32_OTG_DIEPCTL(0)); /* Clear global IN NAK */ - regval = stm32_getreg(STM32_OTG_DCTL); + regval = stm32_getreg(STM32_OTG_DCTL); regval |= OTG_DCTL_CGINAK; stm32_putreg(regval, STM32_OTG_DCTL); } @@ -1085,13 +1101,12 @@ static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv) /* Setup the hardware to perform the SETUP transfer */ regval = (USB_SIZEOF_CTRLREQ * 3 << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) | - (OTG_DOEPTSIZ0_PKTCNT) | - (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT); + (OTG_DOEPTSIZ0_PKTCNT) | (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT); stm32_putreg(regval, STM32_OTG_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); + regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); regval |= (OTG_DOEPCTL0_CNAK | OTG_DOEPCTL0_EPENA); stm32_putreg(regval, STM32_OTG_DOEPCTL(0)); } @@ -1105,7 +1120,7 @@ static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv) ****************************************************************************/ static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, - FAR uint8_t *buf, int nbytes) + FAR uint8_t * buf, int nbytes) { uint32_t regaddr; uint32_t regval; @@ -1128,10 +1143,10 @@ static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, * and pack these into one 32-bit word (little endian). */ - regval = (uint32_t)*buf++; - regval |= ((uint32_t)*buf++) << 8; - regval |= ((uint32_t)*buf++) << 16; - regval |= ((uint32_t)*buf++) << 24; + regval = (uint32_t) * buf++; + regval |= ((uint32_t) * buf++) << 8; + regval |= ((uint32_t) * buf++) << 16; + regval |= ((uint32_t) * buf++) << 24; /* Then write the packet data to the TxFIFO */ @@ -1148,7 +1163,7 @@ static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, ****************************************************************************/ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, - FAR uint8_t *buf, int nbytes) + FAR uint8_t * buf, int nbytes) { uint32_t pktcnt; uint32_t regval; @@ -1173,22 +1188,21 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, else { /* No.. Program the transfer size and packet count . First calculate: - * - * xfrsize = The total number of bytes to be sent. - * pktcnt = the number of packets (of maxpacket bytes) required to - * perform the transfer. + * xfrsize = The total number of bytes to be sent. pktcnt = the number of + * packets (of maxpacket bytes) required to perform the transfer. */ - pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = + ((uint32_t) nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; } /* Set the XFRSIZ and PKTCNT */ regval |= (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT); - regval |= ((uint32_t)nbytes << OTG_DIEPTSIZ_XFRSIZ_SHIFT); + regval |= ((uint32_t) nbytes << OTG_DIEPTSIZ_XFRSIZ_SHIFT); - /* If this is an isochronous endpoint, then set the multi-count field to - * the PKTCNT as well. + /* If this is an isochronous endpoint, then set the multi-count field to the + * PKTCNT as well. */ if (privep->eptype == USB_EP_ATTR_XFER_ISOC) @@ -1204,8 +1218,8 @@ static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, regval = stm32_getreg(STM32_OTG_DIEPCTL(privep->epphy)); - /* If this is an isochronous endpoint, then set the even/odd frame bit - * the DIEPCTLx register. + /* If this is an isochronous endpoint, then set the even/odd frame bit the + * DIEPCTLx register. */ if (privep->eptype == USB_EP_ATTR_XFER_ISOC) @@ -1258,22 +1272,17 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, int nwords; int bytesleft; - /* We get here in one of four possible ways. From three interrupting - * events: - * + /* We get here in one of four possible ways. From three interrupting events: * 1. From stm32_epin as part of the transfer complete interrupt processing - * This interrupt indicates that the last transfer has completed. - * 2. As part of the ITTXFE interrupt processing. That interrupt indicates - * that an IN token was received when the associated TxFIFO was empty. - * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing. - * The TXFE interrupt is only enabled when the TxFIFO is full and the - * software must wait for space to become available in the TxFIFO. - * - * And this function may be called immediately when the write request is - * queue to start up the next transaction. - * - * 4. From stm32_ep_submit when a new write request is received WHILE the - * endpoint is not active (privep->active == false). + * This interrupt indicates that the last transfer has completed. 2. As part of + * the ITTXFE interrupt processing. That interrupt indicates that an IN token + * was received when the associated TxFIFO was empty. 3. From + * stm32_epin_txfifoempty as part of the TXFE interrupt processing. The TXFE + * interrupt is only enabled when the TxFIFO is full and the software must wait + * for space to become available in the TxFIFO. And this function may be + * called immediately when the write request is queue to start up the next + * transaction. 4. From stm32_ep_submit when a new write request is received + * WHILE the endpoint is not active (privep->active == false). */ /* Check the request from the head of the endpoint request queue */ @@ -1283,14 +1292,14 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); - /* There is no TX transfer in progress and no new pending TX - * requests to send. To stop transmitting any data on a particular - * IN endpoint, the application must set the IN NAK bit. To set this - * bit, the following field must be programmed. + /* There is no TX transfer in progress and no new pending TX requests to + * send. To stop transmitting any data on a particular IN endpoint, the + * application must set the IN NAK bit. To set this bit, the following + * field must be programmed. */ regaddr = STM32_OTG_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTG_DIEPCTL_SNAK; stm32_putreg(regval, regaddr); @@ -1301,43 +1310,41 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, } uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n", - privep->epphy, privreq, privreq->req.len, - privreq->req.xfrd, privep->zlp); + privep->epphy, privreq, privreq->req.len, + privreq->req.xfrd, privep->zlp); - /* Check for a special case: If we are just starting a request (xfrd==0) and - * the class driver is trying to send a zero-length packet (len==0). Then set - * the ZLP flag so that the packet will be sent. + /* Check for a special case: If we are just starting a request (xfrd==0) and + * the class driver is trying to send a zero-length packet (len==0). Then + * set the ZLP flag so that the packet will be sent. */ if (privreq->req.len == 0) { - /* The ZLP flag is set TRUE whenever we want to force the driver to - * send a zero-length-packet on the next pass through the loop (below). - * The flag is cleared whenever a packet is sent in the loop below. + /* The ZLP flag is set TRUE whenever we want to force the driver to send + * a zero-length-packet on the next pass through the loop (below). The + * flag is cleared whenever a packet is sent in the loop below. */ - privep->zlp = true; + privep->zlp = true; } - /* Add one more packet to the TxFIFO. We will wait for the transfer - * complete event before we add the next packet (or part of a packet - * to the TxFIFO). - * - * The documentation says that we can can multiple packets to the TxFIFO, - * but it seems that we need to get the transfer complete event before - * we can add the next (or maybe I have got something wrong?) + /* Add one more packet to the TxFIFO. We will wait for the transfer complete + * event before we add the next packet (or part of a packet to the TxFIFO). + * The documentation says that we can can multiple packets to the TxFIFO, but + * it seems that we need to get the transfer complete event before we can add + * the next (or maybe I have got something wrong?) */ -#if 0 +# if 0 while (privreq->req.xfrd < privreq->req.len || privep->zlp) -#else +# else if (privreq->req.xfrd < privreq->req.len || privep->zlp) -#endif +# endif { /* Get the number of bytes left to be sent in the request */ bytesleft = privreq->req.len - privreq->req.xfrd; - nbytes = bytesleft; + nbytes = bytesleft; /* Assume no zero-length-packet on the next pass through this loop */ @@ -1349,28 +1356,27 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, if (nbytes > 0) { - /* Either send the maxpacketsize or all of the remaining data in - * the request. + /* Either send the maxpacketsize or all of the remaining data in the + * request. */ if (nbytes >= privep->ep.maxpacket) { - nbytes = privep->ep.maxpacket; + nbytes = privep->ep.maxpacket; /* Handle the case where this packet is exactly the - * maxpacketsize. Do we need to send a zero-length packet - * in this case? + * maxpacketsize. Do we need to send a zero-length packet in + * this case? */ - if (bytesleft == privep->ep.maxpacket && - (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) { - /* The ZLP flag is set TRUE whenever we want to force - * the driver to send a zero-length-packet on the next - * pass through this loop. The flag is cleared (above) - * whenever we are committed to sending any packet and - * set here when we want to force one more pass through - * the loop. + /* The ZLP flag is set TRUE whenever we want to force the + * driver to send a zero-length-packet on the next pass + * through this loop. The flag is cleared (above) whenever we + * are committed to sending any packet and set here when we + * want to force one more pass through the loop. */ privep->zlp = true; @@ -1382,27 +1388,24 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, nwords = (nbytes + 3) >> 2; - /* Get the number of 32-bit words available in the TxFIFO. The - * DXTFSTS indicates the amount of free space available in the - * endpoint TxFIFO. Values are in terms of 32-bit words: - * - * 0: Endpoint TxFIFO is full - * 1: 1 word available - * 2: 2 words available - * n: n words available + /* Get the number of 32-bit words available in the TxFIFO. The DXTFSTS + * indicates the amount of free space available in the endpoint TxFIFO. + * Values are in terms of 32-bit words: 0: Endpoint TxFIFO is full 1: 1 + * word available 2: 2 words available n: n words available */ regaddr = STM32_OTG_DTXFSTS(privep->epphy); /* Check for space in the TxFIFO. If space in the TxFIFO is not - * available, then set up an interrupt to resume the transfer when - * the TxFIFO is empty. + * available, then set up an interrupt to resume the transfer when the + * TxFIFO is empty. */ regval = stm32_getreg(regaddr); if ((int)(regval & OTG_DTXFSTS_MASK) < nwords) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), + (uint16_t) regval); /* There is insufficient space in the TxFIFO. Wait for a TxFIFO * empty interrupt and try again. @@ -1451,8 +1454,8 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, { usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - /* We are finished with the request (although the transfer has not - * yet completed). + /* We are finished with the request (although the transfer has not yet + * completed). */ stm32_req_complete(privep, OK); @@ -1468,13 +1471,13 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, ****************************************************************************/ static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, - FAR uint8_t *dest, uint16_t len) + FAR uint8_t * dest, uint16_t len) { uint32_t regaddr; int i; - /* Get the address of the RxFIFO. Note: there is only one RxFIFO so - * we might as well use the address associated with EP0. + /* Get the address of the RxFIFO. Note: there is only one RxFIFO so we might + * as well use the address associated with EP0. */ regaddr = STM32_OTG_DFIFO_DEP(EP0); @@ -1484,10 +1487,10 @@ static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, for (i = 0; i < len; i += 4) { union - { - uint32_t w; - uint8_t b[4]; - } data; + { + uint32_t w; + uint8_t b[4]; + } data; /* Read 1 x 32-bits of EP0 packet data */ @@ -1517,8 +1520,8 @@ static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len) uint32_t regaddr; int i; - /* Get the address of the RxFIFO Note: there is only one RxFIFO so - * we might as well use the address associated with EP0. + /* Get the address of the RxFIFO Note: there is only one RxFIFO so we + * might as well use the address associated with EP0. */ regaddr = STM32_OTG_DFIFO_DEP(EP0); @@ -1548,8 +1551,8 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, { struct stm32_req_s *privreq; - /* Since a transfer just completed, there must be a read request at the head of - * the endpoint request queue. + /* Since a transfer just completed, there must be a read request at the head + * of the endpoint request queue. */ privreq = stm32_rqpeek(privep); @@ -1567,7 +1570,7 @@ static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, } uinfo("EP%d: len=%d xfrd=%d\n", - privep->epphy, privreq->req.len, privreq->req.xfrd); + privep->epphy, privreq->req.len, privreq->req.xfrd); /* Return the completed read request to the class driver and mark the state * IDLE. @@ -1604,8 +1607,8 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) uinfo("EP0: bcnt=%d\n", bcnt); usbtrace(TRACE_READ(EP0), bcnt); - /* Verify that an OUT SETUP request as received before this data was - * received in the RxFIFO. + /* Verify that an OUT SETUP request as received before this data was received + * in the RxFIFO. */ if (priv->ep0state == EP0STATE_SETUP_OUT) @@ -1617,21 +1620,21 @@ static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) /* Do we have to discard any excess bytes? */ - stm32_rxfifo_discard(privep, bcnt - readlen); + stm32_rxfifo_discard(privep, bcnt - readlen); /* Now we can process the setup command */ - privep->active = false; - priv->ep0state = EP0STATE_SETUP_READY; + privep->active = false; + priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; stm32_ep0out_setup(priv); } else { - /* This is an error. We don't have any idea what to do with the EP0 - * data in this case. Just read and discard it so that the RxFIFO - * does not become constipated. + /* This is an error. We don't have any idea what to do with the EP0 data + * in this case. Just read and discard it so that the RxFIFO does not + * become constipated. */ usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); @@ -1666,11 +1669,10 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) { /* Incoming data is available in the RxFIFO, but there is no read setup * to receive the receive the data. This should not happen for data - * endpoints; those endpoints should have been NAKing any OUT data tokens. - * - * We should get here normally on OUT data phase following an OUT - * SETUP command. EP0 data will still receive data in this case and it - * should not be NAKing. + * endpoints; those endpoints should have been NAKing any OUT data + * tokens. We should get here normally on OUT data phase following an + * OUT SETUP command. EP0 data will still receive data in this case and + * it should not be NAKing. */ if (privep->epphy == 0) @@ -1694,12 +1696,13 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) return; } - uinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd); + uinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, + privreq->req.xfrd); usbtrace(TRACE_READ(privep->epphy), bcnt); /* Get the number of bytes to transfer from the RxFIFO */ - buflen = privreq->req.len - privreq->req.xfrd; + buflen = privreq->req.len - privreq->req.xfrd; DEBUGASSERT(buflen > 0 && buflen >= bcnt); readlen = MIN(buflen, bcnt); @@ -1741,8 +1744,8 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, uint32_t xfrsize; uint32_t pktcnt; - /* Make sure that there is not already a pending request request. If there is, - * just return, leaving the newly received request in the request queue. + /* Make sure that there is not already a pending request request. If there + * is, just return, leaving the newly received request in the request queue. */ if (!privep->active) @@ -1754,21 +1757,24 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, for (; ; ) { - /* Get a reference to the request at the head of the endpoint's request queue */ + /* Get a reference to the request at the head of the endpoint's + * request queue + */ privreq = stm32_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), + privep->epphy); - /* There are no read requests to be setup. Configure the hardware to - * NAK any incoming packets. (This should already be the case. I - * think that the hardware will automatically NAK after a transfer is - * completed until SNAK is cleared). + /* There are no read requests to be setup. Configure the + * hardware to NAK any incoming packets. (This should already be + * the case. I think that the hardware will automatically NAK + * after a transfer is completed until SNAK is cleared). */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTG_DOEPCTL_SNAK; stm32_putreg(regval, regaddr); @@ -1799,35 +1805,34 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, } /* Setup the pending read into the request buffer. First calculate: - * - * pktcnt = the number of packets (of maxpacket bytes) required to - * perform the transfer. - * xfrsize = The total number of bytes required (in units of - * maxpacket bytes). + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. xfrsize = The total number of bytes required (in + * units of maxpacket bytes). */ - pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + pktcnt = + (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; xfrsize = pktcnt * privep->ep.maxpacket; /* Then setup the hardware to perform this transfer */ regaddr = STM32_OTG_DOEPTSIZ(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~(OTG_DOEPTSIZ_XFRSIZ_MASK | OTG_DOEPTSIZ_PKTCNT_MASK); regval |= (xfrsize << OTG_DOEPTSIZ_XFRSIZ_SHIFT); - regval |= (pktcnt << OTG_DOEPTSIZ_PKTCNT_SHIFT); + regval |= (pktcnt << OTG_DOEPTSIZ_PKTCNT_SHIFT); stm32_putreg(regval, regaddr); /* Then enable the transfer */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); /* When an isochronous transfer is enabled the Even/Odd frame bit must * also be set appropriately. */ -#ifdef CONFIG_USBDEV_ISOCHRONOUS +# ifdef CONFIG_USBDEV_ISOCHRONOUS if (privep->eptype == USB_EP_ATTR_XFER_ISOC) { if (privep->odd) @@ -1839,7 +1844,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, regval |= OTG_DOEPCTL_SEVNFRM; } } -#endif +# endif /* Clearing NAKing and enable the transfer. */ @@ -1850,8 +1855,8 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, privep->active = true; - /* EP0 is a special case. We need to know when to switch back to - * normal SETUP processing. + /* EP0 is a special case. We need to know when to switch back to normal + * SETUP processing. */ if (privep->epphy == EP0) @@ -1898,8 +1903,8 @@ static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) privreq = stm32_req_remfirst(privep); DEBUGASSERT(privreq != NULL); - /* If endpoint 0, temporarily reflect the state of protocol stalled - * in the callback. + /* If endpoint 0, temporarily reflect the state of protocol stalled in the + * callback. */ bool stalled = privep->stalled; @@ -1938,8 +1943,7 @@ static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) while (!stm32_rqempty(privep)) { - usbtrace(TRACE_COMPLETE(privep->epphy), - (stm32_rqpeek(privep))->req.xfrd); + usbtrace(TRACE_COMPLETE(privep->epphy), (stm32_rqpeek(privep))->req.xfrd); stm32_req_complete(privep, status); } } @@ -2039,8 +2043,8 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(EP0)); - /* Tell the class driver that we are disconnected. The class - * driver should then accept any new configurations. + /* Tell the class driver that we are disconnected. The class driver should + * then accept any new configurations. */ if (priv->driver) @@ -2055,7 +2059,7 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) /* Disable all end point interrupts */ - for (i = 0; i < STM32_NENDPOINTS ; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Disable endpoint interrupts */ @@ -2102,7 +2106,11 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; +# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) + priv->usbdev.speed = USB_SPEED_HIGH; +# else priv->usbdev.speed = USB_SPEED_FULL; +# endif /* Re-configure EP0 */ @@ -2151,9 +2159,9 @@ static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, default: usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); - priv->dotest = false; + priv->dotest = false; priv->testmode = OTG_TESTMODE_DISABLED; - priv->stalled = true; + priv->stalled = true; } priv->dotest = true; @@ -2180,17 +2188,14 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { case USB_REQ_GETSTATUS: { - /* type: device-to-host; recipient = device, interface, endpoint - * value: 0 - * index: zero interface endpoint - * len: 2; data = status + /* type: device-to-host; recipient = device, interface, endpoint value: + * 0 index: zero interface endpoint len: 2; data = status */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); if (!priv->addressed || - ctrlreq->len != 2 || - USB_REQ_ISOUT(ctrlreq->type) || - ctrlreq->value != 0) + ctrlreq->len != 2 || + USB_REQ_ISOUT(ctrlreq->type) || ctrlreq->value != 0) { priv->stalled = true; } @@ -2204,7 +2209,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, privep = stm32_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), + 0); priv->stalled = true; } else @@ -2228,19 +2234,23 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, { if (ctrlreq->index == 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), + 0); - /* Features: Remote Wakeup and self-powered */ + /* Features: Remote Wakeup and self-powered */ - priv->ep0data[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED); - priv->ep0data[0] |= (priv->wakeup << USB_FEATURE_REMOTEWAKEUP); - priv->ep0data[1] = 0; + priv->ep0data[0] = + (priv->selfpowered << USB_FEATURE_SELFPOWERED); + priv->ep0data[0] |= + (priv->wakeup << USB_FEATURE_REMOTEWAKEUP); + priv->ep0data[1] = 0; stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } else { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), + 0); priv->stalled = true; } } @@ -2269,10 +2279,9 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, case USB_REQ_CLEARFEATURE: { - /* type: host-to-device; recipient = device, interface or endpoint - * value: feature selector - * index: zero interface endpoint; - * len: zero, data = none + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector index: zero interface endpoint; len: zero, + * data = none */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); @@ -2309,10 +2318,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, case USB_REQ_SETFEATURE: { - /* type: host-to-device; recipient = device, interface, endpoint - * value: feature selector - * index: zero interface endpoint; - * len: 0; data = none + /* type: host-to-device; recipient = device, interface, endpoint value: + * feature selector index: zero interface endpoint; len: 0; data = none */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); @@ -2336,7 +2343,7 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, ctrlreq->value == USB_FEATURE_TESTMODE && ((ctrlreq->index & 0xff) == 0)) { - stm32_ep0out_testmode(priv, ctrlreq->index); + stm32_ep0out_testmode(priv, ctrlreq->index); } else if (priv->configured) { @@ -2360,24 +2367,20 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, case USB_REQ_SETADDRESS: { - /* type: host-to-device; recipient = device - * value: device address - * index: 0 - * len: 0; data = none + /* type: host-to-device; recipient = device value: device address + * index: 0 len: 0; data = none */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->index == 0 && - ctrlreq->len == 0 && - ctrlreq->value < 128 && - priv->devstate != DEVSTATE_CONFIGURED) + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE + && ctrlreq->index == 0 && ctrlreq->len == 0 && ctrlreq->value < 128 + && priv->devstate != DEVSTATE_CONFIGURED) { - /* Save the address. We cannot actually change to the next address until - * the completion of the status phase. + /* Save the address. We cannot actually change to the next address + * until the completion of the status phase. */ - stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_setaddress(priv, (uint16_t) priv->ctrlreq.value[0]); stm32_ep0in_transmitzlp(priv); } else @@ -2389,22 +2392,22 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, break; case USB_REQ_GETDESCRIPTOR: - /* type: device-to-host; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor + /* type: device-to-host; recipient = device, interface value: descriptor + * type and index index: 0 or language ID; len: descriptor len; data = + * descriptor */ case USB_REQ_SETDESCRIPTOR: - /* type: host-to-device; recipient = device - * value: descriptor type and index - * index: 0 or language ID; - * len: descriptor len; data = descriptor + /* type: host-to-device; recipient = device value: descriptor type and + * index index: 0 or language ID; len: descriptor len; data = descriptor */ { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); - if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + if (((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) || + ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_INTERFACE)) { (void)stm32_req_dispatch(priv, &priv->ctrlreq); } @@ -2417,19 +2420,15 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, break; case USB_REQ_GETCONFIGURATION: - /* type: device-to-host; recipient = device - * value: 0; - * index: 0; - * len: 1; data = configuration value + /* type: device-to-host; recipient = device value: 0; index: 0; len: 1; + * data = configuration value */ { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->value == 0 && - ctrlreq->index == 0 && - ctrlreq->len == 1) + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE + && ctrlreq->value == 0 && ctrlreq->index == 0 && ctrlreq->len == 1) { (void)stm32_req_dispatch(priv, &priv->ctrlreq); } @@ -2442,18 +2441,15 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, break; case USB_REQ_SETCONFIGURATION: - /* type: host-to-device; recipient = device - * value: configuration value - * index: 0; - * len: 0; data = none + /* type: host-to-device; recipient = device value: configuration value + * index: 0; len: 0; data = none */ { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && - (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && - ctrlreq->index == 0 && - ctrlreq->len == 0) + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE + && ctrlreq->index == 0 && ctrlreq->len == 0) { /* Give the configuration to the class driver */ @@ -2466,15 +2462,15 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, if (ret == OK) { - uint8_t cfg = (uint8_t)ctrlreq->value; + uint8_t cfg = (uint8_t) ctrlreq->value; if (cfg != 0) { - priv->devstate = DEVSTATE_CONFIGURED; + priv->devstate = DEVSTATE_CONFIGURED; priv->configured = true; } else { - priv->devstate = DEVSTATE_ADDRESSED; + priv->devstate = DEVSTATE_ADDRESSED; priv->configured = false; } } @@ -2488,17 +2484,13 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, break; case USB_REQ_GETINTERFACE: - /* type: device-to-host; recipient = interface - * value: 0 - * index: interface; - * len: 1; data = alt interface + /* type: device-to-host; recipient = interface value: 0 index: interface; + * len: 1; data = alt interface */ case USB_REQ_SETINTERFACE: - /* type: host-to-device; recipient = interface - * value: alternate setting - * index: interface; - * len: 0; data = none + /* type: host-to-device; recipient = interface value: alternate setting + * index: interface; len: 0; data = none */ { @@ -2508,10 +2500,8 @@ static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, break; case USB_REQ_SYNCHFRAME: - /* type: device-to-host; recipient = endpoint - * value: 0 - * index: endpoint; - * len: 2; data = frame number + /* type: device-to-host; recipient = endpoint value: 0 index: endpoint; + * len: 2; data = frame number */ { @@ -2552,7 +2542,7 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) /* Terminate any pending requests */ stm32_req_cancel(&priv->epout[EP0], -EPROTO); - stm32_req_cancel(&priv->epin[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); /* Assume NOT stalled */ @@ -2566,14 +2556,14 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) /* And extract the little-endian 16-bit values to host order */ - ctrlreq.type = priv->ctrlreq.type; - ctrlreq.req = priv->ctrlreq.req; + ctrlreq.type = priv->ctrlreq.type; + ctrlreq.req = priv->ctrlreq.req; ctrlreq.value = GETUINT16(priv->ctrlreq.value); ctrlreq.index = GETUINT16(priv->ctrlreq.index); - ctrlreq.len = GETUINT16(priv->ctrlreq.len); + ctrlreq.len = GETUINT16(priv->ctrlreq.len); uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", - ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len); + ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len); /* Check for a standard request */ @@ -2600,7 +2590,7 @@ static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) /* Reset state/data associated with thie SETUP request */ - priv->ep0datlen = 0; + priv->ep0datlen = 0; } /**************************************************************************** @@ -2622,9 +2612,8 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) { privep = &priv->epout[EP0]; - /* In the EP0STATE_DATA_OUT state, we are receiving data into the - * request buffer. In that case, we must continue the request - * processing. + /* In the EP0STATE_DATA_OUT state, we are receiving data into the request + * buffer. In that case, we must continue the request processing. */ if (priv->ep0state == EP0STATE_DATA_OUT) @@ -2633,8 +2622,8 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) stm32_epout_complete(priv, privep); - /* If we are not actively processing an OUT request, then we - * need to setup to receive the next control request. + /* If we are not actively processing an OUT request, then we need to + * setup to receive the next control request. */ if (!privep->active) @@ -2645,8 +2634,8 @@ static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) } } - /* For other endpoints, the only possibility is that we are continuing - * or finishing an OUT request. + /* For other endpoints, the only possibility is that we are continuing or + * finishing an OUT request. */ else if (priv->devstate == DEVSTATE_CONFIGURED) @@ -2679,27 +2668,26 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) * interrupt status register. */ - regval = stm32_getreg(STM32_OTG_DAINT); + regval = stm32_getreg(STM32_OTG_DAINT); regval &= stm32_getreg(STM32_OTG_DAINTMSK); - daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; + daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; if (daint == 0) { - /* We got an interrupt, but there is no unmasked endpoint that caused - * it ?! When this happens, the interrupt flag never gets cleared and - * we are stuck in infinite interrupt loop. - * - * This shouldn't happen if we are diligent about handling timing - * issues when masking endpoint interrupts. However, this workaround - * avoids infinite loop and allows operation to continue normally. It - * works by clearing each endpoint flags, masked or not. + /* We got an interrupt, but there is no unmasked endpoint that caused it + * ?! When this happens, the interrupt flag never gets cleared and we are + * stuck in infinite interrupt loop. This shouldn't happen if we are + * diligent about handling timing issues when masking endpoint + * interrupts. However, this workaround avoids infinite loop and allows + * operation to continue normally. It works by clearing each endpoint + * flags, masked or not. */ - regval = stm32_getreg(STM32_OTG_DAINT); - daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; + regval = stm32_getreg(STM32_OTG_DAINT); + daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), - (uint16_t)regval); + (uint16_t) regval); epno = 0; while (daint) @@ -2708,7 +2696,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) { regval = stm32_getreg(STM32_OTG_DOEPINT(epno)); uerr("DOEPINT(%d) = %08x\n", epno, regval); - stm32_putreg(0xFF, STM32_OTG_DOEPINT(epno)); + stm32_putreg(0xff, STM32_OTG_DOEPINT(epno)); } epno++; @@ -2729,18 +2717,19 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) { /* Yes.. get the OUT endpoint interrupt status */ - doepint = stm32_getreg(STM32_OTG_DOEPINT(epno)); + doepint = stm32_getreg(STM32_OTG_DOEPINT(epno)); doepint &= stm32_getreg(STM32_OTG_DOEPMSK); /* Transfer completed interrupt. This interrupt is trigged when * stm32_rxinterrupt() removes the last packet data from the RxFIFO. - * In this case, core internally sets the NAK bit for this endpoint to - * prevent it from receiving any more packets. + * In this case, core internally sets the NAK bit for this endpoint + * to prevent it from receiving any more packets. */ if ((doepint & OTG_DOEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), + (uint16_t) doepint); /* Clear the bit in DOEPINTn for this interrupt */ @@ -2754,26 +2743,29 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) /* Endpoint disabled interrupt (ignored because this interrupt is * used in polled mode by the endpoint disable logic). */ -#if 1 +# if 1 /* REVISIT: */ + if ((doepint & OTG_DOEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), + (uint16_t) doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(epno)); } -#endif +# endif /* Setup Phase Done (control EPs) */ if ((doepint & OTG_DOEPINT_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), + priv->ep0state); /* Handle the receipt of the IN SETUP packets now (OUT setup - * packet processing may be delayed until the accompanying - * OUT DATA is received) + * packet processing may be delayed until the accompanying OUT + * DATA is received) */ if (priv->ep0state == EP0STATE_SETUP_READY) @@ -2801,8 +2793,8 @@ static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv) { uint32_t regval = stm32_getreg(STM32_OTG_DCTL); regval &= OTG_DCTL_TCTL_MASK; - regval |= (uint32_t)priv->testmode << OTG_DCTL_TCTL_SHIFT; - stm32_putreg(regval , STM32_OTG_DCTL); + regval |= (uint32_t) priv->testmode << OTG_DCTL_TCTL_SHIFT; + stm32_putreg(regval, STM32_OTG_DCTL); priv->dotest = 0; priv->testmode = OTG_TESTMODE_DISABLED; @@ -2826,7 +2818,7 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) if (epno == 0) { /* In the EP0STATE_DATA_IN state, we are sending data from request - * buffer. In that case, we must continue the request processing. + * buffer. In that case, we must continue the request processing */ if (priv->ep0state == EP0STATE_DATA_IN) @@ -2835,8 +2827,8 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) stm32_epin_request(priv, privep); - /* If we are not actively processing an OUT request, then we - * need to setup to receive the next control request. + /* If we are not actively processing an OUT request, then we need to + * setup to receive the next control request. */ if (!privep->active) @@ -2854,8 +2846,8 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) } } - /* For other endpoints, the only possibility is that we are continuing - * or finishing an IN request. + /* For other endpoints, the only possibility is that we are continuing or + * finishing an IN request. */ else if (priv->devstate == DEVSTATE_CONFIGURED) @@ -2874,13 +2866,14 @@ static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) * ****************************************************************************/ -static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno) +static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, + int epno) { FAR struct stm32_ep_s *privep = &priv->epin[epno]; - /* Continue processing the write request queue. This may mean sending - * more data from the existing request or terminating the current requests - * and (perhaps) starting the IN transfer from the next write request. + /* Continue processing the write request queue. This may mean sending more + * data from the existing request or terminating the current requests and + * (perhaps) starting the IN transfer from the next write request. */ stm32_epin_request(priv, privep); @@ -2910,25 +2903,23 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) * interrupt status register. */ - daint = stm32_getreg(STM32_OTG_DAINT); + daint = stm32_getreg(STM32_OTG_DAINT); daint &= stm32_getreg(STM32_OTG_DAINTMSK); daint &= OTG_DAINT_IEP_MASK; if (daint == 0) { - /* We got an interrupt, but there is no unmasked endpoint that caused - * it ?! When this happens, the interrupt flag never gets cleared and - * we are stuck in infinite interrupt loop. - * - * This shouldn't happen if we are diligent about handling timing - * issues when masking endpoint interrupts. However, this workaround - * avoids infinite loop and allows operation to continue normally. It - * works by clearing each endpoint flags, masked or not. + /* We got an interrupt, but there is no unmasked endpoint that caused it + * ?! When this happens, the interrupt flag never gets cleared and we are + * stuck in infinite interrupt loop. This shouldn't happen if we are + * diligent about handling timing issues when masking endpoint + * interrupts. However, this workaround avoids infinite loop and allows + * operation to continue normally. It works by clearing each endpoint + * flags, masked or not. */ - daint = stm32_getreg(STM32_OTG_DAINT); - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), - (uint16_t)daint); + daint = stm32_getreg(STM32_OTG_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t) daint); daint &= OTG_DAINT_IEP_MASK; epno = 0; @@ -2938,8 +2929,8 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) if ((daint & 1) != 0) { uerr("DIEPINT(%d) = %08x\n", - epno, stm32_getreg(STM32_OTG_DIEPINT(epno))); - stm32_putreg(0xFF, STM32_OTG_DIEPINT(epno)); + epno, stm32_getreg(STM32_OTG_DIEPINT(epno))); + stm32_putreg(0xff, STM32_OTG_DIEPINT(epno)); } epno++; @@ -2966,10 +2957,10 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) mask = stm32_getreg(STM32_OTG_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this - * endpoint in the DIEPMSK register. Bits n corresponds to - * endpoint n in the register. That condition corresponds to - * bit 7 of the DIEPINT interrupt status register. There is - * no TXFE bit in the mask register, so we fake one here. + * endpoint in the DIEPMSK register. Bits n corresponds to endpoint + * n in the register. That condition corresponds to bit 7 of the + * DIEPINT interrupt status register. There is no TXFE bit in the + * mask register, so we fake one here. */ empty = stm32_getreg(STM32_OTG_DIEPEMPMSK); @@ -2990,12 +2981,12 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) if ((diepint & OTG_DIEPINT_XFRC) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), - (uint16_t)diepint); + (uint16_t) diepint); - /* It is possible that logic may be waiting for a the - * TxFIFO to become empty. We disable the TxFIFO empty - * interrupt here; it will be re-enabled if there is still - * insufficient space in the TxFIFO. + /* It is possible that logic may be waiting for a the TxFIFO to + * become empty. We disable the TxFIFO empty interrupt here; it + * will be re-enabled if there is still insufficient space in the + * TxFIFO. */ empty &= ~OTG_DIEPEMPMSK(epno); @@ -3011,20 +3002,22 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) if ((diepint & OTG_DIEPINT_TOC) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), + (uint16_t) diepint); stm32_putreg(OTG_DIEPINT_TOC, STM32_OTG_DIEPINT(epno)); } - /* IN token received when TxFIFO is empty. Applies to non-periodic IN - * endpoints only. This interrupt indicates that an IN token was received - * when the associated TxFIFO (periodic/non-periodic) was empty. This - * interrupt is asserted on the endpoint for which the IN token was - * received. + /* IN token received when TxFIFO is empty. Applies to non-periodic + * IN endpoints only. This interrupt indicates that an IN token was + * received when the associated TxFIFO (periodic/non-periodic) was + * empty. This interrupt is asserted on the endpoint for which the IN + * token was received. */ if ((diepint & OTG_DIEPINT_ITTXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), + (uint16_t) diepint); stm32_epin_request(priv, &priv->epin[epno]); stm32_putreg(OTG_DIEPINT_ITTXFE, STM32_OTG_DIEPINT(epno)); } @@ -3032,38 +3025,42 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) /* IN endpoint NAK effective (ignored as this used only in polled * mode) */ -#if 0 +# if 0 if ((diepint & OTG_DIEPINT_INEPNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), + (uint16_t) diepint); stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(epno)); } -#endif +# endif /* Endpoint disabled interrupt (ignored as this used only in polled * mode) */ -#if 0 +# if 0 if ((diepint & OTG_DIEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), + (uint16_t) diepint); stm32_putreg(OTG_DIEPINT_EPDISD, STM32_OTG_DIEPINT(epno)); } -#endif +# endif /* Transmit FIFO empty */ if ((diepint & OTG_DIEPINT_TXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), + (uint16_t) diepint); - /* If we were waiting for TxFIFO to become empty, the we might have both - * XFRC and TXFE interrupts pending. Since we do the same thing for both - * cases, ignore the TXFE if we have already processed the XFRC. + /* If we were waiting for TxFIFO to become empty, the we might + * have both XFRC and TXFE interrupts pending. Since we do the + * same thing for both cases, ignore the TXFE if we have already + * processed the XFRC. */ if ((diepint & OTG_DIEPINT_XFRC) == 0) { - /* Mask further FIFO empty interrupts. This will be re-enabled - * whenever we need to wait for a FIFO event. + /* Mask further FIFO empty interrupts. This will be + * re-enabled whenever we need to wait for a FIFO event. */ empty &= ~OTG_DIEPEMPMSK(epno); @@ -3099,15 +3096,15 @@ static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv) /* Restart the PHY clock and un-gate USB core clock (HCLK) */ -#ifdef CONFIG_USBDEV_LOWPOWER +# ifdef CONFIG_USBDEV_LOWPOWER regval = stm32_getreg(STM32_OTG_PCGCCTL); regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK); stm32_putreg(regval, STM32_OTG_PCGCCTL); -#endif +# endif /* Clear remote wake-up signaling */ - regval = stm32_getreg(STM32_OTG_DCTL); + regval = stm32_getreg(STM32_OTG_DCTL); regval &= ~OTG_DCTL_RWUSIG; stm32_putreg(regval, STM32_OTG_DCTL); @@ -3133,9 +3130,9 @@ static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv) static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv) { -#ifdef CONFIG_USBDEV_LOWPOWER +# ifdef CONFIG_USBDEV_LOWPOWER uint32_t regval; -#endif +# endif /* Notify the class driver of the suspend event */ @@ -3144,9 +3141,9 @@ static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv) CLASS_SUSPEND(priv->driver, &priv->usbdev); } -#ifdef CONFIG_USBDEV_LOWPOWER - /* OTG_DSTS_SUSPSTS is set as long as the suspend condition is detected - * on USB. Check if we are still have the suspend condition, that we are +# ifdef CONFIG_USBDEV_LOWPOWER + /* OTG_DSTS_SUSPSTS is set as long as the suspend condition is detected on + * USB. Check if we are still have the suspend condition, that we are * connected to the host, and that we have been configured. */ @@ -3154,26 +3151,24 @@ static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv) if ((regval & OTG_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) { - /* Switch off OTG clocking. Setting OTG_PCGCCTL_STPPCLK stops the - * PHY clock. + /* Switch off OTG clocking. Setting OTG_PCGCCTL_STPPCLK stops the PHY + * clock. */ regval = stm32_getreg(STM32_OTG_PCGCCTL); regval |= OTG_PCGCCTL_STPPCLK; stm32_putreg(regval, STM32_OTG_PCGCCTL); - /* Setting OTG_PCGCCTL_GATEHCLK gate HCLK to modules other than - * the AHB Slave and Master and wakeup logic. + /* Setting OTG_PCGCCTL_GATEHCLK gate HCLK to modules other than the AHB + * Slave and Master and wakeup logic. */ regval |= OTG_PCGCCTL_GATEHCLK; stm32_putreg(regval, STM32_OTG_PCGCCTL); } -#endif +# endif - /* Let the board-specific logic know that we have entered the suspend - * state - */ + /* Let the board-specific logic know that we have entered the suspend state */ stm32_usbsuspend((FAR struct usbdev_s *)priv, false); } @@ -3200,7 +3195,7 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) /* Decode status fields */ - epphy = (regval & OTG_GRXSTSD_EPNUM_MASK) >> OTG_GRXSTSD_EPNUM_SHIFT; + epphy = (regval & OTG_GRXSTSD_EPNUM_MASK) >> OTG_GRXSTSD_EPNUM_SHIFT; if (epphy < STM32_NENDPOINTS) { @@ -3210,12 +3205,10 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) switch (regval & OTG_GRXSTSD_PKTSTS_MASK) { - /* Global OUT NAK. This indicate that the global OUT NAK bit has taken - * effect. - * - * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't - * Care. - */ + /* Global OUT NAK. This indicate that the global OUT NAK bit has + * taken effect. PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't + * Care, DPID = Don't Care. + */ case OTG_GRXSTSD_PKTSTS_OUTNAK: { @@ -3223,11 +3216,10 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } break; - /* OUT data packet received. - * - * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, - * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID. - */ + /* OUT data packet received. PKTSTS = DataOUT, BCNT = size of the + * received data OUT packet, EPNUM = EPNUM on which the packet was + * received, DPID = Actual Data PID. + */ case OTG_GRXSTSD_PKTSTS_OUTRECVD: { @@ -3240,14 +3232,13 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } break; - /* OUT transfer completed. This indicates that an OUT data transfer for - * the specified OUT endpoint has completed. After this entry is popped - * from the receive FIFO, the core asserts a Transfer Completed interrupt - * on the specified OUT endpoint. - * - * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on - * which the data transfer is complete, DPID = Don't Care. - */ + /* OUT transfer completed. This indicates that an OUT data transfer + * for the specified OUT endpoint has completed. After this entry is + * popped from the receive FIFO, the core asserts a Transfer + * Completed interrupt on the specified OUT endpoint. PKTSTS = Data + * OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on which the data + * transfer is complete, DPID = Don't Care. + */ case OTG_GRXSTSD_PKTSTS_OUTDONE: { @@ -3255,43 +3246,39 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) } break; - /* SETUP transaction completed. This indicates that the Setup stage for - * the specified endpoint has completed and the Data stage has started. - * After this entry is popped from the receive FIFO, the core asserts a - * Setup interrupt on the specified control OUT endpoint (triggers an - * interrupt). - * - * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, - * DPID = Don't Care. - */ + /* SETUP transaction completed. This indicates that the Setup stage + * for the specified endpoint has completed and the Data stage has + * started. After this entry is popped from the receive FIFO, the + * core asserts a Setup interrupt on the specified control OUT + * endpoint (triggers an interrupt). PKTSTS = Setup Stage Done, BCNT + * = 0, EPNUM = Control EP Num, DPID = Don't Care. + */ case OTG_GRXSTSD_PKTSTS_SETUPDONE: { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); - /* Now that the Setup Phase is complete if it was an OUT enable - * the endpoint - * (Doing this here prevents the loss of the first FIFO word) + /* Now that the Setup Phase is complete if it was an OUT enable the + * endpoint (Doing this here prevents the loss of the first FIFO + * word) */ if (priv->ep0state == EP0STATE_SETUP_OUT) { - /* Clear NAKSTS so that we can receive the data */ - regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); + regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); regval |= OTG_DOEPCTL0_CNAK; stm32_putreg(regval, STM32_OTG_DOEPCTL(0)); - - } + } } break; - /* SETUP data packet received. This indicates that a SETUP packet for the - * specified endpoint is now available for reading from the receive FIFO. - * - * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. - */ + /* SETUP data packet received. This indicates that a SETUP packet + * for the specified endpoint is now available for reading from the + * receive FIFO. PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, + * DPID = D0. + */ case OTG_GRXSTSD_PKTSTS_SETUPRECVD: { @@ -3299,20 +3286,20 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); - /* Read EP0 setup data. NOTE: If multiple SETUP packets are received, - * the last one overwrites the previous setup packets and only that - * last SETUP packet will be processed. + /* Read EP0 setup data. NOTE: If multiple SETUP packets are + * received, the last one overwrites the previous setup packets and + * only that last SETUP packet will be processed. */ - stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq, - USB_SIZEOF_CTRLREQ); + stm32_rxfifo_read(&priv->epout[EP0], + (FAR uint8_t *) & priv->ctrlreq, + USB_SIZEOF_CTRLREQ); /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP, * then we need to wait for the completion of the data phase to - * process the setup command. If it is an IN SETUP packet, then - * we must processing the command BEFORE we enter the DATA phase. - * - * If the data associated with the OUT SETUP packet is zero length, + * process the setup command. If it is an IN SETUP packet, then we + * must processing the command BEFORE we enter the DATA phase. If + * the data associated with the OUT SETUP packet is zero length, * then, of course, we don't need to wait. */ @@ -3335,12 +3322,12 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) default: { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), - (regval & OTG_GRXSTSD_PKTSTS_MASK) >> OTG_GRXSTSD_PKTSTS_SHIFT); + (regval & OTG_GRXSTSD_PKTSTS_MASK) >> + OTG_GRXSTSD_PKTSTS_SHIFT); } break; } } - } /**************************************************************************** @@ -3359,11 +3346,17 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv) stm32_ep0in_activate(); - /* Set USB turn-around time for the full speed device with internal PHY interface. */ + /* Set USB turn-around time for the full speed device with internal PHY + * interface. + */ - regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; - regval |= OTG_GUSBCFG_TRDT(6); +# ifdef CONFIG_STM32F7_OTGFSHS + regval |= OTG_GUSBCFG_TRDT(9); +# else + regval |= OTG_GUSBCFG_TRDT(6); +# endif stm32_putreg(regval, STM32_OTG_GUSBCFG); } @@ -3377,13 +3370,14 @@ static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_USBDEV_ISOCHRONOUS +# ifdef CONFIG_USBDEV_ISOCHRONOUS static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) { int i; - /* The application must read the endpoint control register for all isochronous - * IN endpoints to detect endpoints with incomplete IN data transfers. + /* The application must read the endpoint control register for all + * isochronous IN endpoints to detect endpoints with incomplete IN data + * transfers. */ for (i = 0; i < STM32_NENDPOINTS; i++) @@ -3411,10 +3405,10 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) regaddr = STM32_OTG_DIEPCTL(privep->epphy); doepctl = stm32_getreg(regaddr); - dsts = stm32_getreg(STM32_OTG_DSTS); + dsts = stm32_getreg(STM32_OTG_DSTS); - /* EONUM = 0:even frame, 1:odd frame - * SOFFN = Frame number of the received SOF + /* EONUM = 0:even frame, 1:odd frame SOFFN = Frame number of the received + * SOF */ eonum = ((doepctl & OTG_DIEPCTL_EONUM) != 0); @@ -3427,18 +3421,18 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) continue; } - /* For isochronous IN endpoints with incomplete transfers, - * the application must discard the data in the memory and - * disable the endpoint. + /* For isochronous IN endpoints with incomplete transfers, the + * application must discard the data in the memory and disable the + * endpoint. */ stm32_req_complete(privep, -EIO); -#warning "Will clear OTG_DIEPCTL_USBAEP too" +# warning "Will clear OTG_DIEPCTL_USBAEP too" stm32_epin_disable(privep); break; } } -#endif +# endif /**************************************************************************** * Name: stm32_isocoutinterrupt @@ -3448,7 +3442,7 @@ static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_USBDEV_ISOCHRONOUS +# ifdef CONFIG_USBDEV_ISOCHRONOUS static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) { FAR struct stm32_ep_s *privep; @@ -3463,9 +3457,7 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) * control registers of all isochronous OUT endpoints to determine which * endpoints had an incomplete transfer in the current microframe. An * endpoint transfer is incomplete if both the following conditions are true: - * - * DOEPCTLx:EONUM = DSTS:SOFFN[0], and - * DOEPCTLx:EPENA = 1 + * DOEPCTLx:EONUM = DSTS:SOFFN[0], and DOEPCTLx:EPENA = 1 */ for (i = 0; i < STM32_NENDPOINTS; i++) @@ -3493,10 +3485,10 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) regaddr = STM32_OTG_DOEPCTL(privep->epphy); doepctl = stm32_getreg(regaddr); - dsts = stm32_getreg(STM32_OTG_DSTS); + dsts = stm32_getreg(STM32_OTG_DSTS); - /* EONUM = 0:even frame, 1:odd frame - * SOFFN = Frame number of the received SOF + /* EONUM = 0:even frame, 1:odd frame SOFFN = Frame number of the received + * SOF */ eonum = ((doepctl & OTG_DOEPCTL_EONUM) != 0); @@ -3509,18 +3501,18 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) continue; } - /* For isochronous OUT endpoints with incomplete transfers, - * the application must discard the data in the memory and - * disable the endpoint. + /* For isochronous OUT endpoints with incomplete transfers, the + * application must discard the data in the memory and disable the + * endpoint. */ stm32_req_complete(privep, -EIO); -#warning "Will clear OTG_DOEPCTL_USBAEP too" +# warning "Will clear OTG_DOEPCTL_USBAEP too" stm32_epout_disable(privep); break; } } -#endif +# endif /**************************************************************************** * Name: stm32_sessioninterrupt @@ -3530,12 +3522,12 @@ static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_USBDEV_VBUSSENSING +# ifdef CONFIG_USBDEV_VBUSSENSING static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv) { -#warning "Missing logic" +# warning "Missing logic" } -#endif +# endif /**************************************************************************** * Name: stm32_otginterrupt @@ -3545,7 +3537,7 @@ static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_USBDEV_VBUSSENSING +# ifdef CONFIG_USBDEV_VBUSSENSING static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) { uint32_t regval; @@ -3555,14 +3547,14 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GOTGINT); if ((regval & OTG_GOTGINT_SEDET) != 0) { -#warning "Missing logic" +# warning "Missing logic" } /* Clear OTG interrupt */ stm32_putreg(regval, STM32_OTG_GOTGINT); } -#endif +# endif /**************************************************************************** * Name: stm32_usbinterrupt @@ -3574,7 +3566,7 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) { - /* At present, there is only a single OTG device support. Hence it is + /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the * global data) in order to simplify any future support for multiple devices. @@ -3588,36 +3580,36 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) /* Assure that we are in device mode */ - DEBUGASSERT((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINTSTS_CMOD) == OTG_GINTSTS_DEVMODE); + DEBUGASSERT((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINTSTS_CMOD) == + OTG_GINTSTS_DEVMODE); - /* Get the state of all enabled interrupts. We will do this repeatedly - * some interrupts (like RXFLVL) will generate additional interrupting - * events. + /* Get the state of all enabled interrupts. We will do this repeatedly some + * interrupts (like RXFLVL) will generate additional interrupting events. */ for (; ; ) { /* Get the set of pending, un-masked interrupts */ - regval = stm32_getreg(STM32_OTG_GINTSTS); + regval = stm32_getreg(STM32_OTG_GINTSTS); reserved = (regval & OTG_GINT_RESERVED); regval &= stm32_getreg(STM32_OTG_GINTMSK); - /* With out modifying the reserved bits, acknowledge all - * **Writable** pending irqs we will service below + /* With out modifying the reserved bits, acknowledge all **Writable** + * pending irqs we will service below. */ stm32_putreg(((regval | reserved) & OTG_GINT_RC_W1), STM32_OTG_GINTSTS); - /* Break out of the loop when there are no further pending (and - * unmasked) interrupts to be processes. + /* Break out of the loop when there are no further pending (and unmasked) + * interrupts to be processes. */ if (regval == 0) { break; } - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t) regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an * interrupt is pending on one of the OUT endpoints of the core. @@ -3625,34 +3617,35 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_OEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t) regval); stm32_epout_interrupt(priv); } - /* IN endpoint interrupt. The core sets this bit to indicate that - * an interrupt is pending on one of the IN endpoints of the core. + /* IN endpoint interrupt. The core sets this bit to indicate that an + * interrupt is pending on one of the IN endpoints of the core. */ if ((regval & OTG_GINT_IEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t) regval); stm32_epin_interrupt(priv); } /* Host/device mode mismatch error interrupt */ -#ifdef CONFIG_DEBUG_USB +# ifdef CONFIG_DEBUG_USB if ((regval & OTG_GINT_MMIS) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), + (uint16_t) regval); } -#endif +# endif /* Resume/remote wakeup detected interrupt */ if ((regval & OTG_GINT_WKUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t) regval); stm32_resumeinterrupt(priv); } @@ -3660,18 +3653,19 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_USBSUSP) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), + (uint16_t) regval); stm32_suspendinterrupt(priv); } /* Start of frame interrupt */ -#ifdef CONFIG_USBDEV_SOFINTERRUPT +# ifdef CONFIG_USBDEV_SOFINTERRUPT if ((regval & OTG_GINT_SOF) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t) regval); } -#endif +# endif /* RxFIFO non-empty interrupt. Indicates that there is at least one * packet pending to be read from the RxFIFO. @@ -3679,7 +3673,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t) regval); stm32_rxinterrupt(priv); } @@ -3687,7 +3681,8 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & (OTG_GINT_USBRST | OTG_GINT_RSTDET)) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), + (uint16_t) regval); /* Perform the device reset */ @@ -3700,46 +3695,48 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_ENUMDNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), + (uint16_t) regval); stm32_enuminterrupt(priv); } /* Incomplete isochronous IN transfer interrupt. When the core finds - * non-empty any of the isochronous IN endpoint FIFOs scheduled for - * the current frame non-empty, the core generates an IISOIXFR - * interrupt. + * non-empty any of the isochronous IN endpoint FIFOs scheduled for the + * current frame non-empty, the core generates an IISOIXFR interrupt. */ -#ifdef CONFIG_USBDEV_ISOCHRONOUS +# ifdef CONFIG_USBDEV_ISOCHRONOUS if ((regval & OTG_GINT_IISOIXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), + (uint16_t) regval); stm32_isocininterrupt(priv); } - /* Incomplete isochronous OUT transfer. For isochronous OUT - * endpoints, the XFRC interrupt may not always be asserted. If the - * core drops isochronous OUT data packets, the application could fail - * to detect the XFRC interrupt. The incomplete Isochronous OUT data - * interrupt indicates that an XFRC interrupt was not asserted on at - * least one of the isochronous OUT endpoints. At this point, the - * endpoint with the incomplete transfer remains enabled, but no active - * transfers remain in progress on this endpoint on the USB. + /* Incomplete isochronous OUT transfer. For isochronous OUT endpoints, + * the XFRC interrupt may not always be asserted. If the core drops + * isochronous OUT data packets, the application could fail to detect the + * XFRC interrupt. The incomplete Isochronous OUT data interrupt + * indicates that an XFRC interrupt was not asserted on at least one of + * the isochronous OUT endpoints. At this point, the endpoint with the + * incomplete transfer remains enabled, but no active transfers remain in + * progress on this endpoint on the USB. */ if ((regval & OTG_GINT_IISOOXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), + (uint16_t) regval); stm32_isocoutinterrupt(priv); } -#endif +# endif /* Session request/new session detected interrupt */ -#ifdef CONFIG_USBDEV_VBUSSENSING +# ifdef CONFIG_USBDEV_VBUSSENSING if ((regval & OTG_GINT_SRQ) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t) regval); stm32_sessioninterrupt(priv); } @@ -3747,10 +3744,10 @@ static int stm32_usbinterrupt(int irq, FAR void *context, FAR void *arg) if ((regval & OTG_GINT_OTG) != 0) { - usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t) regval); stm32_otginterrupt(priv); } -#endif +# endif } usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); @@ -3775,9 +3772,9 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep) /* First, make sure that there is no GNOAKEFF interrupt pending. */ -#if 0 +# if 0 stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS); -#endif +# endif /* Enable Global OUT NAK mode in the core. */ @@ -3785,26 +3782,24 @@ static void stm32_enablegonak(FAR struct stm32_ep_s *privep) regval |= OTG_DCTL_SGONAK; stm32_putreg(regval, STM32_OTG_DCTL); -#if 0 - /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK - * mode is in effect. When the interrupt handler pops the OUTNAK word - * from the RxFIFO, the core sets the GONAKEFF interrupt. +# if 0 + /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK mode is in + * effect. When the interrupt handler pops the OUTNAK word from the RxFIFO, + * the core sets the GONAKEFF interrupt. */ while ((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINT_GONAKEFF) == 0); stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS); -#else +# else /* Since we are in the interrupt handler, we cannot wait inline for the * GONAKEFF because it cannot occur until service the RXFLVL global interrupt - * and pop the OUTNAK word from the RxFIFO. - * - * Perhaps it is sufficient to wait for Global OUT NAK status to be reported - * in OTG DCTL register? + * and pop the OUTNAK word from the RxFIFO. Perhaps it is sufficient to wait + * for Global OUT NAK status to be reported in OTG DCTL register? */ while ((stm32_getreg(STM32_OTG_DCTL) & OTG_DCTL_GONSTS) == 0); -#endif +# endif } /**************************************************************************** @@ -3821,7 +3816,7 @@ static void stm32_disablegonak(FAR struct stm32_ep_s *privep) /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - regval = stm32_getreg(STM32_OTG_DCTL); + regval = stm32_getreg(STM32_OTG_DCTL); regval |= OTG_DCTL_CGONAK; stm32_putreg(regval, STM32_OTG_DCTL); } @@ -3858,25 +3853,25 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, switch (maxpacket) { - case 8: - mpsiz = OTG_DOEPCTL0_MPSIZ_8; - break; + case 8: + mpsiz = OTG_DOEPCTL0_MPSIZ_8; + break; - case 16: - mpsiz = OTG_DOEPCTL0_MPSIZ_16; - break; + case 16: + mpsiz = OTG_DOEPCTL0_MPSIZ_16; + break; - case 32: - mpsiz = OTG_DOEPCTL0_MPSIZ_32; - break; + case 32: + mpsiz = OTG_DOEPCTL0_MPSIZ_32; + break; - case 64: - mpsiz = OTG_DOEPCTL0_MPSIZ_64; - break; + case 64: + mpsiz = OTG_DOEPCTL0_MPSIZ_64; + break; - default: - uerr("Unsupported maxpacket: %d\n", maxpacket); - return -EINVAL; + default: + uerr("Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; } } @@ -3892,7 +3887,7 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTG_DOEPCTL_USBAEP) == 0) { if (regval & OTG_DOEPCTL_NAKSTS) @@ -3909,8 +3904,8 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, /* Save the endpoint configuration */ privep->ep.maxpacket = maxpacket; - privep->eptype = eptype; - privep->stalled = false; + privep->eptype = eptype; + privep->stalled = false; } /* Enable the interrupt for this endpoint */ @@ -3953,25 +3948,25 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, switch (maxpacket) { - case 8: - mpsiz = OTG_DIEPCTL0_MPSIZ_8; - break; + case 8: + mpsiz = OTG_DIEPCTL0_MPSIZ_8; + break; - case 16: - mpsiz = OTG_DIEPCTL0_MPSIZ_16; - break; + case 16: + mpsiz = OTG_DIEPCTL0_MPSIZ_16; + break; - case 32: - mpsiz = OTG_DIEPCTL0_MPSIZ_32; - break; + case 32: + mpsiz = OTG_DIEPCTL0_MPSIZ_32; + break; - case 64: - mpsiz = OTG_DIEPCTL0_MPSIZ_64; - break; + case 64: + mpsiz = OTG_DIEPCTL0_MPSIZ_64; + break; - default: - uerr("Unsupported maxpacket: %d\n", maxpacket); - return -EINVAL; + default: + uerr("Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; } } @@ -3982,13 +3977,12 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, mpsiz = (maxpacket << OTG_DIEPCTL_MPSIZ_SHIFT); } - /* If the endpoint is already active don't change the endpoint control * register. */ regaddr = STM32_OTG_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTG_DIEPCTL_USBAEP) == 0) { if (regval & OTG_DIEPCTL_NAKSTS) @@ -4007,8 +4001,8 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, /* Save the endpoint configuration */ privep->ep.maxpacket = maxpacket; - privep->eptype = eptype; - privep->stalled = false; + privep->eptype = eptype; + privep->stalled = false; } /* Enable the interrupt for this endpoint */ @@ -4036,12 +4030,11 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, ****************************************************************************/ static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, - FAR const struct usb_epdesc_s *desc, - bool last) + FAR const struct usb_epdesc_s *desc, bool last) { FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; uint16_t maxpacket; - uint8_t eptype; + uint8_t eptype; int ret; usbtrace(TRACE_EPCONFIGURE, privep->epphy); @@ -4050,7 +4043,7 @@ static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, /* Initialize EP capabilities */ maxpacket = GETUINT16(desc->mxpacketsize); - eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; + eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; /* Setup Endpoint Control Register */ @@ -4102,48 +4095,49 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep) /* Is this an IN or an OUT endpoint */ - /* Before disabling any OUT endpoint, the application must enable - * Global OUT NAK mode in the core. + /* Before disabling any OUT endpoint, the application must enable Global OUT + * NAK mode in the core. */ flags = enter_critical_section(); stm32_enablegonak(privep); - /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits - * int DOECPTL register. + /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits int + * DOECPTL register. */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTG_DOEPCTL_USBAEP; regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_SNAK); stm32_putreg(regval, regaddr); - /* Wait for the EPDISD interrupt which indicates that the OUT - * endpoint is completely disabled. + /* Wait for the EPDISD interrupt which indicates that the OUT endpoint is + * completely disabled. */ -#if 0 /* Doesn't happen */ +# if 0 /* Doesn't happen */ regaddr = STM32_OTG_DOEPINT(privep->epphy); while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0); -#else +# else /* REVISIT: */ + up_udelay(10); -#endif +# endif /* Clear the EPDISD interrupt indication */ stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(privep->epphy)); - /* Then disable the Global OUT NAK mode to continue receiving data - * from other non-disabled OUT endpoints. + /* Then disable the Global OUT NAK mode to continue receiving data from other + * non-disabled OUT endpoints. */ stm32_disablegonak(privep); /* Disable endpoint interrupts */ - regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval = stm32_getreg(STM32_OTG_DAINTMSK); regval &= ~OTG_DAINT_OEP(privep->epphy); stm32_putreg(regval, STM32_OTG_DAINTMSK); @@ -4170,24 +4164,24 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) usbtrace(TRACE_EPDISABLE, privep->epphy); - /* After USB reset, the endpoint will already be deactivated by the - * hardware. Trying to disable again will just hang in the wait. + /* After USB reset, the endpoint will already be deactivated by the hardware. + * Trying to disable again will just hang in the wait. */ regaddr = STM32_OTG_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTG_DIEPCTL_USBAEP) == 0) { return; } - /* This INEPNE wait logic is suggested by reference manual, but seems - * to get stuck to infinite loop. + /* This INEPNE wait logic is suggested by reference manual, but seems to get + * stuck to infinite loop. */ -#if 0 - /* Make sure that there is no pending IPEPNE interrupt (because we are - * to poll this bit below). +# if 0 + /* Make sure that there is no pending IPEPNE interrupt (because we are to + * poll this bit below). */ stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(privep->epphy)); @@ -4195,7 +4189,7 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) /* Set the endpoint in NAK mode */ regaddr = STM32_OTG_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTG_DIEPCTL_USBAEP; regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK); stm32_putreg(regval, regaddr); @@ -4208,21 +4202,21 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) /* Clear the INEPNE interrupt indication */ stm32_putreg(OTG_DIEPINT_INEPNE, regaddr); -#endif +# endif - /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits - * the DIEPCTLx register. + /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits the + * DIEPCTLx register. */ flags = enter_critical_section(); regaddr = STM32_OTG_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTG_DIEPCTL_USBAEP; regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK); stm32_putreg(regval, regaddr); - /* Wait for the EPDISD interrupt which indicates that the IN - * endpoint is completely disabled. + /* Wait for the EPDISD interrupt which indicates that the IN endpoint is + * completely disabled. */ regaddr = STM32_OTG_DIEPINT(privep->epphy); @@ -4240,7 +4234,7 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep) /* Disable endpoint interrupts */ - regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval = stm32_getreg(STM32_OTG_DAINTMSK); regval &= ~OTG_DAINT_IEP(privep->epphy); stm32_putreg(regval, STM32_OTG_DAINTMSK); @@ -4262,13 +4256,13 @@ static int stm32_ep_disable(FAR struct usbdev_ep_s *ep) { FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } -#endif +# endif usbtrace(TRACE_EPDISABLE, privep->epphy); @@ -4302,13 +4296,13 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep) { FAR struct stm32_req_s *privreq; -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } -#endif +# endif usbtrace(TRACE_EPALLOCREQ, ((FAR struct stm32_ep_s *)ep)->epphy); @@ -4331,17 +4325,18 @@ static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep) * ****************************************************************************/ -static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } -#endif +# endif usbtrace(TRACE_EPFREEREQ, ((FAR struct stm32_ep_s *)ep)->epphy); kmm_free(privreq); @@ -4355,18 +4350,18 @@ static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * ****************************************************************************/ -#ifdef CONFIG_USBDEV_DMA +# ifdef CONFIG_USBDEV_DMA static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes) { usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy); -#ifdef CONFIG_USBDEV_DMAMEMORY +# ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); -#else +# else return kmm_malloc(bytes); -#endif +# endif } -#endif +# endif /**************************************************************************** * Name: stm32_ep_freebuffer @@ -4376,18 +4371,18 @@ static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, uint16_t bytes) * ****************************************************************************/ -#ifdef CONFIG_USBDEV_DMA +# ifdef CONFIG_USBDEV_DMA static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) { usbtrace(TRACE_EPALLOCBUFFER, ((FAR struct stm32_ep_s *)ep)->epphy); -#ifdef CONFIG_USBDEV_DMAMEMORY +# ifdef CONFIG_USBDEV_DMAMEMORY usbdev_dma_free(buf); -#else +# else kmm_free(buf); -#endif +# endif } -#endif +# endif /**************************************************************************** * Name: stm32_ep_submit @@ -4397,7 +4392,8 @@ static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) * ****************************************************************************/ -static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; @@ -4407,30 +4403,32 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * /* Some sanity checking */ -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); - uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, + ep); return -EINVAL; } -#endif +# endif usbtrace(TRACE_EPSUBMIT, privep->epphy); priv = privep->dev; -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); return -ESHUTDOWN; } -#endif +# endif /* Handle the request from the class driver */ req->result = -EINPROGRESS; - req->xfrd = 0; + req->xfrd = 0; /* Disable Interrupts */ @@ -4448,16 +4446,16 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * if (stm32_req_addlast(privep, privreq) && !privep->active) { - /* If a request was added to an IN endpoint, then attempt to send - * the request data buffer now. + /* If a request was added to an IN endpoint, then attempt to send the + * request data buffer now. */ if (privep->isin) { usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); - /* If the endpoint is not busy with another write request, - * then process the newly received write request now. + /* If the endpoint is not busy with another write request, then + * process the newly received write request now. */ if (!privep->active) @@ -4466,9 +4464,9 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * } } - /* If the request was added to an OUT endpoint, then attempt to - * setup a read into the request data buffer now (this will, of - * course, fail if there is already a read in place). + /* If the request was added to an OUT endpoint, then attempt to setup + * a read into the request data buffer now (this will, of course, + * fail if there is already a read in place). */ else @@ -4491,27 +4489,27 @@ static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * * ****************************************************************************/ -static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *req) { FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; irqstate_t flags; -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } -#endif +# endif usbtrace(TRACE_EPCANCEL, privep->epphy); flags = enter_critical_section(); - /* FIXME: if the request is the first, then we need to flush the EP - * otherwise just remove it from the list - * - * but ... all other implementations cancel all requests ... + /* FIXME: if the request is the first, then we need to flush the EP otherwise + * just remove it from the list but ... all other implementations cancel all + * requests ... */ stm32_req_cancel(privep, -ESHUTDOWN); @@ -4529,7 +4527,7 @@ static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s * static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) { -#if 1 +# if 1 /* This implementation follows the requirements from the STM32 F4 reference * manual. */ @@ -4541,26 +4539,27 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) stm32_enablegonak(privep); - /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits - * in the DOECPTL register. + /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits in + * the DOECPTL register. */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_STALL); stm32_putreg(regval, regaddr); - /* Wait for the EPDISD interrupt which indicates that the OUT - * endpoint is completely disabled. + /* Wait for the EPDISD interrupt which indicates that the OUT endpoint is + * completely disabled. */ -#if 0 /* Doesn't happen */ +# if 0 /* Doesn't happen */ regaddr = STM32_OTG_DOEPINT(privep->epphy); while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0); -#else +# else /* REVISIT: */ + up_udelay(10); -#endif +# endif /* Disable Global OUT NAK mode */ @@ -4570,7 +4569,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) privep->stalled = true; return OK; -#else +# else /* This implementation follows the STMicro code example. */ /* REVISIT: */ @@ -4580,7 +4579,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. */ regaddr = STM32_OTG_DOEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTG_DOEPCTL_STALL; stm32_putreg(regval, regaddr); @@ -4588,7 +4587,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) privep->stalled = true; return OK; -#endif +# endif } /**************************************************************************** @@ -4607,7 +4606,7 @@ static int stm32_epin_setstall(FAR struct stm32_ep_s *privep) /* Get the IN endpoint device control register */ regaddr = STM32_OTG_DIEPCTL(privep->epphy); - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); /* Then stall the endpoint */ @@ -4667,7 +4666,7 @@ static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regaddr = STM32_OTG_DIEPCTL(privep->epphy); stallbit = OTG_DIEPCTL_STALL; data0bit = OTG_DIEPCTL_SD0PID; } @@ -4675,14 +4674,14 @@ static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regaddr = STM32_OTG_DOEPCTL(privep->epphy); stallbit = OTG_DOEPCTL_STALL; data0bit = OTG_DOEPCTL_SD0PID; } /* Clear the stall bit */ - regval = stm32_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~stallbit; /* Set the DATA0 pid for interrupt and bulk endpoints */ @@ -4779,7 +4778,7 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, int epphy; int epno = 0; - usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); + usbtrace(TRACE_DEVALLOCEP, (uint16_t) eplog); /* Ignore any direction bits in the logical address */ @@ -4794,16 +4793,15 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, if (epphy > 0) { - /* Otherwise, we will return the endpoint structure only for the requested - * 'logical' endpoint. All of the other checks will still be performed. - * - * First, verify that the logical endpoint is in the range supported by - * by the hardware. + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still be + * performed. First, verify that the logical endpoint is in the range + * supported by by the hardware. */ if (epphy >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t) epphy); return NULL; } @@ -4841,7 +4839,7 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, /* We should not get here */ } - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t) eplog); leave_critical_section(flags); return NULL; } @@ -4860,7 +4858,7 @@ static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; irqstate_t flags; - usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); + usbtrace(TRACE_DEVFREEEP, (uint16_t) privep->epphy); if (priv && privep) { @@ -4920,14 +4918,14 @@ static int stm32_wakeup(struct usbdev_s *dev) { /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ -#ifdef CONFIG_USBDEV_LOWPOWER +# ifdef CONFIG_USBDEV_LOWPOWER regval = stm32_getreg(STM32_OTG_PCGCCTL); regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK); stm32_putreg(regval, STM32_OTG_PCGCCTL); -#endif +# endif /* Activate Remote wakeup signaling */ - regval = stm32_getreg(STM32_OTG_DCTL); + regval = stm32_getreg(STM32_OTG_DCTL); regval |= OTG_DCTL_RWUSIG; stm32_putreg(regval, STM32_OTG_DCTL); up_mdelay(5); @@ -4952,15 +4950,15 @@ static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; - usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t) selfpowered); -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!dev) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } -#endif +# endif priv->selfpowered = selfpowered; return OK; @@ -4978,7 +4976,7 @@ static int stm32_pullup(struct usbdev_s *dev, bool enable) { uint32_t regval; - usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + usbtrace(TRACE_DEVPULLUP, (uint16_t) enable); irqstate_t flags = enter_critical_section(); regval = stm32_getreg(STM32_OTG_DCTL); @@ -5020,21 +5018,19 @@ static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DAD_MASK; - regval |= ((uint32_t)address << OTG_DCFG_DAD_SHIFT); + regval |= ((uint32_t) address << OTG_DCFG_DAD_SHIFT); stm32_putreg(regval, STM32_OTG_DCFG); - /* Are we now addressed? (i.e., do we have a non-NULL device - * address?) - */ + /* Are we now addressed? (i.e., do we have a non-NULL device address?) */ if (address != 0) { - priv->devstate = DEVSTATE_ADDRESSED; + priv->devstate = DEVSTATE_ADDRESSED; priv->addressed = true; } else { - priv->devstate = DEVSTATE_DEFAULT; + priv->devstate = DEVSTATE_DEFAULT; priv->addressed = false; } } @@ -5131,34 +5127,33 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv) priv->epavail[0] = STM32_EP_AVAILABLE; priv->epavail[1] = STM32_EP_AVAILABLE; - priv->epin[EP0].ep.priv = priv; + priv->epin[EP0].ep.priv = priv; priv->epout[EP0].ep.priv = priv; /* Initialize the endpoint lists */ for (i = 0; i < STM32_NENDPOINTS; i++) { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the physical endpoint number (which is just the index to the - * endpoint). + /* Set endpoint operations, reference to driver structure (not really + * necessary because there is only one controller), and the physical + * endpoint number (which is just the index to the endpoint). */ - privep = &priv->epin[i]; - privep->ep.ops = &g_epops; - privep->dev = priv; - privep->isin = 1; + privep = &priv->epin[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + privep->isin = 1; - /* The index, i, is the physical endpoint address; Map this - * to a logical endpoint address usable by the class driver. + /* The index, i, is the physical endpoint address; Map this to a logical + * endpoint address usable by the class driver. */ - privep->epphy = i; + privep->epphy = i; privep->ep.eplog = STM32_EPPHYIN2LOG(i); /* Control until endpoint is activated */ - privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->eptype = USB_EP_ATTR_XFER_CONTROL; privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; } @@ -5166,26 +5161,25 @@ static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv) for (i = 0; i < STM32_NENDPOINTS; i++) { - /* Set endpoint operations, reference to driver structure (not - * really necessary because there is only one controller), and - * the physical endpoint number (which is just the index to the - * endpoint). + /* Set endpoint operations, reference to driver structure (not really + * necessary because there is only one controller), and the physical + * endpoint number (which is just the index to the endpoint). */ - privep = &priv->epout[i]; - privep->ep.ops = &g_epops; - privep->dev = priv; + privep = &priv->epout[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; - /* The index, i, is the physical endpoint address; Map this - * to a logical endpoint address usable by the class driver. + /* The index, i, is the physical endpoint address; Map this to a logical + * endpoint address usable by the class driver. */ - privep->epphy = i; + privep->epphy = i; privep->ep.eplog = STM32_EPPHYOUT2LOG(i); /* Control until endpoint is activated */ - privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->eptype = USB_EP_ATTR_XFER_CONTROL; privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; } } @@ -5214,15 +5208,86 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -#if defined(CONFIG_STM32F7_OTGHS) - /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial - * transceiver: "This bit is always 1 with write-only access" +# ifdef CONFIG_STM32F7_OTGFSHS + +# ifndef CONFIG_STM32F7_NO_ULPI + + /* Switch off FS tranceiver */ + + regval = stm32_getreg(STM32_OTG_GCCFG); + regval &= ~(OTG_GCCFG_PWRDWN); + stm32_putreg(regval, STM32_OTG_GCCFG); + + /* Init The ULPI Interface: Set the PHYSEL bit in the GUSBCFG register to + * select the OTG HS serial 0: USB 2.0 external ULPI high-speed PHY or + * internal UTMI high-speed PHY" 1: USB 1.1 full-speed serial transceiver */ - regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~(OTG_GUSBCFG_TSDPS | OTG_GUSBCFG_ULPIFSLS | OTG_GUSBCFG_PHYSEL); + stm32_putreg(regval, STM32_OTG_GUSBCFG); + + /* Select vbus source */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI); + stm32_putreg(regval, STM32_OTG_GUSBCFG); + +# ifdef CONFIG_STM32F7_INTERNAL_ULPI + + /* Select UTMI/ULPI Interace */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~OTG_GUSBCFG_ULPISEL; + stm32_putreg(regval, STM32_OTG_GUSBCFG); + + /* Not in datasheet but in stmcube ? */ + + regval = stm32_getreg(STM32_OTG_GCCFG); + regval |= OTG_GCCFG_PHYHSEN; + stm32_putreg(regval, STM32_OTG_GCCFG); + + /* Enable LDO */ + + stm32_putreg(USBPHYC_LDO_ENABLE, STM32_USBPHYC_LDO); + + /* wait for LDO Ready */ + + while (!(stm32_getreg(STM32_USBPHYC_LDO) & USBPHYC_LDO_STATUS)); + + /* Controls PHY frequency operation selection */ + + stm32_putreg(USBPHYC_PLL1_SEL_25MHz, STM32_USBPHYC_PLL1); + + /* Control the tuning interface of the High Speed PHY */ + + regval = stm32_getreg(STM32_USBPHYC_TUNE); + + /* TODO set right value */ + + regval |= 0x00000f13; + stm32_putreg(regval, STM32_USBPHYC_TUNE); + + /* Enable PLL internal PHY */ + + regval = stm32_getreg(STM32_USBPHYC_PLL1); + regval |= USBPHYC_PLL1_EN; + stm32_putreg(regval, STM32_USBPHYC_PLL1); + + /* 2ms delay required for clk to be stable */ + + up_udelay(2000); + +# endif /* CONFIG_STM32F7_INTERNAL_ULPI */ +# endif /* ifndef CONFIG_STM32F7_NO_ULPI */ + +# else /* CONFIG_STM32F7_OTGFSHS */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); regval |= OTG_GUSBCFG_PHYSEL; stm32_putreg(regval, STM32_OTG_GUSBCFG); -#endif + +# endif /* CONFIG_STM32F7_OTGFSHS */ /* Common USB OTG core initialization */ /* Reset after a PHY select and set Host mode. First, wait for AHB master @@ -5241,7 +5306,9 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) /* Then perform the core soft reset. */ - stm32_putreg(OTG_GRSTCTL_CSRST, STM32_OTG_GRSTCTL); + regval = stm32_getreg(STM32_OTG_GRSTCTL); + regval |= OTG_GRSTCTL_CSRST; + stm32_putreg(regval, STM32_OTG_GRSTCTL); for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { regval = stm32_getreg(STM32_OTG_GRSTCTL); @@ -5257,35 +5324,32 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) /* Deactivate the power down */ + /* Detection Enable when set */ - /* Detection Enable when set - */ + regval = stm32_getreg(STM32_OTG_GCCFG); - regval = OTG_GCCFG_PWRDWN; +# if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_NO_ULPI)) + regval |= OTG_GCCFG_PWRDWN; +# endif -# ifdef CONFIG_USBDEV_VBUSSENSING +# ifdef CONFIG_USBDEV_VBUSSENSING regval |= OTG_GCCFG_VBDEN; -# endif - +# endif stm32_putreg(regval, STM32_OTG_GCCFG); up_mdelay(20); - /* When VBUS sensing is not used we - * need to force the B session valid - */ + /* When VBUS sensing is not used we need to force the B session valid */ - -# ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32_getreg(STM32_OTG_GOTGCTL); +# ifndef CONFIG_USBDEV_VBUSSENSING + regval = stm32_getreg(STM32_OTG_GOTGCTL); regval |= (OTG_GOTGCTL_BVALOEN | OTG_GOTGCTL_BVALOVAL); stm32_putreg(regval, STM32_OTG_GOTGCTL); -# endif - +# endif /* Force Device Mode */ - regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_FHMOD; regval |= OTG_GUSBCFG_FDMOD; stm32_putreg(regval, STM32_OTG_GUSBCFG); @@ -5303,79 +5367,83 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) regval |= OTG_DCFG_PFIVL_80PCT; stm32_putreg(regval, STM32_OTG_DCFG); - /* Set full speed PHY */ + /* Set PHY speed */ regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; +# ifdef CONFIG_STM32F7_OTGFSHS + regval |= OTG_DCFG_DSPD_HS; +# else regval |= OTG_DCFG_DSPD_FS; +# endif stm32_putreg(regval, STM32_OTG_DCFG); /* Set Rx FIFO size */ stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTG_GRXFSIZ); -#if STM32_NENDPOINTS > 0 +# if STM32_NENDPOINTS > 0 address = STM32_RXFIFO_WORDS; - regval = (address << OTG_DIEPTXF0_TX0FD_SHIFT) | - (STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT); + regval = (address << OTG_DIEPTXF0_TX0FD_SHIFT) | + (STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF0); -#endif +# endif -#if STM32_NENDPOINTS > 1 +# if STM32_NENDPOINTS > 1 address += STM32_EP0_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(1)); -#endif +# endif -#if STM32_NENDPOINTS > 2 +# if STM32_NENDPOINTS > 2 address += STM32_EP1_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(2)); -#endif +# endif -#if STM32_NENDPOINTS > 3 +# if STM32_NENDPOINTS > 3 address += STM32_EP2_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(3)); -#endif +# endif -#if STM32_NENDPOINTS > 4 +# if STM32_NENDPOINTS > 4 address += STM32_EP3_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP4_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP4_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(4)); -#endif +# endif -#if STM32_NENDPOINTS > 5 +# if STM32_NENDPOINTS > 5 address += STM32_EP4_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP5_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP5_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(5)); -#endif +# endif -#if STM32_NENDPOINTS > 6 +# if STM32_NENDPOINTS > 6 address += STM32_EP5_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP6_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP6_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(6)); -#endif +# endif -#if STM32_NENDPOINTS > 7 +# if STM32_NENDPOINTS > 7 address += STM32_EP6_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP7_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP7_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(7)); -#endif +# endif -#if STM32_NENDPOINTS > 8 +# if STM32_NENDPOINTS > 8 address += STM32_EP7_TXFIFO_WORDS; - regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | - (STM32_EP8_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP8_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); stm32_putreg(regval, STM32_OTG_DIEPTXF(8)); -#endif +# endif /* Flush the FIFOs */ @@ -5399,7 +5467,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) { /* The endpoint is already enabled */ - regval = OTG_DIEPCTL_EPENA | OTG_DIEPCTL_SNAK; + regval = OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK; } else { @@ -5420,7 +5488,7 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) { /* The endpoint is already enabled */ - regval = OTG_DOEPCTL_EPENA | OTG_DOEPCTL_SNAK; + regval = OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_SNAK; } else { @@ -5443,52 +5511,51 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) /* Clear any pending interrupts */ regval = stm32_getreg(STM32_OTG_GINTSTS); - regval &= OTG_GINT_RESERVED; + regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -#if defined(CONFIG_STM32F7_OTGHS) && !defined(BOARD_ENABLE_USBOTG_HSULPI) - /* Disable the ULPI Clock enable in RCC AHB1 Register. This must - * be done because if both the ULPI and the FS PHY clock enable bits - * are set at the same time, the ARM never awakens from WFI due to - * some bug / errata in the chip. +# if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI) + /* Disable the ULPI Clock enable in RCC AHB1 Register. This must be done + * because if both the ULPI and the FS PHY clock enable bits are set at the + * same time, the ARM never awakens from WFI due to some bug / errata in the + * chip. */ regval = stm32_getreg(STM32_RCC_AHB1LPENR); regval &= ~RCC_AHB1ENR_OTGHSULPIEN; stm32_putreg(regval, STM32_RCC_AHB1LPENR); -#endif +# endif /* Enable the interrupts in the INTMSK */ regval = (OTG_GINT_RXFLVL | OTG_GINT_USBSUSP | OTG_GINT_ENUMDNE | OTG_GINT_IEP | OTG_GINT_OEP | OTG_GINT_USBRST); -#ifdef CONFIG_USBDEV_ISOCHRONOUS +# ifdef CONFIG_USBDEV_ISOCHRONOUS regval |= (OTG_GINT_IISOIXFR | OTG_GINT_IISOOXFR); -#endif +# endif -#ifdef CONFIG_USBDEV_SOFINTERRUPT +# ifdef CONFIG_USBDEV_SOFINTERRUPT regval |= OTG_GINT_SOF; -#endif +# endif -#ifdef CONFIG_USBDEV_VBUSSENSING +# ifdef CONFIG_USBDEV_VBUSSENSING regval |= (OTG_GINT_OTG | OTG_GINT_SRQ); -#endif +# endif -#ifdef CONFIG_DEBUG_USB +# ifdef CONFIG_DEBUG_USB regval |= OTG_GINT_MMIS; -#endif +# endif stm32_putreg(regval, STM32_OTG_GINTMSK); - /* Enable the USB global interrupt by setting GINTMSK in the global OTG - * AHB configuration register; Set the TXFELVL bit in the GAHBCFG - * register so that TxFIFO interrupts will occur when the TxFIFO is truly - * empty (not just half full). + /* Enable the USB global interrupt by setting GINTMSK in the global OTG AHB + * configuration register; Set the TXFELVL bit in the GAHBCFG register so + * that TxFIFO interrupts will occur when the TxFIFO is truly empty (not just + * half full). */ - stm32_putreg(OTG_GAHBCFG_GINTMSK | OTG_GAHBCFG_TXFELVL, - STM32_OTG_GAHBCFG); + stm32_putreg(OTG_GAHBCFG_GINTMSK | OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); } /**************************************************************************** @@ -5515,8 +5582,7 @@ void up_usbinitialize(void) /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the - * global data) in order to simplify any future support for multiple - * devices. + * global data) in order to simplify any future support for multiple devices. */ FAR struct stm32_usbdev_s *priv = &g_otghsdev; @@ -5524,30 +5590,27 @@ void up_usbinitialize(void) usbtrace(TRACE_DEVINIT, 0); - /* Here we assume that: - * - * 1. GPIOA and OTG peripheral clocking has already been enabled as part - * of the boot sequence. - * 2. Board-specific logic has already enabled other board specific GPIOs - * for things like soft pull-up, VBUS sensing, power controls, and over- - * current detection. + /* Here we assume that: 1. GPIOA and OTG peripheral clocking has already + * been enabled as part of the boot sequence. 2. Board-specific logic has + * already enabled other board specific GPIOs for things like soft pull-up, + * VBUS sensing, power controls, and over- current detection. */ - /* Configure OTG alternate function pins - */ + /* Configure OTG alternate function pins */ stm32_configgpio(GPIO_OTG_DM); stm32_configgpio(GPIO_OTG_DP); - stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ + stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ /* SOF output pin configuration is configurable. */ -#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32F7_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); -#endif +# endif /* Uninitialize the hardware so that we know that we are starting from a - * known state. */ + * known state. + */ up_usbuninitialize(); @@ -5579,6 +5642,7 @@ void up_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ up_enable_irq(STM32_IRQ_OTG); + return; errout: @@ -5591,7 +5655,7 @@ errout: void up_usbuninitialize(void) { - /* At present, there is only a single OTG device support. Hence it is + /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the * global data) in order to simplify any future support for multiple devices. @@ -5656,7 +5720,7 @@ void up_usbuninitialize(void) int usbdev_register(struct usbdevclass_driver_s *driver) { - /* At present, there is only a single OTG device support. Hence it is + /* At present, there is only a single OTG device support. Hence it is * pre-allocated as g_otghsdev. However, in most code, the private data * structure will be referenced using the 'priv' pointer (rather than the * global data) in order to simplify any future support for multiple devices. @@ -5667,7 +5731,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVREGISTER, 0); -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { @@ -5680,7 +5744,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } -#endif +# endif /* First hook up the driver */ @@ -5691,7 +5755,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t) - ret); priv->driver = NULL; } else @@ -5700,16 +5764,20 @@ int usbdev_register(struct usbdevclass_driver_s *driver) up_enable_irq(STM32_IRQ_OTG); - /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set - * the RS bit to enable the controller. It kind of makes sense - * to do this after the class has bound to us... - * GEN: This bug is really in the class driver. It should make the - * soft connect when it is ready to be enumerated. I have added - * that logic to the class drivers but left this logic here. + /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set the RS + * bit to enable the controller. It kind of makes sense to do this after + * the class has bound to us... GEN: This bug is really in the class + * driver. It should make the soft connect when it is ready to be + * enumerated. I have added that logic to the class drivers but left + * this logic here. */ stm32_pullup(&priv->usbdev, true); +# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) + priv->usbdev.speed = USB_SPEED_HIGH; +# else priv->usbdev.speed = USB_SPEED_FULL; +# endif } return ret; @@ -5738,16 +5806,16 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVUNREGISTER, 0); -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES if (driver != priv->driver) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } -#endif +# endif - /* Reset the hardware and cancel all requests. All requests must be - * canceled while the class driver is still bound. + /* Reset the hardware and cancel all requests. All requests must be canceled + * while the class driver is still bound. */ flags = enter_critical_section(); @@ -5775,4 +5843,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */ +#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */ diff --git a/arch/arm/src/stm32f7/stm32_usbhost.h b/arch/arm/src/stm32f7/stm32_usbhost.h index 4d3ee1aa978..29431e144f9 100644 --- a/arch/arm/src/stm32f7/stm32_usbhost.h +++ b/arch/arm/src/stm32f7/stm32_usbhost.h @@ -43,7 +43,7 @@ * CONFIG_USBHOST - Enable general USB host support * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32F7_OTGHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32F7_OTGFSHS - Enable the STM32 USB OTG HS block * CONFIG_STM32F7_SYSCFG - Needed * * Options: @@ -68,7 +68,7 @@ #include #include -#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS)) && \ +#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \ defined(CONFIG_USBHOST) /************************************************************************************ @@ -120,5 +120,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 39c9b188059..c6488538112 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -227,8 +227,8 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGHS -#ifdef BOARD_ENABLE_USBOTG_HSULPI +#ifdef CONFIG_STM32F7_OTGFSHS +#if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); @@ -237,7 +237,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGHS */ +#endif /* CONFIG_STM32F7_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -657,6 +657,13 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_LTDCEN; #endif +#ifdef CONFIG_STM32F7_OTGFSHS +#ifdef CONFIG_STM32F7_INTERNAL_ULPI + regval |= RCC_APB2ENR_OTGPHYCEN; + +#endif +#endif + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } @@ -833,8 +840,8 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); #ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR - /* The Flash memory interface accelerates code execution with a system of - * instruction prefetch and cache lines on ITCM interface (ART + /* The Flash memory interface accelerates code execution with a system + * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). */ @@ -862,7 +869,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); - regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | RCC_PLLSAICFGR_PLLSAIQ_MASK # if defined(CONFIG_STM32F7_LTDC) @@ -899,7 +906,6 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR1); - /* Enable PLLSAI */ regval = getreg32(STM32_RCC_CR); @@ -917,7 +923,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLI2S */ regval = getreg32(STM32_RCC_PLLI2SCFGR); - regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK + regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK # if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) | RCC_PLLI2SCFGR_PLLI2SP_MASK # endif @@ -932,7 +938,7 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_PLLI2SCFGR); regval = getreg32(STM32_RCC_DCKCFGR2); - regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK | RCC_DCKCFGR2_USART2SEL_MASK | RCC_DCKCFGR2_UART4SEL_MASK | RCC_DCKCFGR2_UART5SEL_MASK @@ -951,7 +957,7 @@ static void stm32_stdclockconfig(void) | RCC_DCKCFGR2_SDMMCSEL_MASK | RCC_DCKCFGR2_SDMMC2SEL_MASK); - regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + regval |= (STM32_RCC_DCKCFGR2_USART1SRC | STM32_RCC_DCKCFGR2_USART2SRC | STM32_RCC_DCKCFGR2_UART4SRC | STM32_RCC_DCKCFGR2_UART5SRC diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 0883a31b705..4f571e92566 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -230,17 +230,18 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGHS -#ifdef BOARD_ENABLE_USBOTG_HSULPI +#ifdef CONFIG_STM32F7_OTGFSHS + #if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); #else + /* Enable only clocking for USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGHS */ +#endif /* CONFIG_STM32F7_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -836,8 +837,8 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); #ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR - /* The Flash memory interface accelerates code execution with a system of - * instruction prefetch and cache lines on ITCM interface (ART + /* The Flash memory interface accelerates code execution with a system + * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). */ @@ -865,7 +866,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); - regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | RCC_PLLSAICFGR_PLLSAIQ_MASK | RCC_PLLSAICFGR_PLLSAIR_MASK); @@ -892,7 +893,6 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR1); - /* Enable PLLSAI */ regval = getreg32(STM32_RCC_CR); @@ -910,7 +910,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLI2S */ regval = getreg32(STM32_RCC_PLLI2SCFGR); - regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK + regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK | RCC_PLLI2SCFGR_PLLI2SP_MASK | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); @@ -921,7 +921,7 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_PLLI2SCFGR); regval = getreg32(STM32_RCC_DCKCFGR2); - regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK | RCC_DCKCFGR2_USART2SEL_MASK | RCC_DCKCFGR2_UART4SEL_MASK | RCC_DCKCFGR2_UART5SEL_MASK @@ -937,7 +937,7 @@ static void stm32_stdclockconfig(void) | RCC_DCKCFGR2_CK48MSEL_MASK | RCC_DCKCFGR2_SDMMCSEL_MASK); - regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + regval |= (STM32_RCC_DCKCFGR2_USART1SRC | STM32_RCC_DCKCFGR2_USART2SRC | STM32_RCC_DCKCFGR2_UART4SRC | STM32_RCC_DCKCFGR2_UART5SRC diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index f43e90c383d..cf89f52da1c 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -236,7 +236,7 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGHS +#ifdef CONFIG_STM32F7_OTGFSHS #ifdef BOARD_ENABLE_USBOTG_HSULPI /* Enable clocking for USB OTG HS and external PHY */ @@ -246,7 +246,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGHS */ +#endif /* CONFIG_STM32F7_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -503,7 +503,6 @@ static inline void rcc_enableapb1(void) regval |= (RCC_APB1ENR_CAN3EN); #endif - #ifdef CONFIG_STM32F7_CEC /* CEC clock enable. */ @@ -855,8 +854,8 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); #ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR - /* The Flash memory interface accelerates code execution with a system of - * instruction prefetch and cache lines on ITCM interface (ART + /* The Flash memory interface accelerates code execution with a system + * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). */ @@ -884,7 +883,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLSAI */ regval = getreg32(STM32_RCC_PLLSAICFGR); - regval &= ~( RCC_PLLSAICFGR_PLLSAIN_MASK + regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | RCC_PLLSAICFGR_PLLSAIQ_MASK | RCC_PLLSAICFGR_PLLSAIR_MASK); @@ -932,7 +931,7 @@ static void stm32_stdclockconfig(void) /* Configure PLLI2S */ regval = getreg32(STM32_RCC_PLLI2SCFGR); - regval &= ~( RCC_PLLI2SCFGR_PLLI2SN_MASK + regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK | RCC_PLLI2SCFGR_PLLI2SP_MASK | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); @@ -956,7 +955,7 @@ static void stm32_stdclockconfig(void) #endif regval = getreg32(STM32_RCC_DCKCFGR2); - regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK + regval &= ~(RCC_DCKCFGR2_USART1SEL_MASK | RCC_DCKCFGR2_USART2SEL_MASK | RCC_DCKCFGR2_UART4SEL_MASK | RCC_DCKCFGR2_UART5SEL_MASK @@ -974,7 +973,7 @@ static void stm32_stdclockconfig(void) | RCC_DCKCFGR2_SDMMC2SEL_MASK | RCC_DCKCFGR2_DSISEL_MASK); - regval |= ( STM32_RCC_DCKCFGR2_USART1SRC + regval |= (STM32_RCC_DCKCFGR2_USART1SRC | STM32_RCC_DCKCFGR2_USART2SRC | STM32_RCC_DCKCFGR2_UART4SRC | STM32_RCC_DCKCFGR2_UART5SRC diff --git a/drivers/usbdev/Kconfig b/drivers/usbdev/Kconfig index adaff6bddaf..d0d9c178f04 100644 --- a/drivers/usbdev/Kconfig +++ b/drivers/usbdev/Kconfig @@ -128,6 +128,52 @@ config USBDEV_TRACE_INITIALIDSET endif # USBDEV_TRACE +menuconfig USBDEV_CUSTOM_TXFIFO_SIZE + bool "Custom TX Fifo size" + default n + ---help--- + Enables custom TX Fifo size + +if USBDEV_CUSTOM_TXFIFO_SIZE + +config USBDEV_EP0_TXFIFO_SIZE + int "USBDEV_EP0_TXFIFO_SIZE" + default 64 + +config USBDEV_EP1_TXFIFO_SIZE + int "USBDEV_EP1_TXFIFO_SIZE" + default 0 + +config USBDEV_EP2_TXFIFO_SIZE + int "USBDEV_EP2_TXFIFO_SIZE" + default 0 + +config USBDEV_EP3_TXFIFO_SIZE + int "USBDEV_EP3_TXFIFO_SIZE" + default 0 + +config USBDEV_EP4_TXFIFO_SIZE + int "USBDEV_EP4_TXFIFO_SIZE" + default 0 + +config USBDEV_EP5_TXFIFO_SIZE + int "USBDEV_EP5_TXFIFO_SIZE" + default 0 + +config USBDEV_EP6_TXFIFO_SIZE + int "USBDEV_EP6_TXFIFO_SIZE" + default 0 + +config USBDEV_EP7_TXFIFO_SIZE + int "USBDEV_EP7_TXFIFO_SIZE" + default 0 + +config USBDEV_EP8_TXFIFO_SIZE + int "USBDEV_EP8_TXFIFO_SIZE" + default 0 + +endif # USBDEV_CUSTOM_TXFIFO_SIZE + comment "USB Device Class Driver Options" menuconfig USBDEV_COMPOSITE @@ -691,12 +737,12 @@ menuconfig RNDIS if RNDIS config RNDIS_COMPOSITE - bool "RNDIS composite support" - default n - depends on USBDEV_COMPOSITE - ---help--- - Configure the RNDIS driver as part of a composite driver - (only if USBDEV_COMPOSITE is also defined) + bool "RNDIS composite support" + default n + depends on USBDEV_COMPOSITE + ---help--- + Configure the RNDIS driver as part of a composite driver + (only if USBDEV_COMPOSITE is also defined) if !RNDIS_COMPOSITE