style fixes

arch/arm/src/stm32l4/stm32l4_gpio.c

@@ -60,6 +60,7 @@
 /****************************************************************************
  * Public Data
  ****************************************************************************/
+
 /* Base addresses for each GPIO block */
 
 const uint32_t g_gpiobase[STM32L4_NPORTS] =
@@ -172,20 +173,32 @@ int stm32l4_configgpio(uint32_t cfgset)
   switch (cfgset & GPIO_MODE_MASK)
     {
       default:
-      case GPIO_INPUT:      /* Input mode */
+
+      /* Input mode */
+
+      case GPIO_INPUT:
         pinmode = GPIO_MODER_INPUT;
         break;
 
-      case GPIO_OUTPUT:     /* General purpose output mode */
+      /* General purpose output mode */
-        stm32l4_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); /* Set the initial output value */
+
+      case GPIO_OUTPUT:
+
+        /* Set the initial output value */
+
+        stm32l4_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
         pinmode = GPIO_MODER_OUTPUT;
         break;
 
-      case GPIO_ALT:        /* Alternate function mode */
+      /* Alternate function mode */
+
+      case GPIO_ALT:
         pinmode = GPIO_MODER_ALT;
         break;
 
-      case GPIO_ANALOG:     /* Analog mode */
+      /* Analog mode */
+
+      case GPIO_ANALOG:
         pinmode = GPIO_MODER_ANALOG;
         break;
     }
@@ -307,17 +320,19 @@ int stm32l4_configgpio(uint32_t cfgset)
 
   putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET);
 
-  /* Otherwise, it is an input pin.  Should it configured as an EXTI interrupt? */
+  /* Otherwise, it is an input pin.  Should it configured as an
+   * EXTI interrupt?
+   */
 
   if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0)
     {
       /* The selection of the EXTI line source is performed through the EXTIx
        * bits in the SYSCFG_EXTICRx registers.
        *
-       * The range of EXTI bit values in STM32L4x6 goes to 0b1000 to support the
+       * The range of EXTI bit values in STM32L4x6 goes to 0b1000 to support
-       * ports up to PI in STM32L496xx devices. For STM32L4x3 the EXTI bit values
+       * the ports up to PI in STM32L496xx devices. For STM32L4x3 the EXTI
-       * end at 0b111 (for PH0, PH1 and PH3 only) and values for non-existent
+       * bit values end at 0b111 (for PH0, PH1 and PH3 only) and values for
-       * ports F and G are reserved.
+       * non-existent ports F and G are reserved.
        */
 
       uint32_t regaddr;
@@ -361,14 +376,15 @@ int stm32l4_configgpio(uint32_t cfgset)
  * Name: stm32l4_unconfiggpio
  *
  * Description:
- *   Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
+ *   Unconfigure a GPIO pin based on bit-encoded description of the pin, set
- *   into default HiZ state (and possibly mark it's unused) and unlock it whether
+ *   it into default HiZ state (and possibly mark it's unused) and unlock it
- *   it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
+ *   whether it was previsouly selected as alternative function
+ *   (GPIO_ALT|GPIO_CNF_AFPP|...).
  *
- *   This is a safety function and prevents hardware from schocks, as unexpected
+ *   This is a safety function and prevents hardware from schocks, as
- *   write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
+ *   unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
- *   operate in PWM mode could produce excessive on-board currents and trigger
+ *   while it should operate in PWM mode could produce excessive on-board
- *   over-current/alarm function.
+ *   currents and trigger over-current/alarm function.
  *
  * Returned Value:
  *  OK on success
@@ -427,7 +443,6 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value)
         }
 
       putreg32(bit, base + STM32L4_GPIO_BSRR_OFFSET);
-
     }
 }
 
@@ -457,5 +472,6 @@ bool stm32l4_gpioread(uint32_t pinset)
       pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
       return ((getreg32(base + STM32L4_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
     }
+
   return 0;
 }