diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index a89d27c09a5..2f719fd2d94 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -7704,7 +7704,7 @@ config STM32_ADC1_DMA config STM32_ADC1_DMA_CFG int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA + depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC range 0 1 default 0 ---help--- @@ -7721,7 +7721,7 @@ config STM32_ADC2_DMA config STM32_ADC2_DMA_CFG int "ADC2 DMA configuration" - depends on STM32_ADC2_DMA + depends on STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC range 0 1 default 0 ---help--- @@ -7738,7 +7738,7 @@ config STM32_ADC3_DMA config STM32_ADC3_DMA_CFG int "ADC3 DMA configuration" - depends on STM32_ADC3_DMA + depends on STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC range 0 1 default 0 ---help--- @@ -7755,7 +7755,7 @@ config STM32_ADC4_DMA config STM32_ADC4_DMA_CFG int "ADC4 DMA configuration" - depends on STM32_ADC4_DMA + depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_V1_BASIC range 0 1 default 0 ---help--- diff --git a/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h index 7804792a847..0f41b9bb770 100644 --- a/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h +++ b/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h @@ -112,6 +112,7 @@ #define GPIO_ADC3_IN5 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN7) #define GPIO_ADC3_IN6 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN8) #define GPIO_ADC3_IN7 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN9) +#define GPIO_ADC3_IN8 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN10) #define GPIO_ADC3_IN9 (GPIO_ANALOG|GPIO_PORTF|GPIO_PIN3) #define GPIO_ADC3_IN10 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0) #define GPIO_ADC3_IN11 (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1) diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index ad791ccae85..f43a6db9b44 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -449,6 +449,14 @@ #define ADC_INJ_MAX_SAMPLES 4 +/* ADC DMA configuration bit support */ + +#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +# define ADC_HAVE_DMACFG 1 +#else +# undef ADC_HAVE_DMACFG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -491,7 +499,9 @@ struct stm32_dev_s #endif #ifdef ADC_HAVE_DMA uint8_t dmachan; /* DMA channel needed by this ADC */ +# ifdef ADC_HAVE_DMACFG uint8_t dmacfg; /* DMA channel configuration, only for ADC IPv2 */ +# endif bool hasdma; /* True: This channel supports DMA */ #endif #ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME @@ -828,7 +838,9 @@ static struct stm32_dev_s g_adcpriv1 = #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, +# endif .hasdma = true, #endif }; @@ -881,7 +893,9 @@ static struct stm32_dev_s g_adcpriv2 = #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, +# endif .hasdma = true, #endif }; @@ -934,7 +948,9 @@ static struct stm32_dev_s g_adcpriv3 = #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, +# endif .hasdma = true, #endif }; @@ -980,7 +996,9 @@ static struct stm32_dev_s g_adcpriv4 = #endif #ifdef ADC4_HAVE_DMA .dmachan = ADC4_DMA_CHAN, +# ifdef ADC_HAVE_DMACFG .dmacfg = CONFIG_STM32_ADC4_DMA_CFG, +# endif .hasdma = true, #endif }; @@ -2551,6 +2569,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) # ifdef ADC_HAVE_DMA if (priv->hasdma) { +# ifdef ADC_HAVE_DMACFG /* Set DMA mode */ if (priv->dmacfg == 0) @@ -2565,6 +2584,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) setbits |= ADC_CR2_DDS; } +# endif /* Enable DMA */ diff --git a/configs/nucleo-f103rb/adc/defconfig b/configs/nucleo-f103rb/adc/defconfig new file mode 100644 index 00000000000..1c29eaaa494 --- /dev/null +++ b/configs/nucleo-f103rb/adc/defconfig @@ -0,0 +1,56 @@ +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=4 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_LINELEN=80 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/nucleo-f103rb/include/board.h b/configs/nucleo-f103rb/include/board.h index 8a8d63b3e1e..f725e5244ae 100644 --- a/configs/nucleo-f103rb/include/board.h +++ b/configs/nucleo-f103rb/include/board.h @@ -101,7 +101,15 @@ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) -/* TODO: timers */ +/* APB2 TIM 1 will receive PCLK2 (72MHz) */ + +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) + +/* APB1 TIM 2-4 will be twice PCLK1 (72MHz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ /* The Nucleo F103RB board has three LEDs. Two of these are controlled by @@ -172,4 +180,9 @@ /* Alternate function pin selections ****************************************/ +/* DMA channels *************************************************************/ +/* ADC */ + +#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */ + #endif /* __CONFIG_NUCLEO_F103RB_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-f103rb/pwm/defconfig b/configs/nucleo-f103rb/pwm/defconfig new file mode 100644 index 00000000000..ee492592135 --- /dev/null +++ b/configs/nucleo-f103rb/pwm/defconfig @@ -0,0 +1,49 @@ +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f103rb" +CONFIG_ARCH_BOARD_NUCLEO_F103RB=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=5483 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=1024 +CONFIG_NSH_LINELEN=80 +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=20480 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2011 +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_FORCEPOWER=y +CONFIG_STM32_JTAG_FULL_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART2=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/nucleo-f103rb/src/Makefile b/configs/nucleo-f103rb/src/Makefile index b39d43a3824..0887a30a748 100644 --- a/configs/nucleo-f103rb/src/Makefile +++ b/configs/nucleo-f103rb/src/Makefile @@ -52,4 +52,12 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/nucleo-f103rb/src/nucleo-f103rb.h b/configs/nucleo-f103rb/src/nucleo-f103rb.h index e2165173b96..1b87dc1a95d 100644 --- a/configs/nucleo-f103rb/src/nucleo-f103rb.h +++ b/configs/nucleo-f103rb/src/nucleo-f103rb.h @@ -86,4 +86,36 @@ #define GPIO_BTN_USER (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13) +/* PWM */ + +#define NUCLEOF103RB_PWMTIMER 1 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F103RB_SRC_NUCLEO_F103RB_H */ diff --git a/configs/nucleo-f103rb/src/stm32_adc.c b/configs/nucleo-f103rb/src/stm32_adc.c new file mode 100644 index 00000000000..451406a5821 --- /dev/null +++ b/configs/nucleo-f103rb/src/stm32_adc.c @@ -0,0 +1,253 @@ +/**************************************************************************** + * configs/nucleo-f103rb/src/stm32_adc.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2) */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC2) +# if defined(DEV1_PORT) +# define DEV2_PORT 2 +# else +# define DEV1_PORT 2 +# endif +#endif + +/* The number of ADC channels in the conversion list */ +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC2_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less) */ + +static const uint8_t g_chanlist1[3] = +{ + 0, + 1, + 4 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC123_IN0, /* PA0/A0 */ + GPIO_ADC123_IN1, /* PA1/A1 */ + GPIO_ADC12_IN4, /* PA4/A2 */ +}; + +#elif DEV1_PORT == 2 + +#define DEV1_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 8, + 11, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC12_IN8, /* PB0/A3 */ + GPIO_ADC123_IN11, /* PC1/A4 */ + GPIO_ADC123_IN10, /* PC0/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 2 + +#define DEV2_NCHANNELS ADC2_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 8, + 11, + 10 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC12_IN8, /* PB0/A3 */ + GPIO_ADC123_IN11, /* PC1/A4 */ + GPIO_ADC123_IN10, /* PC0/A5 */ +}; + +#endif /* DEV2_PORT == 2 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + FAR struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + + /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */ diff --git a/configs/nucleo-f103rb/src/stm32_appinitialize.c b/configs/nucleo-f103rb/src/stm32_appinitialize.c index a4aba43afd4..8ade7c98d74 100644 --- a/configs/nucleo-f103rb/src/stm32_appinitialize.c +++ b/configs/nucleo-f103rb/src/stm32_appinitialize.c @@ -106,6 +106,26 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/configs/nucleo-f103rb/src/stm32_pwm.c b/configs/nucleo-f103rb/src/stm32_pwm.c new file mode 100644 index 00000000000..d45e8dcd711 --- /dev/null +++ b/configs/nucleo-f103rb/src/stm32_pwm.c @@ -0,0 +1,122 @@ +/************************************************************************************ + * configs/nucleo-f103rb/src/stm32_pwm.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_pwm.h" +#include "nucleo-f103rb.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF103RB_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/configs/nucleo-f207zg/adc/defconfig b/configs/nucleo-f207zg/adc/defconfig new file mode 100644 index 00000000000..0bfcd4894ee --- /dev/null +++ b/configs/nucleo-f207zg/adc/defconfig @@ -0,0 +1,50 @@ +CONFIG_ADC=y +CONFIG_ADC_FIFOSIZE=4 +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=3 +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART3=y +CONFIG_SYSLOG_NONE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=1 diff --git a/configs/nucleo-f207zg/include/board.h b/configs/nucleo-f207zg/include/board.h index 7d225f3520f..bda8351e6c5 100644 --- a/configs/nucleo-f207zg/include/board.h +++ b/configs/nucleo-f207zg/include/board.h @@ -107,23 +107,35 @@ #define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */ -/* APB1 clock (PCLK1) is HCLK/2 (50MHz) */ +/* APB1 clock (PCLK1) is HCLK/2 (25MHz) */ -#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) -/* Timers driven from APB1 will be twice PCLK1 */ -/* REVISIT */ +/* APB2 clock (PCLK2) is HCLK/2 (50MHz) */ +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 (100Mhz) */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timers driven from APB1 will be twice PCLK1 (50MHz) */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) - -/* APB2 clock (PCLK2) is HCLK (100MHz) */ - -#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */ -#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY) - -/* TODO: Timers */ +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) /* LED definitions **********************************************************/ /* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue @@ -186,4 +198,20 @@ #define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */ #define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */ +/* PWM configuration ********************************************************/ + +/* TIM1 PWM */ + +#define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_2 /* PE9 */ +#define GPIO_TIM1_CH1NOUT GPIO_TIM1_CH1N_3 /* PE8 */ +#define GPIO_TIM1_CH2OUT GPIO_TIM1_CH2OUT_2 /* PE11 */ +#define GPIO_TIM1_CH2NOUT GPIO_TIM1_CH2N_3 /* PE10 */ +#define GPIO_TIM1_CH3OUT GPIO_TIM1_CH3OUT_2 /* PE13 */ +#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */ + +/* DMA channels *************************************************************/ +/* ADC */ + +#define ADC1_DMA_CHAN DMAMAP_ADC1_1 + #endif /* __CONFIG_NUCLEO_F207ZG_INCLUDE_BOARD_H */ diff --git a/configs/nucleo-f207zg/pwm/defconfig b/configs/nucleo-f207zg/pwm/defconfig new file mode 100644 index 00000000000..7b6676a5cc0 --- /dev/null +++ b/configs/nucleo-f207zg/pwm/defconfig @@ -0,0 +1,44 @@ +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-f207zg" +CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6522 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POLL=y +CONFIG_EXAMPLES_PWM=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INTELHEX_BINARY=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_PWM=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=27 +CONFIG_START_YEAR=2013 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y +CONFIG_SYSLOG_NONE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=1 diff --git a/configs/nucleo-f207zg/src/Makefile b/configs/nucleo-f207zg/src/Makefile index 0b59e78efd1..08d82fc2f9e 100644 --- a/configs/nucleo-f207zg/src/Makefile +++ b/configs/nucleo-f207zg/src/Makefile @@ -52,4 +52,12 @@ ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/nucleo-f207zg/src/nucleo-f207zg.h b/configs/nucleo-f207zg/src/nucleo-f207zg.h index c39f6137fe6..9bc1bb66bf6 100644 --- a/configs/nucleo-f207zg/src/nucleo-f207zg.h +++ b/configs/nucleo-f207zg/src/nucleo-f207zg.h @@ -84,6 +84,10 @@ #define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13) +/* PWM */ + +#define NUCLEOF207ZG_PWMTIMER 1 + /**************************************************************************** * Public Data ****************************************************************************/ @@ -94,4 +98,28 @@ int stm32_bringup(void); +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + +/************************************************************************************ + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ************************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + #endif /* __CONFIGS_NUCLEO_F207ZG_SRC_NUCLEO_F207ZG_H */ diff --git a/configs/nucleo-f207zg/src/stm32_adc.c b/configs/nucleo-f207zg/src/stm32_adc.c new file mode 100644 index 00000000000..221a69d299d --- /dev/null +++ b/configs/nucleo-f207zg/src/stm32_adc.c @@ -0,0 +1,253 @@ +/**************************************************************************** + * configs/nucleo-f303ze/src/stm32_adc.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "stm32.h" + +#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* 1 or 2 ADC devices (DEV1, DEV2). + * ADC1 and ADC3 supported for now. + */ + +#if defined(CONFIG_STM32_ADC1) +# define DEV1_PORT 1 +#endif + +#if defined(CONFIG_STM32_ADC3) +# if defined(DEV1_PORT) +# define DEV2_PORT 3 +# else +# define DEV1_PORT 3 +# endif +#endif + +/* The number of ADC channels in the conversion list */ +/* TODO DMA */ + +#define ADC1_NCHANNELS 3 +#define ADC3_NCHANNELS 3 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* DEV 1 */ + +#if DEV1_PORT == 1 + +#define DEV1_NCHANNELS ADC1_NCHANNELS + +/* Identifying number of each ADC channel (even if NCHANNELS is less ) */ + +static const uint8_t g_chanlist1[3] = +{ + 3, + 10, + 13 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC1_IN3, /* PA3/A0 */ + GPIO_ADC1_IN10, /* PC0/A1 */ + GPIO_ADC1_IN13, /* PC3/A2 */ +}; + +#elif DEV1_PORT == 3 + +#define DEV1_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist1[3] = +{ + 9, + 15, + 8 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist1[3] = +{ + GPIO_ADC3_IN9, /* PF3/A3 */ + GPIO_ADC3_IN15, /* PF5/A4 */ + GPIO_ADC3_IN8, /* PF10/A5 */ +}; + +#endif /* DEV1_PORT == 1 */ + +#ifdef DEV2_PORT + +/* DEV 2 */ + +#if DEV2_PORT == 3 + +#define DEV2_NCHANNELS ADC3_NCHANNELS + +/* Identifying number of each ADC channel */ + +static const uint8_t g_chanlist2[3] = +{ + 9, + 15, + 8 +}; + +/* Configurations of pins used by each ADC channel */ + +static const uint32_t g_pinlist2[3] = +{ + GPIO_ADC3_IN9, /* PF3/A3 */ + GPIO_ADC3_IN15, /* PF5/A4 */ + GPIO_ADC3_IN8, /* PF10/A5 */ +}; + +#endif /* DEV2_PORT == 3 */ +#endif /* DEV2_PORT */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + static bool initialized = false; + FAR struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* DEV1 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist1[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 1\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret); + return ret; + } + +#ifdef DEV2_PORT + /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < DEV2_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist2[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface 2\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc1" */ + + ret = adc_register("/dev/adc1", adc); + if (ret < 0) + { + aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret); + return ret; + } +#endif + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC3) */ diff --git a/configs/nucleo-f207zg/src/stm32_bringup.c b/configs/nucleo-f207zg/src/stm32_bringup.c index 1552951f028..e6856b701b0 100644 --- a/configs/nucleo-f207zg/src/stm32_bringup.c +++ b/configs/nucleo-f207zg/src/stm32_bringup.c @@ -72,7 +72,26 @@ int stm32_bringup(void) { int ret = OK; - UNUSED(ret); +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM driver. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup failed: %d\n", ret); + } +#endif + + UNUSED(ret); return OK; } diff --git a/configs/nucleo-f207zg/src/stm32_pwm.c b/configs/nucleo-f207zg/src/stm32_pwm.c new file mode 100644 index 00000000000..6de04eaa1d0 --- /dev/null +++ b/configs/nucleo-f207zg/src/stm32_pwm.c @@ -0,0 +1,122 @@ +/************************************************************************************ + * configs/nucleo-f207zg/src/stm32_pwm.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "stm32_pwm.h" +#include "nucleo-f207zg.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration *******************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM1_PWM +# undef HAVE_PWM +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ************************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOF207ZG_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/configs/nucleo-f302r8/include/board.h b/configs/nucleo-f302r8/include/board.h index cfabe462672..27925040d94 100644 --- a/configs/nucleo-f302r8/include/board.h +++ b/configs/nucleo-f302r8/include/board.h @@ -216,9 +216,6 @@ #define GPIO_USART2_RX GPIO_USART2_RX_2 /* PA3 */ #define GPIO_USART2_TX GPIO_USART2_TX_2 /* PA2 */ -/* DMA channels *************************************************************/ - - /* PWM configuration ********************************************************/ /* TIM1 PWM */ diff --git a/configs/nucleo-f334r8/src/stm32_adc.c b/configs/nucleo-f334r8/src/stm32_adc.c index f46970cef94..8569e294d07 100644 --- a/configs/nucleo-f334r8/src/stm32_adc.c +++ b/configs/nucleo-f334r8/src/stm32_adc.c @@ -142,7 +142,7 @@ static const uint32_t g_pinlist1[3] = /* Identifying number of each ADC channel */ -static const uint8_t g_chanlist2[1] = +static const uint8_t g_chanlist2[3] = { 1, 6,