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SAMA5 UDPHS: Minor clean-up of STALL logic

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This commit is contained in:
Gregory Nutt
2013-09-23 18:10:41 -06:00
parent a070e748fd
commit 7c767c4ebe
1 changed files with 17 additions and 22 deletions
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arch/arm/src/sama5/sam_udphs.c
+17 -22
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@@ -3597,7 +3597,7 @@ static int sam_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
/* Handle IN (device-to-host) requests. NOTE: If the class device is /* Handle IN (device-to-host) requests. NOTE: If the class device is
* using the bi-directional EP0, then we assume that they intend the EP0 * using the bi-directional EP0, then we assume that they intend the EP0
* IN functionality. * IN functionality (EP0 OUT data receipt does not use requests).
*/ */
else if (USB_ISEPIN(ep->eplog) || epno == EP0) else if (USB_ISEPIN(ep->eplog) || epno == EP0)
@@ -3708,9 +3708,12 @@ static int sam_ep_stall(struct usbdev_ep_s *ep, bool resume)
privep->epstate = UDPHS_EPSTATE_IDLE; privep->epstate = UDPHS_EPSTATE_IDLE;
/* Clear FORCESTALL flag */ /* Clear FORCESTALL request
* REVISIT: Data sheet says to reset toggle to DATA0 only on OUT
* endpoints.
*/
sam_putreg(UDPHS_EPTSTA_TOGGLESQ_MASK | UDPHS_EPTSTA_FRCESTALL, sam_putreg(UDPHS_EPTCLRSTA_TOGGLESQ | UDPHS_EPTCLRSTA_FRCESTALL,
SAM_UDPHS_EPTCLRSTA(epno)); SAM_UDPHS_EPTCLRSTA(epno));
/* Reset endpoint FIFOs */ /* Reset endpoint FIFOs */
@@ -3725,13 +3728,9 @@ static int sam_ep_stall(struct usbdev_ep_s *ep, bool resume)
(void)sam_req_write(priv, privep); (void)sam_req_write(priv, privep);
} }
else
if ((epno == 0 && privep->epstate == UDPHS_EPSTATE_IDLE) ||
USB_ISEPOUT(ep->eplog))
{ {
/* OUT endpoint (or EP0 with no write request started). /* OUT endpoint. Restart any queued read requests. */
* Restart any queued read requests.
*/
(void)sam_req_read(priv, privep, 0); (void)sam_req_read(priv, privep, 0);
} }
@@ -3764,24 +3763,20 @@ static int sam_ep_stall(struct usbdev_ep_s *ep, bool resume)
sam_putreg(UDPHS_EPTSETSTA_FRCESTALL, SAM_UDPHS_EPTSETSTA(epno)); sam_putreg(UDPHS_EPTSETSTA_FRCESTALL, SAM_UDPHS_EPTSETSTA(epno));
/* Enable endpoint/DMA interrupts */ /* Disable endpoint/DMA interrupts. The not be re-enabled until
* the stall is cleared and the next transfer is started. It
* would, of course, be a bad idea to do this on EP0 since it is
* a SETUP request that is going to clear the STALL.
*/
if (epno != 0)
{
regval = sam_getreg(SAM_UDPHS_IEN); regval = sam_getreg(SAM_UDPHS_IEN);
if ((SAM_EPSET_DMA & SAM_EP_BIT(epno)) != 0) regval &= ~(UDPHS_INT_DMA(epno) | UDPHS_INT_EPT(epno));
{
/* Enable the endpoint DMA interrupt */
regval &= ~UDPHS_INT_DMA(epno);
}
else
{
/* Enable the endpoint interrupt */
regval &= ~UDPHS_INT_EPT(epno);
}
sam_putreg(regval, SAM_UDPHS_IEN); sam_putreg(regval, SAM_UDPHS_IEN);
} }
} }
}
irqrestore(flags); irqrestore(flags);
return OK; return OK;