From 7b7da5ded43a8bcfd0f3f41f40a98a695862be74 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Sat, 23 May 2015 11:01:22 -0600
Subject: [PATCH] SAM4L:  Re-order some clock initialization.  There was a
 dependency of GCLK0 on DFLL, but DFLL was being enabled after GCLK0

---
 arch/arm/src/samdl/saml_clockconfig.c | 36 +++++++++++++--------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/src/samdl/saml_clockconfig.c b/arch/arm/src/samdl/saml_clockconfig.c
index c949e46b8f9..edb86611cfd 100644
--- a/arch/arm/src/samdl/saml_clockconfig.c
+++ b/arch/arm/src/samdl/saml_clockconfig.c
@@ -1233,24 +1233,6 @@ static inline void sam_config_gclks(void)
     {
       sam_gclk_config(&g_gclkconfig[i]);
     }
-
-  /* Enable DFLL reference clock if the DFLL is enabled in closed loop mode */
-
-  sam_dfll48m_refclk();
-
-  /* Enable FDPLL reference clock if the DFLL is enabled */
-
-  sam_fdpll96m_refclk();
-
-  /* Setup CPU and BUS clocks */
-
-  sam_cpu_dividers();
-
-  /* Configure the GCLK_MAIN last as it may depend on the DFLL or other
-   * generators
-   */
-
-  sam_gclk_config(&g_gclkconfig[0]);
 }
 #else
 #  define sam_config_gclks()
@@ -1337,14 +1319,32 @@ void sam_clockconfig(void)
 
   sam_config_gclks();
 
+  /* Enable DFLL reference clock if the DFLL is enabled in closed loop mode */
+
+  sam_dfll48m_refclk();
+
   /* Enable DFLL48M */
 
   sam_dfll48m_enable();
 
+  /* Enable FDPLL reference clock if the DFLL is enabled */
+
+  sam_fdpll96m_refclk();
+
   /* Configure and enable FDPLL96M */
 
   sam_fdpll96m_config();
 
+  /* Setup CPU and BUS clocks */
+
+  sam_cpu_dividers();
+
+  /* Configure the GCLK_MAIN last as it may depend on the DFLL, FDPLL or
+   * other generators
+   */
+
+  sam_gclk_config(&g_gclkconfig[0]);
+
 #if BOARD_CPU_FREQUENCY <= 12000000
   /* If CPU frequency is less than 12MHz, scale down performance level to
    * PL0.