Review of previous commit

arch/arm/src/stm32/Kconfig

@@ -2829,8 +2829,6 @@ config STM32_TICKLESS_CHANNEL
 
 endif # SCHED_TICKLESS
 
-if !SCHED_TICKLESS
-
 config STM32_ONESHOT
 	bool "TIM one-shot wrapper"
 	default n
@@ -2845,8 +2843,6 @@ config STM32_FREERUN
 		Enable a wrapper around the low level timer/counter functions to
 		support a free-running timer.
 
-endif # !SCHED_TICKLESS
-
 config STM32_ONESHOT_MAXTIMERS
 	int "Maximum number of oneshot timers"
 	default 1

arch/arm/src/stm32/stm32_tickless.c

@@ -161,7 +161,8 @@ static inline void stm32_putreg16(uint8_t offset, uint16_t value)
  *
  ************************************************************************************/
 
-static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, uint16_t setbits)
+static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits,
+                                     uint16_t setbits)
 {
   modifyreg16(g_tickless.base + offset, clearbits, setbits);
 }
@@ -242,7 +243,10 @@ static int stm32_tickless_setchannel(uint8_t channel)
     }
 #endif
 
-  /* frozen mode because we don't want to change the gpio, preload register disabled */
+  /* Frozen mode because we don't want to change the GPIO, preload register
+   * disabled.
+   */
+
   ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT);
         
   /* Set polarity */
@@ -251,7 +255,7 @@ static int stm32_tickless_setchannel(uint8_t channel)
 
   /* Define its position (shift) and get register offset */
 
-  if (channel & 1)
+  if ((channel & 1) != 0)
     {
       ccmr_val  <<= 8;
       ccmr_mask <<= 8;
@@ -303,7 +307,6 @@ static void stm32_interval_handler(void)
   sched_timer_expiration();
 }
 
-
 /****************************************************************************
  * Name: stm32_timing_handler
  *
@@ -328,7 +331,6 @@ static void stm32_timing_handler(void)
 }
 #endif /* CONFIG_CLOCK_TIMEKEEPING */
 
-
 /****************************************************************************
  * Name: stm32_tickless_handler
  *
@@ -350,11 +352,15 @@ static int stm32_tickless_handler(int irq, void *context, void *arg)
 
 #ifndef CONFIG_CLOCK_TIMEKEEPING
   if (interrupt_flags & ATIM_SR_UIF)
+    {
       stm32_timing_handler();
+    }
 #endif /* CONFIG_CLOCK_TIMEKEEPING */
 
   if (interrupt_flags & (1 << g_tickless.channel))
+    {
       stm32_interval_handler();
+    }
 
   return OK;
 }
@@ -397,16 +403,19 @@ void arm_timer_initialize(void)
         g_tickless.base = STM32_TIM1_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM2
       case 2:
         g_tickless.base = STM32_TIM2_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM3
       case 3:
         g_tickless.base = STM32_TIM3_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM4
       case 4:
         g_tickless.base = STM32_TIM4_BASE;
@@ -417,6 +426,7 @@ void arm_timer_initialize(void)
         g_tickless.base = STM32_TIM5_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM6
       case 6:
 
@@ -425,6 +435,7 @@ void arm_timer_initialize(void)
         ASSERT(0);
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM7
       case 7:
 
@@ -433,11 +444,13 @@ void arm_timer_initialize(void)
         ASSERT(0);
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM8
       case 8:
         g_tickless.base = STM32_TIM8_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM9
       case 9:
         g_tickless.base = STM32_TIM9_BASE;
@@ -448,6 +461,7 @@ void arm_timer_initialize(void)
         g_tickless.base = STM32_TIM10_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM11
       case 11:
         g_tickless.base = STM32_TIM11_BASE;
@@ -463,6 +477,7 @@ void arm_timer_initialize(void)
         g_tickless.base = STM32_TIM13_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM14
       case 14:
         g_tickless.base = STM32_TIM14_BASE;
@@ -473,11 +488,13 @@ void arm_timer_initialize(void)
         g_tickless.base = STM32_TIM15_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM16
       case 16:
         g_tickless.base = STM32_TIM16_BASE;
         break;
 #endif
+
 #ifdef CONFIG_STM32_TIM17
       case 17:
         g_tickless.base = STM32_TIM17_BASE;
@@ -486,7 +503,6 @@ void arm_timer_initialize(void)
 
       default:
         ASSERT(0);
-
     }
 
   /* Get the TC frequency that corresponds to the requested resolution */
@@ -749,6 +765,7 @@ int up_timer_cancel(FAR struct timespec *ts)
           ts->tv_sec  = 0;
           ts->tv_nsec = 0;
         }
+
       leave_critical_section(flags);
       return OK;
     }
@@ -773,7 +790,7 @@ int up_timer_cancel(FAR struct timespec *ts)
    * remaining?
    */
 
-  if (ts)
+  if (ts != NULL)
     {
       /* Yes.. then calculate and return the time remaining on the
        * oneshot timer.
@@ -897,7 +914,8 @@ int up_timer_start(FAR const struct timespec *ts)
 
   g_tickless.period = (uint16_t)(period + count);
  
-  STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, g_tickless.period);
+  STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel,
+                       g_tickless.period);
 
   /* Enable interrupts.  We should get the callback when the interrupt
    * occurs.