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Email address change in nuttx/
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5145 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -2,7 +2,7 @@
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# drivers/analog/Make.defs
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#
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# Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -8,7 +8,7 @@
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* Derived from drivers/can.c
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||||
*
|
||||
* Copyright (C) 2008-2009Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
# drivers/input/Make.defs
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#
|
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# Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -3,7 +3,7 @@
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||||
* Nokia 6100 LCD Display Driver
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||||
*
|
||||
* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
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||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
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* References:
|
||||
* "Nokia 6100 LCD Display Driver," Revision 1, James P. Lynch ("Nokia 6100 LCD
|
||||
|
||||
+151
-151
@@ -1,152 +1,152 @@
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/**************************************************************************************
|
||||
* drivers/lcd/pcf8833.h
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* Definitions for the Phillips PCF8833 LCD controller
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* References: "Data Sheet, PCF8833 STN RGB 132x132x3 driver," Phillips, 2003 Feb 14.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_PCF8833_H
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#define __DRIVERS_LCD_PCF8833_H
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||||
/**************************************************************************************
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||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
/* Pixel format codes */
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||||
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||||
#define PCF8833_FMT_8BPS (2)
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#define PCF8833_FMT_12BPS (3)
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#define PCF8833_FMT_16BPS (5)
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/* LCD Commands */
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||||
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#define PCF8833_NOP 0x00 /* No operation; Data: none */
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||||
#define PCF8833_SWRESET 0x01 /* Software reset ; Data: none */
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||||
#define PCF8833_BSTROFF 0x02 /* Booster voltage off; Data: none */
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||||
#define PCF8833_BSTRON 0x03 /* Booster voltage on; Data: none */
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||||
#define PCF8833_RDDIDIF 0x04 /* Read display identification; Data: none */
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||||
#define PCF8833_RDDST 0x09 /* Read display status; Data: none */
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||||
#define PCF8833_SLEEPIN 0x10 /* Sleep_IN; Data: none */
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||||
#define PCF8833_SLEEPOUT 0x11 /* Sleep_OUT; Data: none */
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||||
#define PCF8833_PTLON 0x12 /* Partial mode on; Data: none */
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||||
#define PCF8833_NORON 0x13 /* Normal Display mode on; Data: none */
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#define PCF8833_INVOFF 0x20 /* Display inversion off; Data: none */
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||||
#define PCF8833_INVON 0x21 /* Display inversion on; Data: none */
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#define PCF8833_DALO 0x22 /* All pixel off; Data: none */
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||||
#define PCF8833_DAL 0x23 /* All pixel on; Data: none */
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||||
#define PCF8833_SETCON 0x25 /* Set contrast; Data: (1) contrast */
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||||
#define PCF8833_DISPOFF 0x28 /* Display off; Data: none */
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||||
#define PCF8833_DISPON 0x29 /* Display on; Data: none */
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||||
#define PCF8833_CASET 0x2a /* Column address set; Data: (1) X start (2) X end */
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||||
#define PCF8833_PASET 0x2b /* Page address set Data: (1) Y start (2) Y end */
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||||
#define PCF8833_RAMWR 0x2c /* Memory write; Data: (1) write data */
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||||
#define PCF8833_RGBSET 0x2d /* Colour set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */
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#define PCF8833_PTLAR 0x30 /* Partial area; Data: (1) start address (2) end address */
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#define PCF8833_VSCRDEF 0x33 /* Vertical scroll definition; Data: (1) top fixed, (2) scrol area, (3) bottom fixed */
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#define PCF8833_TEOFF 0x34 /* Tearing line off; Data: none */
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#define PCF8833_TEON 0x35 /* Tearing line on; Data: (1) don't care */
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#define PCF8833_MADCTL 0x36 /* Memory data access control; Data: (1) access control settings */
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||||
#define PCF8833_SEP 0x37 /* Set Scroll Entry Point; Data: (1) scroll entry point */
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||||
#define PCF8833_IDMOFF 0x38 /* Idle mode off; Data: none */
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#define PCF8833_IDMON 0x39 /* Idle mode on; Data: none */
|
||||
#define PCF8833_COLMOD 0x3a /* Interface pixel format; Data: (1) color interface format */
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||||
#define PCF8833_SETVOP 0xb0 /* Set VOP; Data: (1) VOP5-8 (2) VOP0-4 */
|
||||
#define PCF8833_BRS 0xb4 /* Bottom Row Swap; Data: none */
|
||||
#define PCF8833_TRS 0xb6 /* Top Row Swap; Data: none */
|
||||
#define PCF8833_FINV 0xb9 /* Super Frame INVersion; Data: none */
|
||||
#define PCF8833_DOR 0xba /* Data ORder; Data: none */
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||||
#define PCF8833_TCDFE 0xbd /* Enable/disable DF temp comp; Data: none */
|
||||
#define PCF8833_TCVOPE 0xbf /* Enable or disable VOP temp comp; Data: none */
|
||||
#define PCF8833_EC 0xc0 /* Internal or external oscillator; Data: none */
|
||||
#define PCF8833_SETMUL 0xc2 /* Set multiplication factor; Data: (1) Multiplication factor */
|
||||
#define PCF8833_TCVOPAB 0xc3 /* Set TCVOP slopes A and B; Data: (1) SLB and SLA */
|
||||
#define PCF8833_TCVOPCD 0xc4 /* Set TCVOP slopes C and D; Data: (1) SLD and SLC */
|
||||
#define PCF8833_TCDF 0xc5 /* Set divider frequency; Data: Divider factor in region (1) A (2) B (3) C (4) D */
|
||||
#define PCF8833_DF8COLOR 0xc6 /* Set divider frequency 8-colour mode; Data: (1) DF80-6 */
|
||||
#define PCF8833_SETBS 0xc7 /* Set bias system; Data: (1) Bias systems */
|
||||
#define PCF8833_RDTEMP 0xc8 /* Temperature read back; Data: none */
|
||||
#define PCF8833_NLI 0xc9 /* N-Line Inversion; Data: (1) NLI time slots invervsion */
|
||||
#define PCF8833_RDID1 0xda /* Read ID1; Data: none */
|
||||
#define PCF8833_RDID2 0xdb /* Read ID2; Data: none */
|
||||
#define PCF8833_RDID3 0xdc /* Read ID3; Data: none */
|
||||
#define PCF8833_SFD 0xef /* Select factory defaults; Data: none */
|
||||
#define PCF8833_ECM 0xf0 /* Enter Calibration mode; Data: (1) Calibration control settings */
|
||||
#define PCF8833_OTPSHTIN 0xf1 /* Shift data in OTP shift registers; Data: Any number of bytes */
|
||||
|
||||
/* Memory data access control (MADCTL) bit definitions */
|
||||
|
||||
#define MADCTL_RGB (1 << 3) /* Bit 3: BGR */
|
||||
#define MADCTL_LAO (1 << 4) /* Bit 4: Line address order bottom to top */
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||||
#define MADCTL_V (1 << 5) /* Bit 5: Vertical RAM write; in Y direction */
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#define MADCTL_MX (1 << 6) /* Bit 6: Mirror X */
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#define MADCTL_MY (1 << 7) /* Bit 7: Mirror Y */
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||||
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||||
/* PCF8833 status register bit definitions */
|
||||
/* CMD format: RDDST command followed by four status bytes: */
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/* Byte 1: D31 d30 D29 D28 D27 D26 --- --- */
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||||
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#define PCF8833_ST_RGB (1 << 2) /* Bit 2: D26 - RGB/BGR order */
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||||
#define PCF8833_ST_LINEADDR (1 << 3) /* Bit 3: D27 - Line address order */
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#define PCF8833_ST_ADDRMODE (1 << 4) /* Bit 4: D28 - Vertical/horizontal addressing mode */
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#define PCF8833_ST_XADDR (1 << 5) /* Bit 5: D29 - X address order */
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#define PCF8833_ST_YADDR (1 << 6) /* Bit 6: D30 - Y address order */
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#define PCF8833_ST_BOOSTER (1 << 7) /* Bit 7: D31 - Booster voltage status */
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/* Byte 2: --- D22 D21 D20 D19 D18 D17 D16 */
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#define PCF8833_ST_NORMAL (1 << 0) /* Bit 0: D16 - Normal display mode */
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#define PCF8833_ST_SLEEPIN (1 << 1) /* Bit 1: D17 - Sleep in selected */
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#define PCF8833_ST_PARTIAL (1 << 2) /* Bit 2: D18 - Partial mode on */
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#define PCF8833_ST_IDLE (1 << 3) /* Bit 3: D19 - Idle mode selected */
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#define PCF8833_ST_PIXELFMT_SHIFT (4) /* Bits 4-6: D20-D22 - Interface pixel format */
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#define PCF8833_ST_PIXELFMT_MASK (7 << PCF8833_ST_PIXELFMT_SHIFT)
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# define PCF8833_ST_PIXELFMT_8BPS (PCF8833_FMT_8BPS << PCF8833_ST_PIXELFMT_SHIFT)
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# define PCF8833_ST_PIXELFMT_12BPS (PCF8833_FMT_12BPS << PCF8833_ST_PIXELFMT_SHIFT)
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# define PCF8833_ST_PIXELFMT_16BPS (PCF8833_FMT_16BPS << PCF8833_ST_PIXELFMT_SHIFT)
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||||
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/* Byte 3: D15 -- D13 D12 D11 D10 D9 --- */
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||||
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||||
#define PCF8833_ST_TEARING (1 << 1) /* Bit 1: D9 - Tearing effect on */
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#define PCF8833_ST_DISPLAYON (1 << 2) /* Bit 2: D10 - Display on */
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#define PCF8833_ST_PIXELSOFF (1 << 3) /* Bit 3: D11 - All pixels off */
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#define PCF8833_ST_PIXELSON (1 << 4) /* Bit 4: D12 - All pixels on */
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#define PCF8833_ST_INV (1 << 5) /* Bit 5: D13 - Display inversion */
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#define PCF8833_ST_VSCROLL (1 << 7) /* Bit 6: D15 - Vertical scroll mode */
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/* Byte 4: All zero */
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/**************************************************************************************
|
||||
* drivers/lcd/pcf8833.h
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||||
* Definitions for the Phillips PCF8833 LCD controller
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: "Data Sheet, PCF8833 STN RGB 132x132x3 driver," Phillips, 2003 Feb 14.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_PCF8833_H
|
||||
#define __DRIVERS_LCD_PCF8833_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
/* Pixel format codes */
|
||||
|
||||
#define PCF8833_FMT_8BPS (2)
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#define PCF8833_FMT_12BPS (3)
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#define PCF8833_FMT_16BPS (5)
|
||||
|
||||
/* LCD Commands */
|
||||
|
||||
#define PCF8833_NOP 0x00 /* No operation; Data: none */
|
||||
#define PCF8833_SWRESET 0x01 /* Software reset ; Data: none */
|
||||
#define PCF8833_BSTROFF 0x02 /* Booster voltage off; Data: none */
|
||||
#define PCF8833_BSTRON 0x03 /* Booster voltage on; Data: none */
|
||||
#define PCF8833_RDDIDIF 0x04 /* Read display identification; Data: none */
|
||||
#define PCF8833_RDDST 0x09 /* Read display status; Data: none */
|
||||
#define PCF8833_SLEEPIN 0x10 /* Sleep_IN; Data: none */
|
||||
#define PCF8833_SLEEPOUT 0x11 /* Sleep_OUT; Data: none */
|
||||
#define PCF8833_PTLON 0x12 /* Partial mode on; Data: none */
|
||||
#define PCF8833_NORON 0x13 /* Normal Display mode on; Data: none */
|
||||
#define PCF8833_INVOFF 0x20 /* Display inversion off; Data: none */
|
||||
#define PCF8833_INVON 0x21 /* Display inversion on; Data: none */
|
||||
#define PCF8833_DALO 0x22 /* All pixel off; Data: none */
|
||||
#define PCF8833_DAL 0x23 /* All pixel on; Data: none */
|
||||
#define PCF8833_SETCON 0x25 /* Set contrast; Data: (1) contrast */
|
||||
#define PCF8833_DISPOFF 0x28 /* Display off; Data: none */
|
||||
#define PCF8833_DISPON 0x29 /* Display on; Data: none */
|
||||
#define PCF8833_CASET 0x2a /* Column address set; Data: (1) X start (2) X end */
|
||||
#define PCF8833_PASET 0x2b /* Page address set Data: (1) Y start (2) Y end */
|
||||
#define PCF8833_RAMWR 0x2c /* Memory write; Data: (1) write data */
|
||||
#define PCF8833_RGBSET 0x2d /* Colour set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */
|
||||
#define PCF8833_PTLAR 0x30 /* Partial area; Data: (1) start address (2) end address */
|
||||
#define PCF8833_VSCRDEF 0x33 /* Vertical scroll definition; Data: (1) top fixed, (2) scrol area, (3) bottom fixed */
|
||||
#define PCF8833_TEOFF 0x34 /* Tearing line off; Data: none */
|
||||
#define PCF8833_TEON 0x35 /* Tearing line on; Data: (1) don't care */
|
||||
#define PCF8833_MADCTL 0x36 /* Memory data access control; Data: (1) access control settings */
|
||||
#define PCF8833_SEP 0x37 /* Set Scroll Entry Point; Data: (1) scroll entry point */
|
||||
#define PCF8833_IDMOFF 0x38 /* Idle mode off; Data: none */
|
||||
#define PCF8833_IDMON 0x39 /* Idle mode on; Data: none */
|
||||
#define PCF8833_COLMOD 0x3a /* Interface pixel format; Data: (1) color interface format */
|
||||
#define PCF8833_SETVOP 0xb0 /* Set VOP; Data: (1) VOP5-8 (2) VOP0-4 */
|
||||
#define PCF8833_BRS 0xb4 /* Bottom Row Swap; Data: none */
|
||||
#define PCF8833_TRS 0xb6 /* Top Row Swap; Data: none */
|
||||
#define PCF8833_FINV 0xb9 /* Super Frame INVersion; Data: none */
|
||||
#define PCF8833_DOR 0xba /* Data ORder; Data: none */
|
||||
#define PCF8833_TCDFE 0xbd /* Enable/disable DF temp comp; Data: none */
|
||||
#define PCF8833_TCVOPE 0xbf /* Enable or disable VOP temp comp; Data: none */
|
||||
#define PCF8833_EC 0xc0 /* Internal or external oscillator; Data: none */
|
||||
#define PCF8833_SETMUL 0xc2 /* Set multiplication factor; Data: (1) Multiplication factor */
|
||||
#define PCF8833_TCVOPAB 0xc3 /* Set TCVOP slopes A and B; Data: (1) SLB and SLA */
|
||||
#define PCF8833_TCVOPCD 0xc4 /* Set TCVOP slopes C and D; Data: (1) SLD and SLC */
|
||||
#define PCF8833_TCDF 0xc5 /* Set divider frequency; Data: Divider factor in region (1) A (2) B (3) C (4) D */
|
||||
#define PCF8833_DF8COLOR 0xc6 /* Set divider frequency 8-colour mode; Data: (1) DF80-6 */
|
||||
#define PCF8833_SETBS 0xc7 /* Set bias system; Data: (1) Bias systems */
|
||||
#define PCF8833_RDTEMP 0xc8 /* Temperature read back; Data: none */
|
||||
#define PCF8833_NLI 0xc9 /* N-Line Inversion; Data: (1) NLI time slots invervsion */
|
||||
#define PCF8833_RDID1 0xda /* Read ID1; Data: none */
|
||||
#define PCF8833_RDID2 0xdb /* Read ID2; Data: none */
|
||||
#define PCF8833_RDID3 0xdc /* Read ID3; Data: none */
|
||||
#define PCF8833_SFD 0xef /* Select factory defaults; Data: none */
|
||||
#define PCF8833_ECM 0xf0 /* Enter Calibration mode; Data: (1) Calibration control settings */
|
||||
#define PCF8833_OTPSHTIN 0xf1 /* Shift data in OTP shift registers; Data: Any number of bytes */
|
||||
|
||||
/* Memory data access control (MADCTL) bit definitions */
|
||||
|
||||
#define MADCTL_RGB (1 << 3) /* Bit 3: BGR */
|
||||
#define MADCTL_LAO (1 << 4) /* Bit 4: Line address order bottom to top */
|
||||
#define MADCTL_V (1 << 5) /* Bit 5: Vertical RAM write; in Y direction */
|
||||
#define MADCTL_MX (1 << 6) /* Bit 6: Mirror X */
|
||||
#define MADCTL_MY (1 << 7) /* Bit 7: Mirror Y */
|
||||
|
||||
/* PCF8833 status register bit definitions */
|
||||
/* CMD format: RDDST command followed by four status bytes: */
|
||||
/* Byte 1: D31 d30 D29 D28 D27 D26 --- --- */
|
||||
|
||||
#define PCF8833_ST_RGB (1 << 2) /* Bit 2: D26 - RGB/BGR order */
|
||||
#define PCF8833_ST_LINEADDR (1 << 3) /* Bit 3: D27 - Line address order */
|
||||
#define PCF8833_ST_ADDRMODE (1 << 4) /* Bit 4: D28 - Vertical/horizontal addressing mode */
|
||||
#define PCF8833_ST_XADDR (1 << 5) /* Bit 5: D29 - X address order */
|
||||
#define PCF8833_ST_YADDR (1 << 6) /* Bit 6: D30 - Y address order */
|
||||
#define PCF8833_ST_BOOSTER (1 << 7) /* Bit 7: D31 - Booster voltage status */
|
||||
|
||||
/* Byte 2: --- D22 D21 D20 D19 D18 D17 D16 */
|
||||
|
||||
#define PCF8833_ST_NORMAL (1 << 0) /* Bit 0: D16 - Normal display mode */
|
||||
#define PCF8833_ST_SLEEPIN (1 << 1) /* Bit 1: D17 - Sleep in selected */
|
||||
#define PCF8833_ST_PARTIAL (1 << 2) /* Bit 2: D18 - Partial mode on */
|
||||
#define PCF8833_ST_IDLE (1 << 3) /* Bit 3: D19 - Idle mode selected */
|
||||
#define PCF8833_ST_PIXELFMT_SHIFT (4) /* Bits 4-6: D20-D22 - Interface pixel format */
|
||||
#define PCF8833_ST_PIXELFMT_MASK (7 << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
# define PCF8833_ST_PIXELFMT_8BPS (PCF8833_FMT_8BPS << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
# define PCF8833_ST_PIXELFMT_12BPS (PCF8833_FMT_12BPS << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
# define PCF8833_ST_PIXELFMT_16BPS (PCF8833_FMT_16BPS << PCF8833_ST_PIXELFMT_SHIFT)
|
||||
|
||||
/* Byte 3: D15 -- D13 D12 D11 D10 D9 --- */
|
||||
|
||||
#define PCF8833_ST_TEARING (1 << 1) /* Bit 1: D9 - Tearing effect on */
|
||||
#define PCF8833_ST_DISPLAYON (1 << 2) /* Bit 2: D10 - Display on */
|
||||
#define PCF8833_ST_PIXELSOFF (1 << 3) /* Bit 3: D11 - All pixels off */
|
||||
#define PCF8833_ST_PIXELSON (1 << 4) /* Bit 4: D12 - All pixels on */
|
||||
#define PCF8833_ST_INV (1 << 5) /* Bit 5: D13 - Display inversion */
|
||||
#define PCF8833_ST_VSCROLL (1 << 7) /* Bit 6: D15 - Vertical scroll mode */
|
||||
|
||||
/* Byte 4: All zero */
|
||||
|
||||
#endif /* __DRIVERS_LCD_PCF8833_H */
|
||||
+140
-140
@@ -1,141 +1,141 @@
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/s1d15g10.h
|
||||
* Definitions for the Epson S1D15G0 LCD controller
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* References: S1D15G0D08B000, Seiko Epson Corportation, 2002.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_S1D15G10_H
|
||||
#define __DRIVERS_LCD_S1D15G10_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
|
||||
/* Epson S1D15G10 Command Set */
|
||||
|
||||
#define S1D15G10_DISON 0xaf /* Display on; Data: none */
|
||||
#define S1D15G10_DISOFF 0xae /* Display off; Data: none */
|
||||
#define S1D15G10_DISNOR 0xa6 /* Normal display; Data: none */
|
||||
#define S1D15G10_DISINV 0xa7 /* Inverse display; Data: none */
|
||||
#define S1D15G10_COMSCN 0xbb /* Common scan direction; Data: (1) common scan direction */
|
||||
#define S1D15G10_DISCTL 0xca /* Display control; Data: Data: (1) CL div, F1/2 pat, (2) duty, (3) FR inverse (4) dispersion */
|
||||
#define S1D15G10_SLPIN 0x95 /* Sleep in; Data: none */
|
||||
#define S1D15G10_SLPOUT 0x94 /* Sleep out; Data: none */
|
||||
#define S1D15G10_PASET 0x75 /* Page address set; Data: (1) start page, (2) end page */
|
||||
#define S1D15G10_CASET 0x15 /* Column address set; Data: (1) start addr, (2) end addr */
|
||||
#define S1D15G10_DATCTL 0xbc /* Data scan direction, etc.; Data: (1) inverse, scan dir (2) RGB, (3) gray-scale */
|
||||
#define S1D15G10_RGBSET8 0xce /* 256-color position set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */
|
||||
#define S1D15G10_RAMWR 0x5c /* Writing to memory; Data: (1) write data */
|
||||
#define S1D15G10_RAMRD 0x5d /* Reading from memory; Data: (1) read data */
|
||||
#define S1D15G10_PTLIN 0xa8 /* Partial display in; Data: (1) start addr, (2) end addr */
|
||||
#define S1D15G10_PTLOUT 0xa9 /* Partial display out; Data: none */
|
||||
#define S1D15G10_RMWIN 0xe0 /* Read and modify write; Data: none */
|
||||
#define S1D15G10_RMWOUT 0xee /* End; Data: none */
|
||||
#define S1D15G10_ASCSET 0xaa /* Area scroll set; Data: (1) top addr, (2) bottom addr, (3) Num blocks, (4) scroll mode */
|
||||
#define S1D15G10_SCSTART 0xab /* Scroll start set; Data: (1) start block addr */
|
||||
#define S1D15G10_OSCON 0xd1 /* Internal oscillation on; Data: none */
|
||||
#define S1D15G10_OSCOFF 0xd2 /* Internal oscillation off; Data: none */
|
||||
#define S1D15G10_PWRCTR 0x20 /* Power control; Data: (1) LCD drive power */
|
||||
#define S1D15G10_VOLCTR 0x81 /* Electronic volume control; Data: (1) volume value, (2) resistance ratio */
|
||||
#define S1D15G10_VOLUP 0xd6 /* Increment electronic control by 1; Data: none */
|
||||
#define S1D15G10_VOLDOWN 0xd7 /* Decrement electronic control by 1; Data: none */
|
||||
#define S1D15G10_TMPGRD 0x82 /* Temperature gradient set; Data: (1-14) temperature gradient */
|
||||
#define S1D15G10_EPCTIN 0xcd /* Control EEPROM; Data: (1) read/write */
|
||||
#define S1D15G10_EPCOUT 0xcc /* Cancel EEPROM control; Data: none */
|
||||
#define S1D15G10_EPMWR 0xfc /* Write into EEPROM; Data: none */
|
||||
#define S1D15G10_EPMRD 0xfd /* Read from EEPROM; Data: none */
|
||||
#define S1D15G10_EPSRRD1 0x7c /* Read register 1; Data: none */
|
||||
#define S1D15G10_EPSRRD2 0x7d /* Read regiser 2; Data: none */
|
||||
#define S1D15G10_NOP 0x25 /* NOP intruction (0x45?); Data: none */
|
||||
#define S1D15G10_STREAD 0x20 /* Status read; Data: none */
|
||||
|
||||
/* Display control (DISCTL) bit definitions */
|
||||
|
||||
#define DISCTL_PERIOD_SHIFT (0) /* P1: Bits 0-1, F1 and F2 drive-pattern switching period */
|
||||
#define DISCTL_PERIOD_MASK (3 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_8 (0 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_4 (1 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_16 (2 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_FLD (3 << DISCTL_PERIOD_SHIFT)
|
||||
#define DISCTL_CLDIV_SHIFT (2) /* P1: Bits 2-4, Clock divider */
|
||||
#define DISCTL_CLDIV_MASK (7 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_2 (0 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_4 (1 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_8 (2 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_NONE (3 << DISCTL_CLDIV_SHIFT)
|
||||
|
||||
/* Power control (PWRCTR) bit definitions */
|
||||
|
||||
#define PWCTR_REFVOLTAGE (1 << 0) /* P1: Bit 0, Turn on reference voltage generation circuit. */
|
||||
#define PWCTR_REGULATOR (1 << 1) /* P1: Bit 1, Turn on voltage regulator and circuit voltage follower. */
|
||||
#define PWCTR_BOOSTER2 (1 << 2) /* P1: Bit 2, Turn on secondary booster/step-down circuit. */
|
||||
#define PWCTR_BOOSTER1 (1 << 3) /* P1: Bit 3, Turn on primary booster circuit. */
|
||||
#define PWCTR_EXTR (1 << 4) /* P1: Bit 4, Use external resistance to adjust voltage. */
|
||||
|
||||
/* Data control (DATCTL) bit definitions */
|
||||
|
||||
#define DATCTL_PGADDR_INV (1 << 0) /* P1: Bit 0, Inverse display of the page address. */
|
||||
#define DATCTL_COLADDR_REV (1 << 1) /* P1: Bit 1, Reverse turn of column address. */
|
||||
#define DATCTL_ADDR_PGDIR (1 << 2) /* P1: Bit 2, Address-scan direction in page (vs column) direction. */
|
||||
|
||||
#define DATCTL_BGR (1 << 0) /* P2: Bit0, RGB->BGR */
|
||||
|
||||
#define DATCTL_8GRAY (1) /* P3: Bits 0-2 = 001, 8 gray-scale */
|
||||
#define DATCTL_16GRAY_A (2) /* P3: Bits 0-2 = 010, 16 gray-scale display type A */
|
||||
#define DATCTL_16GRAY_B (4) /* P3: Bits 0-2 = 100, 16 gray-scale display type B */
|
||||
|
||||
/* Status register bit definions (after reset or NOP) */
|
||||
|
||||
#define S1D15G10_SR_PARTIAL (1 << 0) /* Bit 0: Partial display */
|
||||
#define S1D15G10_SR_NORMAL (1 << 1) /* Bit 1: Normal (vs. inverse) display */
|
||||
#define S1D15G10_SR_EEPROM (1 << 2) /* Bit 2: EEPROM access */
|
||||
#define S1D15G10_SR_DISPON (1 << 3) /* Bit 3: Display on */
|
||||
#define S1D15G10_SR_COLSCAN (1 << 4) /* Bit 4: Column (vs. page) scan direction */
|
||||
#define S1D15G10_SR_RMW (1 << 5) /* Bit 5: Read modify write */
|
||||
#define S1D15G10_SR_SCROLL (3 << 6) /* Bits 6-7: Area scroll mode */
|
||||
|
||||
/* Status register bit definions (after EPSRRD1) */
|
||||
|
||||
#define S1D15G10_SR_VOLUME 0x3f /* Bits 0-5: Electronic volume control values */
|
||||
|
||||
/* Status register bit definions (after EPSRRD2) */
|
||||
|
||||
#define S1D15G10_SR_RRATIO 0x07 /* Bits 0-2: Built-in resistance ratio */
|
||||
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/s1d15g10.h
|
||||
* Definitions for the Epson S1D15G0 LCD controller
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: S1D15G0D08B000, Seiko Epson Corportation, 2002.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_S1D15G10_H
|
||||
#define __DRIVERS_LCD_S1D15G10_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
|
||||
/* Epson S1D15G10 Command Set */
|
||||
|
||||
#define S1D15G10_DISON 0xaf /* Display on; Data: none */
|
||||
#define S1D15G10_DISOFF 0xae /* Display off; Data: none */
|
||||
#define S1D15G10_DISNOR 0xa6 /* Normal display; Data: none */
|
||||
#define S1D15G10_DISINV 0xa7 /* Inverse display; Data: none */
|
||||
#define S1D15G10_COMSCN 0xbb /* Common scan direction; Data: (1) common scan direction */
|
||||
#define S1D15G10_DISCTL 0xca /* Display control; Data: Data: (1) CL div, F1/2 pat, (2) duty, (3) FR inverse (4) dispersion */
|
||||
#define S1D15G10_SLPIN 0x95 /* Sleep in; Data: none */
|
||||
#define S1D15G10_SLPOUT 0x94 /* Sleep out; Data: none */
|
||||
#define S1D15G10_PASET 0x75 /* Page address set; Data: (1) start page, (2) end page */
|
||||
#define S1D15G10_CASET 0x15 /* Column address set; Data: (1) start addr, (2) end addr */
|
||||
#define S1D15G10_DATCTL 0xbc /* Data scan direction, etc.; Data: (1) inverse, scan dir (2) RGB, (3) gray-scale */
|
||||
#define S1D15G10_RGBSET8 0xce /* 256-color position set; Data: (1-8) red tones, (9-16) green tones, (17-20) blue tones */
|
||||
#define S1D15G10_RAMWR 0x5c /* Writing to memory; Data: (1) write data */
|
||||
#define S1D15G10_RAMRD 0x5d /* Reading from memory; Data: (1) read data */
|
||||
#define S1D15G10_PTLIN 0xa8 /* Partial display in; Data: (1) start addr, (2) end addr */
|
||||
#define S1D15G10_PTLOUT 0xa9 /* Partial display out; Data: none */
|
||||
#define S1D15G10_RMWIN 0xe0 /* Read and modify write; Data: none */
|
||||
#define S1D15G10_RMWOUT 0xee /* End; Data: none */
|
||||
#define S1D15G10_ASCSET 0xaa /* Area scroll set; Data: (1) top addr, (2) bottom addr, (3) Num blocks, (4) scroll mode */
|
||||
#define S1D15G10_SCSTART 0xab /* Scroll start set; Data: (1) start block addr */
|
||||
#define S1D15G10_OSCON 0xd1 /* Internal oscillation on; Data: none */
|
||||
#define S1D15G10_OSCOFF 0xd2 /* Internal oscillation off; Data: none */
|
||||
#define S1D15G10_PWRCTR 0x20 /* Power control; Data: (1) LCD drive power */
|
||||
#define S1D15G10_VOLCTR 0x81 /* Electronic volume control; Data: (1) volume value, (2) resistance ratio */
|
||||
#define S1D15G10_VOLUP 0xd6 /* Increment electronic control by 1; Data: none */
|
||||
#define S1D15G10_VOLDOWN 0xd7 /* Decrement electronic control by 1; Data: none */
|
||||
#define S1D15G10_TMPGRD 0x82 /* Temperature gradient set; Data: (1-14) temperature gradient */
|
||||
#define S1D15G10_EPCTIN 0xcd /* Control EEPROM; Data: (1) read/write */
|
||||
#define S1D15G10_EPCOUT 0xcc /* Cancel EEPROM control; Data: none */
|
||||
#define S1D15G10_EPMWR 0xfc /* Write into EEPROM; Data: none */
|
||||
#define S1D15G10_EPMRD 0xfd /* Read from EEPROM; Data: none */
|
||||
#define S1D15G10_EPSRRD1 0x7c /* Read register 1; Data: none */
|
||||
#define S1D15G10_EPSRRD2 0x7d /* Read regiser 2; Data: none */
|
||||
#define S1D15G10_NOP 0x25 /* NOP intruction (0x45?); Data: none */
|
||||
#define S1D15G10_STREAD 0x20 /* Status read; Data: none */
|
||||
|
||||
/* Display control (DISCTL) bit definitions */
|
||||
|
||||
#define DISCTL_PERIOD_SHIFT (0) /* P1: Bits 0-1, F1 and F2 drive-pattern switching period */
|
||||
#define DISCTL_PERIOD_MASK (3 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_8 (0 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_4 (1 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_16 (2 << DISCTL_PERIOD_SHIFT)
|
||||
# define DISCTL_PERIOD_FLD (3 << DISCTL_PERIOD_SHIFT)
|
||||
#define DISCTL_CLDIV_SHIFT (2) /* P1: Bits 2-4, Clock divider */
|
||||
#define DISCTL_CLDIV_MASK (7 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_2 (0 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_4 (1 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_8 (2 << DISCTL_CLDIV_SHIFT)
|
||||
# define DISCTL_CLDIV_NONE (3 << DISCTL_CLDIV_SHIFT)
|
||||
|
||||
/* Power control (PWRCTR) bit definitions */
|
||||
|
||||
#define PWCTR_REFVOLTAGE (1 << 0) /* P1: Bit 0, Turn on reference voltage generation circuit. */
|
||||
#define PWCTR_REGULATOR (1 << 1) /* P1: Bit 1, Turn on voltage regulator and circuit voltage follower. */
|
||||
#define PWCTR_BOOSTER2 (1 << 2) /* P1: Bit 2, Turn on secondary booster/step-down circuit. */
|
||||
#define PWCTR_BOOSTER1 (1 << 3) /* P1: Bit 3, Turn on primary booster circuit. */
|
||||
#define PWCTR_EXTR (1 << 4) /* P1: Bit 4, Use external resistance to adjust voltage. */
|
||||
|
||||
/* Data control (DATCTL) bit definitions */
|
||||
|
||||
#define DATCTL_PGADDR_INV (1 << 0) /* P1: Bit 0, Inverse display of the page address. */
|
||||
#define DATCTL_COLADDR_REV (1 << 1) /* P1: Bit 1, Reverse turn of column address. */
|
||||
#define DATCTL_ADDR_PGDIR (1 << 2) /* P1: Bit 2, Address-scan direction in page (vs column) direction. */
|
||||
|
||||
#define DATCTL_BGR (1 << 0) /* P2: Bit0, RGB->BGR */
|
||||
|
||||
#define DATCTL_8GRAY (1) /* P3: Bits 0-2 = 001, 8 gray-scale */
|
||||
#define DATCTL_16GRAY_A (2) /* P3: Bits 0-2 = 010, 16 gray-scale display type A */
|
||||
#define DATCTL_16GRAY_B (4) /* P3: Bits 0-2 = 100, 16 gray-scale display type B */
|
||||
|
||||
/* Status register bit definions (after reset or NOP) */
|
||||
|
||||
#define S1D15G10_SR_PARTIAL (1 << 0) /* Bit 0: Partial display */
|
||||
#define S1D15G10_SR_NORMAL (1 << 1) /* Bit 1: Normal (vs. inverse) display */
|
||||
#define S1D15G10_SR_EEPROM (1 << 2) /* Bit 2: EEPROM access */
|
||||
#define S1D15G10_SR_DISPON (1 << 3) /* Bit 3: Display on */
|
||||
#define S1D15G10_SR_COLSCAN (1 << 4) /* Bit 4: Column (vs. page) scan direction */
|
||||
#define S1D15G10_SR_RMW (1 << 5) /* Bit 5: Read modify write */
|
||||
#define S1D15G10_SR_SCROLL (3 << 6) /* Bits 6-7: Area scroll mode */
|
||||
|
||||
/* Status register bit definions (after EPSRRD1) */
|
||||
|
||||
#define S1D15G10_SR_VOLUME 0x3f /* Bits 0-5: Electronic volume control values */
|
||||
|
||||
/* Status register bit definions (after EPSRRD2) */
|
||||
|
||||
#define S1D15G10_SR_RRATIO 0x07 /* Bits 0-2: Built-in resistance ratio */
|
||||
|
||||
#endif /* __DRIVERS_LCD_S1D15G10_H */
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/lcd/skeleton.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
+211
-211
@@ -1,211 +1,211 @@
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/ssd1305.h
|
||||
* Definitions for the Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED
|
||||
* Segment/Common Driver with C
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* References: SSD1305.pdf, "Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED
|
||||
* Segment/Common Driver with Controller," Solomon Systech Limited,
|
||||
* http://www.solomon-systech.com, May, 2008.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_SSD1305_H
|
||||
#define __DRIVERS_LCD_SSD1305_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
/* General Definitions ******************************************************/
|
||||
|
||||
#define SSD1305_COLORA 0
|
||||
#define SSD1305_COLORB 1
|
||||
#define SSD1305_COLORC 2
|
||||
#define SSD1305_COLORD 3
|
||||
|
||||
/* Fundamental Commands *****************************************************/
|
||||
#define SSD1305_SETCOLL 0x00 /* 0x00-0x0f: Set lower column address */
|
||||
# define SSD1305_COLL_MASK 0x0f
|
||||
#define SSD1305_SETCOLH 0x10 /* 0x10-0x1f: Set higher column address */
|
||||
# define SSD1305_COLH_MASK 0x0f
|
||||
#define SSD1305_ADDRMODE 0x20 /* 0x20: Set memory address mode */
|
||||
# define SSD1305_ADDRMODE_HOR 0x00 /* Data 1: Set horizontal address mode */
|
||||
# define SSD1305_ADDRMODE_VIRT 0x01 /* Data 1: Set virtal address mode */
|
||||
# define SSD1305_ADDRMODE_PAGE 0x02 /* Data 1: Set page address mode */
|
||||
#define SSD1305_SETCOLADDR 0x21 /* 0x21: Set column address */
|
||||
/* Data 1: Column start address: 0-131 */
|
||||
/* Data 2: Column end address: 0-131 */
|
||||
#define SSD1305_SETPAGEADDR 0x22 /* 0x22: Set page address */
|
||||
/* Data 1: Page start address: 0x00-0x7d */
|
||||
/* Data 2: Page end address: 0x00-0x7d */
|
||||
#define SSD1305_SETSTARTLINE 0x40 /* 0x40-7f: Set display start line */
|
||||
# define SSD1305_STARTLINE_MASK 0x3f
|
||||
|
||||
#define SSD1305_SETCONTRAST 0x81 /* 0x81: Set contrast control */
|
||||
/* Data 1: Set 1 of 256 contrast steps */
|
||||
#define SSD1305_SETBRIGHTNESS 0x82 /* 0x82: Set brightness */
|
||||
/* Data 1: Set 1 of 256 contrast steps */
|
||||
#define SSD1305_SETLUT 0x91 /* 0x01: Set lookup table */
|
||||
/* Data 1: Pulse width: 31-63 */
|
||||
/* Data 2: Color A: 31-63 */
|
||||
/* Data 3: Color B: 31-63 */
|
||||
/* Data 4: Color C: 31-63 */
|
||||
#define SSD1305_SETBANKCOLOR1 0x92 /* 0x92: Set bank 1-16 color */
|
||||
# define SSD1305_SETBANK1(c) (c) /* Data 1, Bits 0-1: Bank 1 color */
|
||||
# define SSD1305_SETBANK2(c) (c << 2) /* Data 1, Bits 2-3: Bank 2 color */
|
||||
# define SSD1305_SETBANK3(c) (c << 4) /* Data 1, Bits 4-5: Bank 3 color */
|
||||
# define SSD1305_SETBANK4(c) (c << 6) /* Data 1, Bits 6-7: Bank 4 color */
|
||||
# define SSD1305_SETBANK5(c) (c) /* Data 2, Bits 0-1: Bank 5 color */
|
||||
# define SSD1305_SETBANK6(c) (c << 2) /* Data 2, Bits 2-3: Bank 6 color */
|
||||
# define SSD1305_SETBANK7(c) (c << 4) /* Data 2, Bits 4-5: Bank 7 color */
|
||||
# define SSD1305_SETBANK8(c) (c << 6) /* Data 2, Bits 6-7: Bank 8 color */
|
||||
# define SSD1305_SETBANK9(c) (c) /* Data 3, Bits 0-1: Bank 9 color */
|
||||
# define SSD1305_SETBANK10(c) (c << 2) /* Data 3, Bits 2-3: Bank 10 color */
|
||||
# define SSD1305_SETBANK11(c) (c << 4) /* Data 3, Bits 4-5: Bank 11 color */
|
||||
# define SSD1305_SETBANK12(c) (c << 6) /* Data 3, Bits 6-7: Bank 12 color */
|
||||
# define SSD1305_SETBANK13(c) (c) /* Data 4, Bits 0-1: Bank 13 color */
|
||||
# define SSD1305_SETBANK14(c) (c << 2) /* Data 4, Bits 2-3: Bank 14 color */
|
||||
# define SSD1305_SETBANK15(c) (c << 4) /* Data 4, Bits 4-5: Bank 15 color */
|
||||
# define SSD1305_SETBANK16(c) (c << 6) /* Data 4, Bits 6-7: Bank 16 color */
|
||||
#define SSD1305_SETBANKCOLOR2 0x93 /* 0x93: Set bank 17-32 color */
|
||||
# define SSD1305_SETBANK17(c) (c) /* Data 1, Bits 0-1: Bank 17 color */
|
||||
# define SSD1305_SETBANK18(c) (c << 2) /* Data 1, Bits 2-3: Bank 18 color */
|
||||
# define SSD1305_SETBANK19(c) (c << 4) /* Data 1, Bits 4-5: Bank 19 color */
|
||||
# define SSD1305_SETBANK20(c) (c << 6) /* Data 1, Bits 6-7: Bank 20 color */
|
||||
# define SSD1305_SETBANK21(c) (c) /* Data 2, Bits 0-1: Bank 21 color */
|
||||
# define SSD1305_SETBANK22(c) (c << 2) /* Data 2, Bits 2-3: Bank 22 color */
|
||||
# define SSD1305_SETBANK23(c) (c << 4) /* Data 2, Bits 4-5: Bank 23 color */
|
||||
# define SSD1305_SETBANK24(c) (c << 6) /* Data 2, Bits 6-7: Bank 24 color */
|
||||
# define SSD1305_SETBANK25(c) (c) /* Data 3, Bits 0-1: Bank 25 color */
|
||||
# define SSD1305_SETBANK26(c) (c << 2) /* Data 3, Bits 2-3: Bank 26 color */
|
||||
# define SSD1305_SETBANK27(c) (c << 4) /* Data 3, Bits 4-5: Bank 27 color */
|
||||
# define SSD1305_SETBANK28(c) (c << 6) /* Data 3, Bits 6-7: Bank 28 color */
|
||||
# define SSD1305_SETBANK29(c) (c) /* Data 4, Bits 0-1: Bank 29 color */
|
||||
# define SSD1305_SETBANK30(c) (c << 2) /* Data 4, Bits 2-3: Bank 30 color */
|
||||
# define SSD1305_SETBANK31(c) (c << 4) /* Data 4, Bits 4-5: Bank 31 color */
|
||||
# define SSD1305_SETBANK32(c) (c << 6) /* Data 4, Bits 6-7: Bank 32 color */
|
||||
#define SSD1305_MAPCOL0 0xa0 /* 0xa0: Column address 0 is mapped to SEG0 */
|
||||
#define SSD1305_MAPCOL131 0xa1 /* 0xa1: Column address 131 is mapped to SEG0 */
|
||||
#define SSD1305_DISPRAM 0xa4 /* 0xa4: Resume to RAM content display */
|
||||
#define SSD1305_DISPENTIRE 0xa5 /* 0xa5: Entire display ON */
|
||||
#define SSD1305_DISPNORMAL 0xa6 /* 0xa6: Normal display */
|
||||
#define SSD1305_DISPINVERTED 0xa7 /* 0xa7: Inverse display */
|
||||
|
||||
#define SSD1305_SETMUX 0xa8 /* 0xa8: Set Multiplex Ratio*/
|
||||
/* Data 1: MUX ratio -1: 15-63 */
|
||||
#define SSD1305_DIMMODE 0xab /* 0xab: Dim mode setting */
|
||||
/* Data 1: Reserverd, must be zero */
|
||||
/* Data 2: Contrast for bank1: 0-255 */
|
||||
/* Data 3: Brightness for color bank: 0-255 */
|
||||
#define SSD1305_MSTRCONFIG 0xad /* 0xad: Master configuration */
|
||||
# define SSD1305_MSTRCONFIG_EXTVCC 0x8e /* Data 1: Select external Vcc */
|
||||
#define SSD1305_DISPONDIM 0xac /* 0xac: Display ON in dim mode */
|
||||
#define SSD1305_DISPOFF 0xae /* 0xae: Display OFF (sleep mode) */
|
||||
#define SSD1305_DISPON 0xaf /* 0xaf: Display ON in normal mode */
|
||||
#define SSD1305_SETPAGESTART 0xb0 /* 0xb0-b7: Set page start address */
|
||||
# define SSD1305_PAGESTART_MASK 0x07
|
||||
#define SSD1305_SETCOMNORMAL 0xc0 /* 0xc0: Set COM output, normal mode */
|
||||
#define SSD1305_SETCOMREMAPPED 0xc8 /* 0xc8: Set COM output, remapped mode */
|
||||
|
||||
#define SSD1305_SETOFFSET 0xd3 /* 0xd3: Set display offset */
|
||||
/* Data 1: Vertical shift by COM: 0-63 */
|
||||
#define SSD1305_SETDCLK 0xd5 /* 0xd5: Set display clock divide ratio/oscillator */
|
||||
# define SSD1305_DCLKDIV_SHIFT (0) /* Data 1, Bits 0-3: DCLK divide ratio/frequency*/
|
||||
# define SSD1305_DCLKDIV_MASK 0x0f
|
||||
# define SSD1305_DCLKFREQ_SHIFT (4) /* Data 1, Bits 4-7: DCLK divide oscillator frequency */
|
||||
# define SSD1305_DCLKFREQ_MASK 0xf0
|
||||
#define SSD1305_SETCOLORMODE 0xd8 /* 0xd: Set area color and low power display modes */
|
||||
# define SSD1305_COLORMODE_MONO 0x00 /* Data 1, Bits 4-5: 00=monochrome */
|
||||
# define SSD1305_COLORMODE_COLOR 0x30 /* Data 1, Bits 4-5: 11=area color enable */
|
||||
# define SSD1305_POWERMODE_NORMAL 0x00 /* Data 1, Bits 0,2: 00=normal power mode */
|
||||
# define SSD1305_POWERMODE_LOW 0x05 /* Data 1, Bits 0,2: 11=low power display mode */
|
||||
#define SSD1305_SETPRECHARGE 0xd9 /* 0xd9: Set pre-charge period */
|
||||
# define SSD1305_PHASE1_SHIFT (0) /* Data 1, Bits 0-3: Phase 1 period of up to 15 DCLK clocks */
|
||||
# define SSD1305_PHASE1_MASK 0x0f
|
||||
# define SSD1305_PHASE2_SHIFT (4) /* Data 1, Bits 4-7: Phase 2 period of up to 15 DCLK clocks */
|
||||
# define SSD1305_PHASE2_MASK 0xf0
|
||||
#define SSD1305_SETCOMCONFIG 0xda /* 0xda: Set COM configuration */
|
||||
# define SSD1305_COMCONFIG_SEQ 0x02 /* Data 1, Bit 4: 0=Sequential COM pin configuration */
|
||||
# define SSD1305_COMCONFIG_ALT 0x12 /* Data 1, Bit 4: 1=Alternative COM pin configuration */
|
||||
# define SSD1305_COMCONFIG_NOREMAP 0x02 /* Data 1, Bit 5: 0=Disable COM Left/Right remap */
|
||||
# define SSD1305_COMCONFIG_REMAP 0x22 /* Data 1, Bit 5: 1=Enable COM Left/Right remap */
|
||||
#define SSD1305_SETVCOMHDESEL 0xdb /* 0xdb: Set VCOMH delselect level */
|
||||
# define SSD1305_VCOMH_x4p3 0x00 /* Data 1: ~0.43 x Vcc */
|
||||
# define SSD1305_VCOMH_x7p7 0x34 /* Data 1: ~0.77 x Vcc */
|
||||
# define SSD1305_VCOMH_x8p3 0x3c /* Data 1: ~0.83 x Vcc */
|
||||
#define SSD1305_ENTER_RMWMODE 0xe0 /* 0xe0: Enter the Read Modify Write mode */
|
||||
#define SSD1305_NOP 0xe3 /* 0xe3: NOP Command for no operation */
|
||||
#define SSD1305_EXIT_RMWMODE 0xee /* 0xee: Leave the Read Modify Write mode */
|
||||
|
||||
/* Graphic Acceleration Commands ********************************************/
|
||||
|
||||
#define SSD1305_HSCROLL_RIGHT 0x26 /* 0x26: Right horizontal scroll */
|
||||
#define SSD1305_HSCROLL_LEFT 0x27 /* 0x27: Left horizontal scroll */
|
||||
/* Data 1, Bits 0-2: Column scroll offset: 0-4 */
|
||||
/* Data 2, Bits 0-2: Start page address: 0-7 */
|
||||
#define SSD1305_HSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */
|
||||
/* Data 4, Bits 0-2: End page address: 0-7 */
|
||||
|
||||
#define SSD1305_VSCROLL_RIGHT 0x29 /* 0x26: Vertical and right horizontal scroll */
|
||||
#define SSD1305_VSCROLL_LEFT 0x2a /* 0x27: Vertical and left horizontal scroll */
|
||||
/* Data 1, Bits 0-2: Column scroll offset: 0-4 */
|
||||
/* Data 2, Bits 0-2: Start page address: 0-7 */
|
||||
#define SSD1305_VSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */
|
||||
/* Data 4, Bits 0-2: End page address: 0-7 */
|
||||
/* Data 5, Bits 0-5: Vertical scrolling offset: 0-63 */
|
||||
#define SSD1305_SCROLL_STOP 0x2e /* 0x2e: Deactivate scroll */
|
||||
#define SSD1305_SCROLL_START 0x2f /* 0x2f: Activate scroll */
|
||||
#define SSD1305_VSCROLL_AREA 0xa3 /* 0xa3: Set vertical scroll area */
|
||||
/* Data 1: Number of rows in the top fixed area */
|
||||
/* Data 1: Number of rows in the scroll area */
|
||||
|
||||
/* Status register bit definitions ******************************************/
|
||||
|
||||
#define SSD1305_STATUS_DISPOFF (1 << 6) /* Bit 6: 1=Display off */
|
||||
|
||||
#endif /* __DRIVERS_LCD_SSD1305_H */
|
||||
/**************************************************************************************
|
||||
* drivers/lcd/ssd1305.h
|
||||
* Definitions for the Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED
|
||||
* Segment/Common Driver with C
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: SSD1305.pdf, "Solomon Systech SSD1305 132x64 Dot Matrix OLED/PLED
|
||||
* Segment/Common Driver with Controller," Solomon Systech Limited,
|
||||
* http://www.solomon-systech.com, May, 2008.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************************/
|
||||
|
||||
#ifndef __DRIVERS_LCD_SSD1305_H
|
||||
#define __DRIVERS_LCD_SSD1305_H
|
||||
|
||||
/**************************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************************/
|
||||
|
||||
/**************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
**************************************************************************************/
|
||||
/* General Definitions ******************************************************/
|
||||
|
||||
#define SSD1305_COLORA 0
|
||||
#define SSD1305_COLORB 1
|
||||
#define SSD1305_COLORC 2
|
||||
#define SSD1305_COLORD 3
|
||||
|
||||
/* Fundamental Commands *****************************************************/
|
||||
#define SSD1305_SETCOLL 0x00 /* 0x00-0x0f: Set lower column address */
|
||||
# define SSD1305_COLL_MASK 0x0f
|
||||
#define SSD1305_SETCOLH 0x10 /* 0x10-0x1f: Set higher column address */
|
||||
# define SSD1305_COLH_MASK 0x0f
|
||||
#define SSD1305_ADDRMODE 0x20 /* 0x20: Set memory address mode */
|
||||
# define SSD1305_ADDRMODE_HOR 0x00 /* Data 1: Set horizontal address mode */
|
||||
# define SSD1305_ADDRMODE_VIRT 0x01 /* Data 1: Set virtal address mode */
|
||||
# define SSD1305_ADDRMODE_PAGE 0x02 /* Data 1: Set page address mode */
|
||||
#define SSD1305_SETCOLADDR 0x21 /* 0x21: Set column address */
|
||||
/* Data 1: Column start address: 0-131 */
|
||||
/* Data 2: Column end address: 0-131 */
|
||||
#define SSD1305_SETPAGEADDR 0x22 /* 0x22: Set page address */
|
||||
/* Data 1: Page start address: 0x00-0x7d */
|
||||
/* Data 2: Page end address: 0x00-0x7d */
|
||||
#define SSD1305_SETSTARTLINE 0x40 /* 0x40-7f: Set display start line */
|
||||
# define SSD1305_STARTLINE_MASK 0x3f
|
||||
|
||||
#define SSD1305_SETCONTRAST 0x81 /* 0x81: Set contrast control */
|
||||
/* Data 1: Set 1 of 256 contrast steps */
|
||||
#define SSD1305_SETBRIGHTNESS 0x82 /* 0x82: Set brightness */
|
||||
/* Data 1: Set 1 of 256 contrast steps */
|
||||
#define SSD1305_SETLUT 0x91 /* 0x01: Set lookup table */
|
||||
/* Data 1: Pulse width: 31-63 */
|
||||
/* Data 2: Color A: 31-63 */
|
||||
/* Data 3: Color B: 31-63 */
|
||||
/* Data 4: Color C: 31-63 */
|
||||
#define SSD1305_SETBANKCOLOR1 0x92 /* 0x92: Set bank 1-16 color */
|
||||
# define SSD1305_SETBANK1(c) (c) /* Data 1, Bits 0-1: Bank 1 color */
|
||||
# define SSD1305_SETBANK2(c) (c << 2) /* Data 1, Bits 2-3: Bank 2 color */
|
||||
# define SSD1305_SETBANK3(c) (c << 4) /* Data 1, Bits 4-5: Bank 3 color */
|
||||
# define SSD1305_SETBANK4(c) (c << 6) /* Data 1, Bits 6-7: Bank 4 color */
|
||||
# define SSD1305_SETBANK5(c) (c) /* Data 2, Bits 0-1: Bank 5 color */
|
||||
# define SSD1305_SETBANK6(c) (c << 2) /* Data 2, Bits 2-3: Bank 6 color */
|
||||
# define SSD1305_SETBANK7(c) (c << 4) /* Data 2, Bits 4-5: Bank 7 color */
|
||||
# define SSD1305_SETBANK8(c) (c << 6) /* Data 2, Bits 6-7: Bank 8 color */
|
||||
# define SSD1305_SETBANK9(c) (c) /* Data 3, Bits 0-1: Bank 9 color */
|
||||
# define SSD1305_SETBANK10(c) (c << 2) /* Data 3, Bits 2-3: Bank 10 color */
|
||||
# define SSD1305_SETBANK11(c) (c << 4) /* Data 3, Bits 4-5: Bank 11 color */
|
||||
# define SSD1305_SETBANK12(c) (c << 6) /* Data 3, Bits 6-7: Bank 12 color */
|
||||
# define SSD1305_SETBANK13(c) (c) /* Data 4, Bits 0-1: Bank 13 color */
|
||||
# define SSD1305_SETBANK14(c) (c << 2) /* Data 4, Bits 2-3: Bank 14 color */
|
||||
# define SSD1305_SETBANK15(c) (c << 4) /* Data 4, Bits 4-5: Bank 15 color */
|
||||
# define SSD1305_SETBANK16(c) (c << 6) /* Data 4, Bits 6-7: Bank 16 color */
|
||||
#define SSD1305_SETBANKCOLOR2 0x93 /* 0x93: Set bank 17-32 color */
|
||||
# define SSD1305_SETBANK17(c) (c) /* Data 1, Bits 0-1: Bank 17 color */
|
||||
# define SSD1305_SETBANK18(c) (c << 2) /* Data 1, Bits 2-3: Bank 18 color */
|
||||
# define SSD1305_SETBANK19(c) (c << 4) /* Data 1, Bits 4-5: Bank 19 color */
|
||||
# define SSD1305_SETBANK20(c) (c << 6) /* Data 1, Bits 6-7: Bank 20 color */
|
||||
# define SSD1305_SETBANK21(c) (c) /* Data 2, Bits 0-1: Bank 21 color */
|
||||
# define SSD1305_SETBANK22(c) (c << 2) /* Data 2, Bits 2-3: Bank 22 color */
|
||||
# define SSD1305_SETBANK23(c) (c << 4) /* Data 2, Bits 4-5: Bank 23 color */
|
||||
# define SSD1305_SETBANK24(c) (c << 6) /* Data 2, Bits 6-7: Bank 24 color */
|
||||
# define SSD1305_SETBANK25(c) (c) /* Data 3, Bits 0-1: Bank 25 color */
|
||||
# define SSD1305_SETBANK26(c) (c << 2) /* Data 3, Bits 2-3: Bank 26 color */
|
||||
# define SSD1305_SETBANK27(c) (c << 4) /* Data 3, Bits 4-5: Bank 27 color */
|
||||
# define SSD1305_SETBANK28(c) (c << 6) /* Data 3, Bits 6-7: Bank 28 color */
|
||||
# define SSD1305_SETBANK29(c) (c) /* Data 4, Bits 0-1: Bank 29 color */
|
||||
# define SSD1305_SETBANK30(c) (c << 2) /* Data 4, Bits 2-3: Bank 30 color */
|
||||
# define SSD1305_SETBANK31(c) (c << 4) /* Data 4, Bits 4-5: Bank 31 color */
|
||||
# define SSD1305_SETBANK32(c) (c << 6) /* Data 4, Bits 6-7: Bank 32 color */
|
||||
#define SSD1305_MAPCOL0 0xa0 /* 0xa0: Column address 0 is mapped to SEG0 */
|
||||
#define SSD1305_MAPCOL131 0xa1 /* 0xa1: Column address 131 is mapped to SEG0 */
|
||||
#define SSD1305_DISPRAM 0xa4 /* 0xa4: Resume to RAM content display */
|
||||
#define SSD1305_DISPENTIRE 0xa5 /* 0xa5: Entire display ON */
|
||||
#define SSD1305_DISPNORMAL 0xa6 /* 0xa6: Normal display */
|
||||
#define SSD1305_DISPINVERTED 0xa7 /* 0xa7: Inverse display */
|
||||
|
||||
#define SSD1305_SETMUX 0xa8 /* 0xa8: Set Multiplex Ratio*/
|
||||
/* Data 1: MUX ratio -1: 15-63 */
|
||||
#define SSD1305_DIMMODE 0xab /* 0xab: Dim mode setting */
|
||||
/* Data 1: Reserverd, must be zero */
|
||||
/* Data 2: Contrast for bank1: 0-255 */
|
||||
/* Data 3: Brightness for color bank: 0-255 */
|
||||
#define SSD1305_MSTRCONFIG 0xad /* 0xad: Master configuration */
|
||||
# define SSD1305_MSTRCONFIG_EXTVCC 0x8e /* Data 1: Select external Vcc */
|
||||
#define SSD1305_DISPONDIM 0xac /* 0xac: Display ON in dim mode */
|
||||
#define SSD1305_DISPOFF 0xae /* 0xae: Display OFF (sleep mode) */
|
||||
#define SSD1305_DISPON 0xaf /* 0xaf: Display ON in normal mode */
|
||||
#define SSD1305_SETPAGESTART 0xb0 /* 0xb0-b7: Set page start address */
|
||||
# define SSD1305_PAGESTART_MASK 0x07
|
||||
#define SSD1305_SETCOMNORMAL 0xc0 /* 0xc0: Set COM output, normal mode */
|
||||
#define SSD1305_SETCOMREMAPPED 0xc8 /* 0xc8: Set COM output, remapped mode */
|
||||
|
||||
#define SSD1305_SETOFFSET 0xd3 /* 0xd3: Set display offset */
|
||||
/* Data 1: Vertical shift by COM: 0-63 */
|
||||
#define SSD1305_SETDCLK 0xd5 /* 0xd5: Set display clock divide ratio/oscillator */
|
||||
# define SSD1305_DCLKDIV_SHIFT (0) /* Data 1, Bits 0-3: DCLK divide ratio/frequency*/
|
||||
# define SSD1305_DCLKDIV_MASK 0x0f
|
||||
# define SSD1305_DCLKFREQ_SHIFT (4) /* Data 1, Bits 4-7: DCLK divide oscillator frequency */
|
||||
# define SSD1305_DCLKFREQ_MASK 0xf0
|
||||
#define SSD1305_SETCOLORMODE 0xd8 /* 0xd: Set area color and low power display modes */
|
||||
# define SSD1305_COLORMODE_MONO 0x00 /* Data 1, Bits 4-5: 00=monochrome */
|
||||
# define SSD1305_COLORMODE_COLOR 0x30 /* Data 1, Bits 4-5: 11=area color enable */
|
||||
# define SSD1305_POWERMODE_NORMAL 0x00 /* Data 1, Bits 0,2: 00=normal power mode */
|
||||
# define SSD1305_POWERMODE_LOW 0x05 /* Data 1, Bits 0,2: 11=low power display mode */
|
||||
#define SSD1305_SETPRECHARGE 0xd9 /* 0xd9: Set pre-charge period */
|
||||
# define SSD1305_PHASE1_SHIFT (0) /* Data 1, Bits 0-3: Phase 1 period of up to 15 DCLK clocks */
|
||||
# define SSD1305_PHASE1_MASK 0x0f
|
||||
# define SSD1305_PHASE2_SHIFT (4) /* Data 1, Bits 4-7: Phase 2 period of up to 15 DCLK clocks */
|
||||
# define SSD1305_PHASE2_MASK 0xf0
|
||||
#define SSD1305_SETCOMCONFIG 0xda /* 0xda: Set COM configuration */
|
||||
# define SSD1305_COMCONFIG_SEQ 0x02 /* Data 1, Bit 4: 0=Sequential COM pin configuration */
|
||||
# define SSD1305_COMCONFIG_ALT 0x12 /* Data 1, Bit 4: 1=Alternative COM pin configuration */
|
||||
# define SSD1305_COMCONFIG_NOREMAP 0x02 /* Data 1, Bit 5: 0=Disable COM Left/Right remap */
|
||||
# define SSD1305_COMCONFIG_REMAP 0x22 /* Data 1, Bit 5: 1=Enable COM Left/Right remap */
|
||||
#define SSD1305_SETVCOMHDESEL 0xdb /* 0xdb: Set VCOMH delselect level */
|
||||
# define SSD1305_VCOMH_x4p3 0x00 /* Data 1: ~0.43 x Vcc */
|
||||
# define SSD1305_VCOMH_x7p7 0x34 /* Data 1: ~0.77 x Vcc */
|
||||
# define SSD1305_VCOMH_x8p3 0x3c /* Data 1: ~0.83 x Vcc */
|
||||
#define SSD1305_ENTER_RMWMODE 0xe0 /* 0xe0: Enter the Read Modify Write mode */
|
||||
#define SSD1305_NOP 0xe3 /* 0xe3: NOP Command for no operation */
|
||||
#define SSD1305_EXIT_RMWMODE 0xee /* 0xee: Leave the Read Modify Write mode */
|
||||
|
||||
/* Graphic Acceleration Commands ********************************************/
|
||||
|
||||
#define SSD1305_HSCROLL_RIGHT 0x26 /* 0x26: Right horizontal scroll */
|
||||
#define SSD1305_HSCROLL_LEFT 0x27 /* 0x27: Left horizontal scroll */
|
||||
/* Data 1, Bits 0-2: Column scroll offset: 0-4 */
|
||||
/* Data 2, Bits 0-2: Start page address: 0-7 */
|
||||
#define SSD1305_HSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */
|
||||
#define SSD1305_HSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */
|
||||
/* Data 4, Bits 0-2: End page address: 0-7 */
|
||||
|
||||
#define SSD1305_VSCROLL_RIGHT 0x29 /* 0x26: Vertical and right horizontal scroll */
|
||||
#define SSD1305_VSCROLL_LEFT 0x2a /* 0x27: Vertical and left horizontal scroll */
|
||||
/* Data 1, Bits 0-2: Column scroll offset: 0-4 */
|
||||
/* Data 2, Bits 0-2: Start page address: 0-7 */
|
||||
#define SSD1305_VSCROLL_FRAMES6 0x00 /* Data 3, Bits 0-2: Timer interval, 000=6 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES32 0x01 /* Data 3, Bits 0-2: Timer interval, 001=32 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES64 0x02 /* Data 3, Bits 0-2: Timer interval, 010=64 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES128 0x03 /* Data 3, Bits 0-2: Timer interval, 011=128 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES3 0x04 /* Data 3, Bits 0-2: Timer interval, 100=3 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES4 0x05 /* Data 3, Bits 0-2: Timer interval, 101=4 frames */
|
||||
#define SSD1305_VSCROLL_FRAMES2 0x06 /* Data 3, Bits 0-2: Timer interval, 110=2 frames */
|
||||
/* Data 4, Bits 0-2: End page address: 0-7 */
|
||||
/* Data 5, Bits 0-5: Vertical scrolling offset: 0-63 */
|
||||
#define SSD1305_SCROLL_STOP 0x2e /* 0x2e: Deactivate scroll */
|
||||
#define SSD1305_SCROLL_START 0x2f /* 0x2f: Activate scroll */
|
||||
#define SSD1305_VSCROLL_AREA 0xa3 /* 0xa3: Set vertical scroll area */
|
||||
/* Data 1: Number of rows in the top fixed area */
|
||||
/* Data 1: Number of rows in the scroll area */
|
||||
|
||||
/* Status register bit definitions ******************************************/
|
||||
|
||||
#define SSD1305_STATUS_DISPOFF (1 << 6) /* Bit 6: 1=Display off */
|
||||
|
||||
#endif /* __DRIVERS_LCD_SSD1305_H */
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
* controller.
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Reference: "Product Specification, OEL Display Module, UG-9664HSWAG01", Univision
|
||||
* Technology Inc., SAS1-6020-B, January 3, 2008.
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
# drivers/mmcsd/Make.defs
|
||||
#
|
||||
# Copyright (C) 2008, 2011 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/mmcsd/mmcsd_csd.h
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/mmcsd/mmcsd_debug.c
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/mmcsd/mmcsd_internal.h
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
+339
-339
File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,7 @@
|
||||
* drivers/mmcsd/mmcsd_spi.h
|
||||
*
|
||||
* Copyright (C) 2008-2009 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* Driver for SPI-based AT45DB161D (16Mbit)
|
||||
*
|
||||
* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/mtd/flash_eraseall.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
+1
-1
@@ -2,7 +2,7 @@
|
||||
* drivers/mtd/ftl.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/mtd/skeleton.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/net/cs89x0.c
|
||||
*
|
||||
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
+326
-326
File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,7 @@
|
||||
* drivers/net/dm9x.c
|
||||
*
|
||||
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References: Davicom data sheets (DM9000-DS-F03-041906.pdf,
|
||||
* DM9010-DS-F01-103006.pdf) and looking at lots of other DM90x0
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/net/enc28j60.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* References:
|
||||
* - ENC28J60 Data Sheet, Stand-Alone Ethernet Controller with SPI Interface,
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/power/pm_activity.c
|
||||
*
|
||||
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
# drivers/sensors/Make.defs
|
||||
#
|
||||
# Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -3,7 +3,7 @@
|
||||
* Character driver for the STMicro LM-75 Temperature Sensor
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
# drivers/serial/Make.defs
|
||||
#
|
||||
# Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
# drivers/usbhost/Make.defs
|
||||
#
|
||||
# Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/usbhost/usbhost_findclass.c
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/usbhost/usbhost_hidkbd.c
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/usbhost/usbhost_registerclass.c
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/usbhost/usbhost_registry.c
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
* drivers/usbhost/usbdev_registry.h
|
||||
*
|
||||
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
# drivers/wireless/Make.defs
|
||||
#
|
||||
# Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
|
||||
Reference in New Issue
Block a user