diff --git a/arch/Kconfig b/arch/Kconfig index d06a58feafa..92a7d2980f6 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -58,6 +58,7 @@ config ARCH_RENESAS config ARCH_RISCV bool "RISC-V" select ARCH_HAVE_INTERRUPTSTACK + select ARCH_HAVE_STACKCHECK select ARCH_HAVE_CUSTOMOPT select ARCH_HAVE_STDARG_H ---help--- diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index 1c37df1b356..80753f11cb1 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -10,6 +10,12 @@ choice prompt "RISC-V chip selection" default ARCH_CHIP_NR5 +config ARCH_CHIP_FE310 + bool "SiFive FE310" + select ARCH_RV32IM + ---help--- + SiFive FE310 processor (E31 RISC-V Core with MAC extensions). + config ARCH_CHIP_NR5 bool "NEXT NanoRisc5" select ARCH_RV32IM @@ -39,6 +45,7 @@ config ARCH_FAMILY config ARCH_CHIP string + default "fe310" if ARCH_CHIP_FE310 default "nr5m100" if ARCH_CHIP_NR5 default "gap8" if ARCH_CHIP_GAP8 @@ -55,6 +62,9 @@ config NR5_MPU if ARCH_RV32IM source arch/risc-v/src/rv32im/Kconfig endif +if ARCH_CHIP_FE310 +source arch/risc-v/src/fe310/Kconfig +endif if ARCH_CHIP_NR5 source arch/risc-v/src/nr5m100/Kconfig endif diff --git a/arch/risc-v/include/.gitignore b/arch/risc-v/include/.gitignore new file mode 100644 index 00000000000..e6460c4a678 --- /dev/null +++ b/arch/risc-v/include/.gitignore @@ -0,0 +1,3 @@ +/board +/chip + diff --git a/arch/risc-v/include/fe310/chip.h b/arch/risc-v/include/fe310/chip.h new file mode 100644 index 00000000000..f8f30100e7a --- /dev/null +++ b/arch/risc-v/include/fe310/chip.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/risc-v/include/fe310/chip.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_FE310_CHIP_H +#define __ARCH_RISCV_INCLUDE_FE310_CHIP_H + +#endif /* __ARCH_RISCV_INCLUDE_FE310_CHIP_H */ diff --git a/arch/risc-v/include/fe310/irq.h b/arch/risc-v/include/fe310/irq.h new file mode 100644 index 00000000000..948e464a55d --- /dev/null +++ b/arch/risc-v/include/fe310/irq.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/risc-v/include/fe310/irq.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_FE310_IRQ_H +#define __ARCH_RISCV_INCLUDE_FE310_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Machine Interrupt Enable bit in mstatus register */ + +#define MSTATUS_MIE (0x1 << 3) + +/* Map RISC-V exception code to NuttX IRQ */ + +/* IRQ 0-15 : (exception:interrupt=0) */ + +#define FE310_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */ +#define FE310_IRQ_IAFAULT (1) /* Instruction Address Fault */ +#define FE310_IRQ_IINSTRUCTION (2) /* Illegal Instruction */ +#define FE310_IRQ_BPOINT (3) /* Break Point */ +#define FE310_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */ +#define FE310_IRQ_LAFAULT (5) /* Load Access Fault */ +#define FE310_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */ +#define FE310_IRQ_SAFAULT (7) /* Store/AMO Access Fault */ +#define FE310_IRQ_ECALLU (8) /* Environment Call from U-mode */ + /* 9-10: Reserved */ + +#define FE310_IRQ_ECALLM (11) /* Environment Call from M-mode */ + /* 12-15: Reserved */ + +/* IRQ 16- : (async event:interrupt=1) */ + +#define FE310_IRQ_ASYNC (16) +#define FE310_IRQ_MSOFT (FE310_IRQ_ASYNC + 3) /* Machine Software Int */ +#define FE310_IRQ_MTIMER (FE310_IRQ_ASYNC + 7) /* Machine Timer Int */ +#define FE310_IRQ_MEXT (FE310_IRQ_ASYNC + 11) /* Machine External Int */ + +/* Machine Grobal External Interrupt */ + +#define FE310_IRQ_UART0 (FE310_IRQ_MEXT + 3) +#define FE310_IRQ_UART1 (FE310_IRQ_MEXT + 4) + +/* Total number of IRQs */ + +#define NR_IRQS (FE310_IRQ_UART1 + 1) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +EXTERN irqstate_t up_irq_save(void); +EXTERN void up_irq_restore(irqstate_t); +EXTERN irqstate_t up_irq_enable(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_INCLUDE_FE310_IRQ_H */ + diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h index d8d23901385..338b9a1da51 100644 --- a/arch/risc-v/include/irq.h +++ b/arch/risc-v/include/irq.h @@ -67,12 +67,4 @@ typedef uint32_t irqstate_t; * Public Variables ****************************************************************************/ -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -irqstate_t irqsave(void); - -void irqrestore(irqstate_t); - #endif /* __ARCH_RISCV_INCLUDE_IRQ_H */ diff --git a/arch/risc-v/src/.gitignore b/arch/risc-v/src/.gitignore new file mode 100644 index 00000000000..dfdfc935431 --- /dev/null +++ b/arch/risc-v/src/.gitignore @@ -0,0 +1,5 @@ +/.depend +/Make.dep +/locked.r +/board +/chip diff --git a/arch/risc-v/src/Makefile b/arch/risc-v/src/Makefile index 5d05cb47a21..e69ec4599fa 100644 --- a/arch/risc-v/src/Makefile +++ b/arch/risc-v/src/Makefile @@ -229,4 +229,4 @@ info: @echo $(ASRCS) @echo $(CONFIG_ARCH_CHIP) -#-include Make.dep +-include Make.dep diff --git a/arch/risc-v/src/common/up_arch.h b/arch/risc-v/src/common/up_arch.h index fc602193450..ee7ed9c0cab 100644 --- a/arch/risc-v/src/common/up_arch.h +++ b/arch/risc-v/src/common/up_arch.h @@ -66,5 +66,23 @@ * Public Function Prototypes ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Atomic modification of registers */ + +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + #endif /* __ASSEMBLY__ */ #endif /* ___ARCH_ARM_SRC_COMMON_UP_ARCH_H */ diff --git a/arch/risc-v/src/common/up_checkstack.c b/arch/risc-v/src/common/up_checkstack.c new file mode 100644 index 00000000000..9ea5ea1c7a2 --- /dev/null +++ b/arch/risc-v/src/common/up_checkstack.c @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_checkstack.c + * + * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" + +#ifdef CONFIG_STACK_COLORATION + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static size_t do_stackcheck(uintptr_t alloc, size_t size, bool int_stack); + +/**************************************************************************** + * Name: do_stackcheck + * + * Description: + * Determine (approximately) how much stack has been used be searching the + * stack memory for a high water mark. That is, the deepest level of the + * stack that clobbered some recognizable marker in the stack memory. + * + * Input Parameters: + * alloc - Allocation base address of the stack + * size - The size of the stack in bytes + * + * Returned Value: + * The estimated amount of stack space used. + * + ****************************************************************************/ + +static size_t do_stackcheck(uintptr_t alloc, size_t size, bool int_stack) +{ + FAR uintptr_t start; + FAR uintptr_t end; + FAR uint32_t *ptr; + size_t mark; + + if (size == 0) + { + return 0; + } + + /* Get aligned addresses of the top and bottom of the stack */ + +#ifdef CONFIG_TLS + if (!int_stack) + { + /* Skip over the TLS data structure at the bottom of the stack */ + + DEBUGASSERT((alloc & TLS_STACK_MASK) == 0); + start = alloc + sizeof(struct tls_info_s); + } + else + { + start = alloc & ~3; + } +#else + UNUSED(int_stack); + start = alloc & ~3; +#endif + end = (alloc + size + 3) & ~3; + + /* Get the adjusted size based on the top and bottom of the stack */ + + size = end - start; + + /* The ARM uses a push-down stack: the stack grows toward lower addresses + * in memory. We need to start at the lowest address in the stack memory + * allocation and search to higher addresses. The first word we encounter + * that does not have the magic value is the high water mark. + */ + + for (ptr = (FAR uint32_t *)start, mark = (size >> 2); + *ptr == STACK_COLOR && mark > 0; + ptr++, mark--); + + /* If the stack is completely used, then this might mean that the stack + * overflowed from above (meaning that the stack is too small), or may + * have been overwritten from below meaning that some other stack or data + * structure overflowed. + * + * If you see returned values saying that the entire stack is being used + * then enable the following logic to see it there are unused areas in the + * middle of the stack. + */ + +#if 0 + if (mark + 16 > nwords) + { + int i; + int j; + + ptr = (FAR uint32_t *)start; + for (i = 0; i < size; i += 4*64) + { + for (j = 0; j < 64; j++) + { + int ch; + if (*ptr++ == STACK_COLOR) + { + ch = '.'; + } + else + { + ch = 'X'; + } + + up_putc(ch); + } + + up_putc('\n'); + } + } +#endif + + /* Return our guess about how much stack space was used */ + + return mark << 2; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_check_stack and friends + * + * Description: + * Determine (approximately) how much stack has been used be searching the + * stack memory for a high water mark. That is, the deepest level of the + * stack that clobbered some recognizable marker in the stack memory. + * + * Input Parameters: + * None + * + * Returned Value: + * The estimated amount of stack space used. + * + ****************************************************************************/ + +size_t up_check_tcbstack(FAR struct tcb_s *tcb) +{ + return do_stackcheck((uintptr_t)tcb->stack_alloc_ptr, tcb->adj_stack_size, + false); +} + +ssize_t up_check_tcbstack_remain(FAR struct tcb_s *tcb) +{ + return (ssize_t)tcb->adj_stack_size - (ssize_t)up_check_tcbstack(tcb); +} + +size_t up_check_stack(void) +{ + return up_check_tcbstack(this_task()); +} + +ssize_t up_check_stack_remain(void) +{ + return up_check_tcbstack_remain(this_task()); +} + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +size_t up_check_intstack(void) +{ + return do_stackcheck((uintptr_t)&g_intstackalloc, + (CONFIG_ARCH_INTERRUPTSTACK & ~3), + true); +} + +size_t up_check_intstack_remain(void) +{ + return (CONFIG_ARCH_INTERRUPTSTACK & ~3) - up_check_intstack(); +} +#endif + +#endif /* CONFIG_STACK_COLORATION */ diff --git a/arch/risc-v/src/common/up_createstack.c b/arch/risc-v/src/common/up_createstack.c index 1861707685a..971a69f3997 100644 --- a/arch/risc-v/src/common/up_createstack.c +++ b/arch/risc-v/src/common/up_createstack.c @@ -175,15 +175,6 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) size_t top_of_stack; size_t size_of_stack; - /* Yes.. If stack debug is enabled, then fill the stack with a - * recognizable value that we can use later to test for high - * water marks. - */ - -#ifdef CONFIG_STACK_COLORATION - memset(tcb->stack_alloc_ptr, 0xaa, stack_size); -#endif - /* MIPS uses a push-down stack: the stack grows toward lower * addresses in memory. The stack pointer register points to the * lowest, valid working address (the "top" of the stack). Items on @@ -206,9 +197,44 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype) tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack; tcb->adj_stack_size = size_of_stack; + /* Yes.. If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + +#ifdef CONFIG_STACK_COLORATION + up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size); +#endif + board_autoled_on(LED_STACKCREATED); return OK; } return ERROR; } + +/**************************************************************************** + * Name: up_stack_color + * + * Description: + * Write a well know value into the stack + * + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +void up_stack_color(FAR void *stackbase, size_t nbytes) +{ + /* Take extra care that we do not write outsize the stack boundaries */ + + uint32_t *stkptr = (uint32_t *)(((uintptr_t)stackbase + 3) & ~3); + uintptr_t stkend = (((uintptr_t)stackbase + nbytes) & ~3); + size_t nwords = (stkend - (uintptr_t)stackbase) >> 2; + + /* Set the entire stack to the coloration value */ + + while (nwords-- > 0) + { + *stkptr++ = STACK_COLOR; + } +} +#endif diff --git a/arch/risc-v/src/common/up_internal.h b/arch/risc-v/src/common/up_internal.h index e7eba8a93d5..004bd9fe6ae 100644 --- a/arch/risc-v/src/common/up_internal.h +++ b/arch/risc-v/src/common/up_internal.h @@ -116,6 +116,33 @@ extern "C" EXTERN volatile uint32_t *g_current_regs; EXTERN uint32_t g_idle_topstack; +/* Address of the saved user stack pointer */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +EXTERN uint32_t g_intstackalloc; /* Allocated stack base */ +EXTERN uint32_t g_intstackbase; /* Initial top of interrupt stack */ +#endif + +/* These 'addresses' of these values are setup by the linker script. They are + * not actual uint32_t storage locations! They are only used meaningfully in the + * following way: + * + * - The linker script defines, for example, the symbol_sdata. + * - The declareion extern uint32_t _sdata; makes C happy. C will believe + * that the value _sdata is the address of a uint32_t variable _data (it is + * not!). + * - We can recoved the linker value then by simply taking the address of + * of _data. like: uint32_t *pdata = &_sdata; + */ + +EXTERN uint32_t _stext; /* Start of .text */ +EXTERN uint32_t _etext; /* End_1 of .text + .rodata */ +EXTERN const uint32_t _eronly; /* End+1 of read only section (.text + .rodata) */ +EXTERN uint32_t _sdata; /* Start of .data */ +EXTERN uint32_t _edata; /* End+1 of .data */ +EXTERN uint32_t _sbss; /* Start of .bss */ +EXTERN uint32_t _ebss; /* End+1 of .bss */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -129,13 +156,12 @@ void up_boot(void); /* Memory allocation ********************************************************/ void up_addregion(void); -void up_allocat_eheap(FAR void **heap_start, size_t *heap_size); +void up_allocate_heap(FAR void **heap_start, size_t *heap_size); /* IRQ initialization *******************************************************/ void up_irqinitialize(void); void up_copystate(uint32_t *dest, uint32_t *src); -void up_dumpstate(void); void up_sigdeliver(void); int up_swint(int irq, FAR void *context, FAR void *arg); uint32_t up_get_newintctx(void); @@ -146,17 +172,38 @@ void riscv_timer_initialize(void); /* Low level serial output **************************************************/ -void up_serialinit(void); void up_lowputc(char ch); void up_puts(const char *str); void up_lowputs(const char *str); +#ifdef USE_SERIALDRIVER +void up_serialinit(void); +#else +# define up_serialinit() +#endif + +#ifdef USE_EARLYSERIALINIT +void up_earlyserialinit(void); +#else +# define up_earlyserialinit() +#endif + +#ifdef CONFIG_RPMSG_UART void rpmsg_serialinit(void); +#else +# define rpmsg_serialinit() +#endif /* The OS start routine **************************************************/ void nx_start(void); +/* Debug ********************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +void up_stack_color(FAR void *stackbase, size_t nbytes); +#endif + #undef EXTERN #ifdef __cplusplus } diff --git a/arch/risc-v/src/common/up_modifyreg32.c b/arch/risc-v/src/common/up_modifyreg32.c new file mode 100644 index 00000000000..6746e43507a --- /dev/null +++ b/arch/risc-v/src/common/up_modifyreg32.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_modifyreg32.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg32 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) +{ + irqstate_t flags; + uint32_t regval; + + flags = spin_lock_irqsave(); + regval = getreg32(addr); + regval &= ~clearbits; + regval |= setbits; + putreg32(regval, addr); + spin_unlock_irqrestore(flags); +} diff --git a/arch/risc-v/src/common/up_puts.c b/arch/risc-v/src/common/up_puts.c new file mode 100644 index 00000000000..9300c12210b --- /dev/null +++ b/arch/risc-v/src/common/up_puts.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/risc-v/src/common/up_puts.c + * + * Copyright (C) 2008-2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_puts + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void up_puts(const char *str) +{ + while (*str) + { + up_putc(*str++); + } +} + diff --git a/arch/risc-v/src/fe310/Kconfig b/arch/risc-v/src/fe310/Kconfig new file mode 100644 index 00000000000..3ccf9bf9df4 --- /dev/null +++ b/arch/risc-v/src/fe310/Kconfig @@ -0,0 +1,62 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "FE310 Configuration Options" + +choice + prompt "FE310 Chip Selection" + default ARCH_CHIP_FE310_G002 + depends on ARCH_CHIP_FE310 + +config ARCH_CHIP_FE310_G002 + bool "FE310_G002" + select FE310_HAVE_UART0 + select FE310_HAVE_GPIO + ---help--- + FE310, RV32IMAC 32Mbit SPI-Flash, 16KB SRAM + +endchoice + +config FE310_G002 + bool + default y + select FE310_HAVE_UART0 + +menu "FE310 Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for the +# selection MCU + +config FE310_HAVE_UART0 + bool + default y + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +# These are the peripheral selections proper + +config FE310_UART0 + bool "UART0" + default y + select ARCH_HAVE_UART0 + select ARCH_HAVE_SERIAL_TERMIOS + select FE310_UART + +endmenu + +config FE310_UART_RX_BUF_SIZE + int "UART RX Bufer size" + default 64 + depends on FE310_UART + ---help--- + Size of RX buffers for FE310 UARTs + +config FE310_UART_TX_BUF_SIZE + int "UART TX Bufer size" + default 64 + depends on FE310_UART + ---help--- + Size of TX buffers for FE310 UARTs + diff --git a/arch/risc-v/src/fe310/Make.defs b/arch/risc-v/src/fe310/Make.defs new file mode 100644 index 00000000000..6b198431532 --- /dev/null +++ b/arch/risc-v/src/fe310/Make.defs @@ -0,0 +1,62 @@ +############################################################################ +# arch/risc-v/src/fe310/Make.defs +# +# Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. +# Author: Masayuki Ishikawa +# +# # Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 +HEAD_ASRC = fe310_vectors.S + +# Specify our general Assembly files +CHIP_ASRCS = fe310_head.S up_syscall.S + +# Specify C code within the common directory to be included +CMN_CSRCS += up_initialize.c up_swint.c +CMN_CSRCS += up_allocateheap.c up_createstack.c up_dumpstate.c up_exit.c +CMN_CSRCS += up_assert.c up_blocktask.c up_copystate.c up_initialstate.c +CMN_CSRCS += up_interruptcontext.c up_modifyreg32.c up_puts.c +CMN_CSRCS += up_releasepending.c up_reprioritizertr.c +CMN_CSRCS += up_releasestack.c up_stackframe.c up_schedulesigaction.c +CMN_CSRCS += up_sigdeliver.c up_unblocktask.c up_usestack.c + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +ifeq ($(CONFIG_ARCH_HAVE_VFORK),y) +CMN_CSRCS += up_vfork.c +endif + +# Specify our C code within this directory to be included +CHIP_CSRCS = fe310_allocateheap.c fe310_idle.c +CHIP_CSRCS += fe310_irq.c fe310_irq_dispatch.c +CHIP_CSRCS += fe310_lowputc.c fe310_serial.c +CHIP_CSRCS += fe310_start.c fe310_timerisr.c + diff --git a/arch/risc-v/src/fe310/chip.h b/arch/risc-v/src/fe310/chip.h new file mode 100644 index 00000000000..3a4733397d7 --- /dev/null +++ b/arch/risc-v/src/fe310/chip.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/chip.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_FE310_CHIP_H +#define __ARCH_RISCV_SRC_FE310_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "fe310_memorymap.h" + +#endif /* __ARCH_RISCV_SRC_FE310_CHIP_H */ + diff --git a/arch/risc-v/src/fe310/fe310.h b/arch/risc-v/src/fe310/fe310.h new file mode 100644 index 00000000000..cfe707fccde --- /dev/null +++ b/arch/risc-v/src/fe310/fe310.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_FE310_FE310_H +#define __ARCH_RISCV_SRC_FE310_FE310_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include "up_internal.h" +#include "chip.h" +#include "fe310_lowputc.h" + +#endif /* __ARCH_RISCV_SRC_FE310_FE310_H */ + diff --git a/arch/risc-v/src/fe310/fe310_allocateheap.c b/arch/risc-v/src/fe310/fe310_allocateheap.c new file mode 100644 index 00000000000..922e6e36623 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_allocateheap.c @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_allocateheap.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "fe310.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_addregion + ****************************************************************************/ + +void up_addregion(void) +{ +} + diff --git a/arch/risc-v/src/fe310/fe310_config.h b/arch/risc-v/src/fe310/fe310_config.h new file mode 100644 index 00000000000..08e960c7798 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_config.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_config.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_FE310_FE310_CONFIG_H +#define __ARCH_RISCV_SRC_FE310_FE310_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_FE310_UART0) || defined(CONFIG_FE310_UART1) +# define HAVE_UART_DEVICE 1 +#endif + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_FE310_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_FE310_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +#endif /* __ARCH_RISCV_SRC_FE310_FE310_CONFIG_H */ diff --git a/arch/risc-v/src/fe310/fe310_head.S b/arch/risc-v/src/fe310/fe310_head.S new file mode 100644 index 00000000000..ed997bc5cc4 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_head.S @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_head.S + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .global exception_common + + /* Imported symbols */ + + .extern __trap_vec + + .section .text + .global __start + +__start: + + /* Set stack pointer to the idle thread stack */ + + lui sp, %hi(FE310_IDLESTACK_TOP) + addi sp, sp, %lo(FE310_IDLESTACK_TOP) + + /* Initialize the Machine Trap Vector */ + + lui t0, %hi(__trap_vec) + addi t0, t0, %lo(__trap_vec) + csrw mtvec, t0 + + /* Jump to __fe310_start */ + + jal x1, __fe310_start + + /* We shouldn't return from __fe310_start */ + + .global _init + .global _fini + +_init: +_fini: + + /* These don't have to do anything since we use init_array/fini_array. */ + + ret + +/**************************************************************************** + * Name: exception_common + ****************************************************************************/ + +exception_common: + + addi sp, sp, -XCPTCONTEXT_SIZE + + sw x1, 1*4(sp) /* ra */ + sw x3, 3*4(sp) /* gp */ + sw x4, 4*4(sp) /* tp */ + sw x5, 5*4(sp) /* t0 */ + sw x6, 6*4(sp) /* t1 */ + sw x7, 7*4(sp) /* t2 */ + sw x8, 8*4(sp) /* s0 */ + sw x9, 9*4(sp) /* s1 */ + sw x10, 10*4(sp) /* a0 */ + sw x11, 11*4(sp) /* a1 */ + sw x12, 12*4(sp) /* a2 */ + sw x13, 13*4(sp) /* a3 */ + sw x14, 14*4(sp) /* a4 */ + sw x15, 15*4(sp) /* a5 */ + sw x16, 16*4(sp) /* a6 */ + sw x17, 17*4(sp) /* a7 */ + sw x18, 18*4(sp) /* s2 */ + sw x19, 19*4(sp) /* s3 */ + sw x20, 20*4(sp) /* s4 */ + sw x21, 21*4(sp) /* s5 */ + sw x22, 22*4(sp) /* s6 */ + sw x23, 23*4(sp) /* s7 */ + sw x24, 24*4(sp) /* s8 */ + sw x25, 25*4(sp) /* s9 */ + sw x26, 26*4(sp) /* s10 */ + sw x27, 27*4(sp) /* s11 */ + sw x28, 28*4(sp) /* t3 */ + sw x29, 29*4(sp) /* t4 */ + sw x30, 30*4(sp) /* t5 */ + sw x31, 31*4(sp) /* t6 */ + + csrr s0, mstatus + sw s0, 32*4(sp) /* mstatus */ + + addi s0, sp, XCPTCONTEXT_SIZE + sw s0, 2*4(sp) /* original SP */ + + /* Setup arg0(exeption cause), arg1(context) */ + + csrr a0, mcause /* exception cause */ + csrr s0, mepc + sw s0, 0(sp) /* exception PC */ + + mv a1, sp /* context = sp */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + /* Switch to interrupt stack */ + + lui sp, %hi(g_intstackbase) + addi sp, sp, %lo(g_intstackbase) +#endif + + /* Call interrupt handler in C */ + + jal x1, fe310_dispatch_irq + + /* If context switch is needed, return a new sp */ + + mv sp, a0 + lw s0, 0(sp) /* restore mepc */ + csrw mepc, s0 + + lw s0, 32*4(sp) /* restore mstatus */ + csrw mstatus, s0 + + lw x3, 3*4(sp) /* gp */ + lw x4, 4*4(sp) /* tp */ + lw x5, 5*4(sp) /* t0 */ + lw x6, 6*4(sp) /* t1 */ + lw x7, 7*4(sp) /* t2 */ + lw x8, 8*4(sp) /* s0 */ + lw x9, 9*4(sp) /* s1 */ + lw x10, 10*4(sp) /* a0 */ + lw x11, 11*4(sp) /* a1 */ + lw x12, 12*4(sp) /* a2 */ + lw x13, 13*4(sp) /* a3 */ + lw x14, 14*4(sp) /* a4 */ + lw x15, 15*4(sp) /* a5 */ + lw x16, 16*4(sp) /* a6 */ + lw x17, 17*4(sp) /* a7 */ + lw x18, 18*4(sp) /* s2 */ + lw x19, 19*4(sp) /* s3 */ + lw x20, 20*4(sp) /* s4 */ + lw x21, 21*4(sp) /* s5 */ + lw x22, 22*4(sp) /* s6 */ + lw x23, 23*4(sp) /* s7 */ + lw x24, 24*4(sp) /* s8 */ + lw x25, 25*4(sp) /* s9 */ + lw x26, 26*4(sp) /* s10 */ + lw x27, 27*4(sp) /* s11 */ + lw x28, 28*4(sp) /* t3 */ + lw x29, 29*4(sp) /* t4 */ + lw x30, 30*4(sp) /* t5 */ + lw x31, 31*4(sp) /* t6 */ + + lw x1, 1*4(sp) /* ra */ + + lw sp, 2*4(sp) /* restore original sp */ + + /* Return from Machine Interrupt */ + + mret + +/************************************************************************************ + * Name: g_intstackalloc and g_intstackbase + ************************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + .bss + .align 4 + .global g_intstackalloc + .global g_intstackbase + .type g_intstackalloc, object + .type g_intstackbase, object +g_intstackalloc: + .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3)) +g_intstackbase: + .skip 4 + .size g_intstackbase, 4 + .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3) +#endif diff --git a/arch/risc-v/src/fe310/fe310_idle.c b/arch/risc-v/src/fe310/fe310_idle.c new file mode 100644 index 00000000000..9d4b9e50e87 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_idle.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_idle.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Based on arch/risc-v/src/common/up_idle.c + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + asm("WFI"); + +#endif +} diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c new file mode 100644 index 00000000000..030351d14ad --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_irq.c @@ -0,0 +1,252 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_irq.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "fe310.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *g_current_regs; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable Machine interrupts */ + + (void)up_irq_save(); + + /* Colorize the interrupt stack for debug purposes */ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size), + intstack_size); +#endif + + /* Set priority for all global interrupts to 1 (lowest) */ + + int id; + + for (id = 1; id <= 52; id++) + { + putreg32(1, FE310_PLIC_PRIORITY + 4 * id); + } + + /* Set irq threshold to 0 (permits all global interrupts) */ + + putreg32(0, FE310_PLIC_THRESHOLD); + + /* currents_regs is non-NULL only while processing an interrupt */ + + g_current_regs = NULL; + + /* Attach the ecall interrupt handler */ + + irq_attach(FE310_IRQ_ECALLM, up_swint, NULL); + up_enable_irq(FE310_IRQ_ECALLM); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + (void)up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + int extirq; + + if (irq > FE310_IRQ_MEXT) + { + extirq = irq - FE310_IRQ_MEXT; + ASSERT(31 >= extirq); /* TODO */ + + /* Clear enable bit for the irq */ + + modifyreg32(FE310_PLIC_ENABLE1, 1 << extirq, 0); + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + int extirq; + + if (irq > FE310_IRQ_MEXT) + { + extirq = irq - FE310_IRQ_MEXT; + ASSERT(31 >= extirq); /* TODO */ + + /* Set enable bit for the irq */ + + modifyreg32(FE310_PLIC_ENABLE1, 0, 1 << extirq); + } +} + +/**************************************************************************** + * Name: up_get_newintctx + * + * Description: + * Return a value for EPIC. But FE310 doesn't use EPIC for event control. + * + ****************************************************************************/ + +uint32_t up_get_newintctx(void) +{ + return 0; +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_irq_save + * + * Description: + * Return the current interrupt state and disable interrupts + * + ****************************************************************************/ + +irqstate_t up_irq_save(void) +{ + uint32_t oldstat; + uint32_t newstat; + + /* Clear machine interrupt enable bit */ + + asm volatile ("csrr %0, mstatus": "=r" (oldstat)); + newstat = oldstat & ~MSTATUS_MIE; + asm volatile("csrw mstatus, %0" : /* no output */ : "r" (newstat)); + + return oldstat; +} + +/**************************************************************************** + * Name: up_irq_restore + * + * Description: + * Restore previous IRQ mask state + * + ****************************************************************************/ + +void up_irq_restore(irqstate_t flags) +{ + /* Machine mode - mstatus */ + + asm volatile("csrw mstatus, %0" : /* no output */ : "r" (flags)); +} + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + +irqstate_t up_irq_enable(void) +{ + uint32_t oldstat; + uint32_t newstat; + uint32_t mie; + +#if 1 + /* Enable MEIE (machine external interrupt enable) + * and MTIE (machine timer interrupt enable) + */ + + /* TODO: should move to up_enable_irq() */ + + mie = 0x1 << 11 | 0x1 << 7; + asm volatile("csrw mie, %0" : /* no output */ : "r" (mie)); +#endif + + /* Set machine interrupt enable (MIE) in mstatus */ + + asm volatile ("csrr %0, mstatus": "=r" (oldstat)); + newstat = oldstat | MSTATUS_MIE; + asm volatile("csrw mstatus, %0" : /* no output */ : "r" (newstat)); + + return oldstat; +} diff --git a/arch/risc-v/src/fe310/fe310_irq_dispatch.c b/arch/risc-v/src/fe310/fe310_irq_dispatch.c new file mode 100644 index 00000000000..3c98054eb85 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_irq_dispatch.c @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_irq_dispatch.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "group/group.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t * g_current_regs; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * fe310_dispatch_irq + ****************************************************************************/ + +void *fe310_dispatch_irq(uint32_t vector, uint32_t *regs) +{ + uint32_t irq = (vector >> 27) | (vector & 0xf); + uint32_t *mepc = regs; + + if (FE310_IRQ_MEXT == irq) + { + /* Read & write FE310_PLIC_CLAIM to clear pending */ + + uint32_t val = getreg32(FE310_PLIC_CLAIM); + putreg32(val, FE310_PLIC_CLAIM); + + irq += val; + } + + /* NOTE: In case of ecall, we need to adjust mepc in the context */ + + if (FE310_IRQ_ECALLM == irq) + { + *mepc += 4; + } + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + /* Current regs non-zero indicates that we are processing an interrupt; + * g_current_regs is also used to manage interrupt level context switches. + * + * Nested interrupts are not supported + */ + + DEBUGASSERT(g_current_regs == NULL); + g_current_regs = regs; + + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); +#endif + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = (uint32_t *)g_current_regs; + g_current_regs = NULL; + + /* Set machine previous privilege mode to machine mode */ + + *(regs + REG_INT_CTX_NDX) |= 0x3 << 11; + + return regs; +} + diff --git a/arch/risc-v/src/fe310/fe310_lowputc.c b/arch/risc-v/src/fe310/fe310_lowputc.c new file mode 100644 index 00000000000..765e7baf2e3 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_lowputc.c @@ -0,0 +1,131 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_lowputc.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "fe310_config.h" +#include "hardware/fe310_memorymap.h" +#include "hardware/fe310_uart.h" +#include "fe310.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select UART parameters for the selected console */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define FE310_CONSOLE_BASE FE310_UART0_BASE +# define FE310_CONSOLE_BAUD CONFIG_UART0_BAUD +# define FE310_CONSOLE_BITS CONFIG_UART0_BITS +# define FE310_CONSOLE_PARITY CONFIG_UART0_PARITY +# define FE310_CONSOLE_2STOP CONFIG_UART0_2STOP +# define FE310_CONSOLE_TX GPIO_UART0_TX +# define FE310_CONSOLE_RX GPIO_UART0_RX +# define HAVE_UART +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define FE310_CONSOLE_BASE FE310_UART1_BASE +# define FE310_CONSOLE_BAUD CONFIG_UART1_BAUD +# define FE310_CONSOLE_BITS CONFIG_UART1_BITS +# define FE310_CONSOLE_PARITY CONFIG_UART1_PARITY +# define FE310_CONSOLE_2STOP CONFIG_UART1_2STOP +# define FE310_CONSOLE_TX GPIO_UART1_TX +# define FE310_CONSOLE_RX GPIO_UART1_RX +# define HAVE_UART +# endif +#endif /* HAVE_CONSOLE */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Wait until the TX data register is empty */ + + while ((getreg32(FE310_CONSOLE_BASE + UART_TXDATA_OFFSET) & UART_TX_FULL)) + ; + + /* Then send the character */ + + putreg32((uint32_t)ch, FE310_CONSOLE_BASE + UART_TXDATA_OFFSET); + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: fe310_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void fe310_lowsetup(void) +{ +#if defined(HAVE_UART) + + /* Enable and configure the selected console device */ + +#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + + /* TODO: Configure the UART Baud Rate */ + +#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_UART */ +} diff --git a/arch/risc-v/src/fe310/fe310_lowputc.h b/arch/risc-v/src/fe310/fe310_lowputc.h new file mode 100644 index 00000000000..2ef3d760a42 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_lowputc.h @@ -0,0 +1,75 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_lowputc.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_FE310_FE310_LOWPUTC_H +#define __ARCH_RISCV_SRC_FE310_FE310_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: fe310_lowsetup + ****************************************************************************/ + +EXTERN void fe310_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_FE310_FE310_LOWPUTC_H */ + diff --git a/arch/risc-v/src/fe310/fe310_memorymap.h b/arch/risc-v/src/fe310/fe310_memorymap.h new file mode 100644 index 00000000000..cdefb15e8ea --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_memorymap.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_memorymap.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef _ARCH_RISCV_SRC_FE310_FE310_MEMORYMAP_H +#define _ARCH_RISCV_SRC_FE310_FE310_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/fe310_memorymap.h" +#include "hardware/fe310_uart.h" +#include "hardware/fe310_clic.h" +#include "hardware/fe310_plic.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Idle thread stack starts from _ebss */ + +#ifndef __ASSEMBLY__ +#define FE310_IDLESTACK_BASE (uint32_t)&_ebss +#else +#define FE310_IDLESTACK_BASE _ebss +#endif + +#define FE310_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) +#define FE310_IDLESTACK_TOP (FE310_IDLESTACK_BASE + FE310_IDLESTACK_SIZE) + +#endif /* _ARCH_RISCV_SRC_FE310_FE310_MEMORYMAP_H */ + diff --git a/arch/risc-v/src/fe310/fe310_serial.c b/arch/risc-v/src/fe310/fe310_serial.c new file mode 100644 index 00000000000..919d9e63f05 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_serial.c @@ -0,0 +1,723 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_serial.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "fe310_config.h" +#include "chip.h" +#include "fe310.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART0_SERIAL_CONSOLE +# if defined(CONFIG_FE310_UART0) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# undef TTYS1_DEV /* No ttyS1 */ +# define SERIAL_CONSOLE 1 +# else +# undef TTYS0_DEV +# undef TTYS1_DEV +# endif +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of up_earlyserialinit(), up_serialinit(), and + * up_putc(). + */ + +#ifdef HAVE_UART_DEVICE + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t im; /* Interrupt mask state */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers */ + +static uint32_t up_serialin(struct up_dev_s *priv, int offset); +static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value); +static void up_restoreuartint(struct up_dev_s *priv, uint8_t im); +static void up_disableuartint(struct up_dev_s *priv, uint8_t *im); + +/* Serial driver methods */ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context, FAR void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_FE310_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +static uint32_t g_rxdata; +#endif + +#ifdef CONFIG_FE310_UART0 +static struct up_dev_s g_uart0priv = +{ + .uartbase = FE310_UART0_BASE, + .baud = CONFIG_UART0_BAUD, + .irq = FE310_IRQ_UART0, +}; + +static uart_dev_t g_uart0port = +{ +#if SERIAL_CONSOLE == 1 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static uint32_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: up_restoreuartint + ****************************************************************************/ + +static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) +{ + priv->im = im; + up_serialout(priv, UART_IE_OFFSET, im); +} + +/**************************************************************************** + * Name: up_disableuartint + ****************************************************************************/ + +static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) +{ + /* Return the current interrupt mask value */ + + if (im) + { + *im = priv->im; + } + + /* Disable all interrupts */ + + priv->im = 0; + up_serialout(priv, UART_IE_OFFSET, 0); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + +#if 0 /* TODO: Setup divisor */ +#endif + + /* Enable RX */ + + up_serialout(priv, UART_RXCTL_OFFSET, 1); + + /* Enable TX */ + + up_serialout(priv, UART_TXCTL_OFFSET, 1); + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + int ret; + + /* Initialize interrupt generation on the peripheral */ + + up_serialout(priv, UART_IE_OFFSET, UART_IE_TXWM | UART_IE_RXWM); + + ret = irq_attach(priv->irq, up_interrupt, dev); + + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); + + /* Detach from the interrupt */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct up_dev_s *priv; + uint32_t status; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct up_dev_s *)dev->priv; + + /* Retrieve interrupt pending status */ + + status = up_serialin(priv, UART_IP_OFFSET); + + if (status & UART_IP_RXWM) + { + /* Process incoming bytes */ + + uart_recvchars(dev); + } + + if (status & UART_IP_TXWM) + { + /* Process outgoing bytes */ + + uart_xmitchars(dev); + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, uint32_t *status) +{ + /* Return status information */ + + if (status) + { + *status = 0; /* We are not yet tracking serial errors */ + } + + /* Return cached data */ + + return g_rxdata; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= UART_IE_RXWM; +#endif + } + else + { + priv->im &= ~UART_IE_RXWM; + } + + up_serialout(priv, UART_IE_OFFSET, priv->im); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return true is data is available in the receive data buffer */ + + uint32_t rxdata = up_serialin(priv, UART_RXDATA_OFFSET); + + /* NOTE: In FE310, actual data is also retrieved */ + + g_rxdata = rxdata & 0xff; + + return (rxdata & UART_RX_EMPTY) == 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + up_serialout(priv, UART_TXDATA_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= UART_IE_TXWM; + up_serialout(priv, UART_IE_OFFSET, priv->im); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->im &= ~UART_IE_TXWM; + up_serialout(priv, UART_IE_OFFSET, priv->im); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return TRUE if the Transmit buffer register is not full */ + + return (up_serialin(priv, UART_TXDATA_OFFSET) & UART_TX_FULL) == 0; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + + /* Return TRUE if the Transmit shift register is empty */ + + return (up_serialin(priv, UART_TXDATA_OFFSET) & UART_TX_FULL) != 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before up_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +void up_earlyserialinit(void) +{ + /* Disable interrupts from all UARTS. The console is enabled in + * fe310_consoleinit(). + */ + + up_disableuartint(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + up_disableuartint(TTYS1_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; + uint8_t imr; + + up_disableuartint(priv, &imr); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + up_restoreuartint(priv, imr); +#endif + return ch; +} + +/**************************************************************************** + * Name: up_earlyserialinit, up_serialinit, and up_putc + * + * Description: + * stubs that may be needed. These stubs would be used if all UARTs are + * disabled. In that case, the logic in common/up_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * + ****************************************************************************/ + +#else /* HAVE_UART_DEVICE */ +void up_earlyserialinit(void) +{ +} + +void up_serialinit(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ + diff --git a/arch/risc-v/src/fe310/fe310_start.c b/arch/risc-v/src/fe310/fe310_start.c new file mode 100644 index 00000000000..562ed7168c9 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_start.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_init.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "fe310.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +uint32_t g_idle_topstack = FE310_IDLESTACK_TOP; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fe310_start + ****************************************************************************/ + +void __fe310_start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + showprogress('A'); + + /* Configure the UART so we can get debug output */ + + fe310_lowsetup(); + + showprogress('B'); + +#ifdef USE_EARLYSERIALINIT + up_earlyserialinit(); +#endif + /* Do board initialization */ + + fe310_boardinitialize(); + + showprogress('C'); + + /* Call nx_start() */ + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} + + diff --git a/arch/risc-v/src/fe310/fe310_timerisr.c b/arch/risc-v/src/fe310/fe310_timerisr.c new file mode 100644 index 00000000000..c1ae8451640 --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_timerisr.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_timerisr.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" + +#include "fe310.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define getreg64(a) (*(volatile uint64_t *)(a)) +#define putreg64(v,a) (*(volatile uint64_t *)(a) = (v)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool _b_tick_started = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fe310_reload_mtimecmp + ****************************************************************************/ + +static void fe310_reload_mtimecmp(void) +{ + irqstate_t flags = spin_lock_irqsave(); + + uint64_t current; + uint64_t next; + + if (!_b_tick_started) + { + _b_tick_started = true; + current = getreg64(FE310_CLIC_MTIME); + } + else + { + current = getreg64(FE310_CLIC_MTIMECMP); + } + + uint64_t tick = 100000; /* TODO */ + next = current + tick; + + putreg64(next, FE310_CLIC_MTIMECMP); + + spin_unlock_irqrestore(flags); +} + +/**************************************************************************** + * Name: fe310_timerisr + ****************************************************************************/ + +static int fe310_timerisr(int irq, void *context, FAR void *arg) +{ + fe310_reload_mtimecmp(); + + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riscv_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void riscv_timer_initialize(void) +{ + /* Attach timer interrupt handler */ + + (void)irq_attach(FE310_IRQ_MTIMER, fe310_timerisr, NULL); + + /* Reload CLIC mtimecmp */ + + fe310_reload_mtimecmp(); + + /* And enable the timer interrupt */ + + up_enable_irq(FE310_IRQ_MTIMER); +} + diff --git a/arch/risc-v/src/fe310/fe310_vectors.S b/arch/risc-v/src/fe310/fe310_vectors.S new file mode 100644 index 00000000000..e9a86bbd62e --- /dev/null +++ b/arch/risc-v/src/fe310/fe310_vectors.S @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/fe310_vectors.S + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + + .section .text.vec + .global __reset_vec + .global __trap_vec + +/**************************************************************************** + * Name: __reset_vec + ****************************************************************************/ + +__reset_vec: + jal __start + +/**************************************************************************** + * Name: exception_common + ****************************************************************************/ + +__trap_vec: + j exception_common + nop + diff --git a/arch/risc-v/src/fe310/hardware/fe310_clic.h b/arch/risc-v/src/fe310/hardware/fe310_clic.h new file mode 100644 index 00000000000..24097f3db9b --- /dev/null +++ b/arch/risc-v/src/fe310/hardware/fe310_clic.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/hardware/fe310_clic.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H +#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FE310_CLIC_MTIMECMP (FE310_CLIC_BASE + 0x4000) +#define FE310_CLIC_MTIME (FE310_CLIC_BASE + 0xbff8) + +#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_CLIC_H */ diff --git a/arch/risc-v/src/fe310/hardware/fe310_memorymap.h b/arch/risc-v/src/fe310/hardware/fe310_memorymap.h new file mode 100644 index 00000000000..0d534f0b729 --- /dev/null +++ b/arch/risc-v/src/fe310/hardware/fe310_memorymap.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/hardware/fe310_memorymap.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_MEMORYMAP_H +#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Base Address ****************************************************/ + +#define FE310_CLIC_BASE 0x02000000 +#define FE310_PLIC_BASE 0x0c000000 + +#define FE310_GPIO_BASE 0x10012000 /* 0x10012000 - 0x10012fff: GPIO */ +#define FE310_UART0_BASE 0x10013000 /* 0x10013000 - 0x10013fff: UART0 */ +#define FE310_UART1_BASE 0x10023000 /* 0x10023000 - 0x10023fff: UART1 */ + +#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_MEMORYMAP_H */ + diff --git a/arch/risc-v/src/fe310/hardware/fe310_plic.h b/arch/risc-v/src/fe310/hardware/fe310_plic.h new file mode 100644 index 00000000000..66311742600 --- /dev/null +++ b/arch/risc-v/src/fe310/hardware/fe310_plic.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/hardware/fe310_plic.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_PLIC_H +#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_PLIC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FE310_PLIC_PRIORITY (FE310_PLIC_BASE + 0x000000) +#define FE310_PLIC_PENDING1 (FE310_PLIC_BASE + 0x001000) +#define FE310_PLIC_ENABLE1 (FE310_PLIC_BASE + 0x002000) +#define FE310_PLIC_THRESHOLD (FE310_PLIC_BASE + 0x200000) +#define FE310_PLIC_CLAIM (FE310_PLIC_BASE + 0x200004) + +#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_PLIC_H */ diff --git a/arch/risc-v/src/fe310/hardware/fe310_uart.h b/arch/risc-v/src/fe310/hardware/fe310_uart.h new file mode 100644 index 00000000000..9a3a98d578d --- /dev/null +++ b/arch/risc-v/src/fe310/hardware/fe310_uart.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/hardware/fe310_uart.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef ARCH_RISCV_SRC_FE310_CHIP_FE310_UART_H +#define ARCH_RISCV_SRC_FE310_CHIP_FE310_UART_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define UART_TXDATA_OFFSET 0x00 +#define UART_RXDATA_OFFSET 0x04 +#define UART_TXCTL_OFFSET 0x08 +#define UART_RXCTL_OFFSET 0x0c +#define UART_IE_OFFSET 0x10 +#define UART_IP_OFFSET 0x14 +#define UART_DIV_OFFSET 0x18 + +#ifdef CONFIG_FE310_UART0 +# define FE310_UART0_TXDATA (FE310_UART0_BASE + UART_TXDATA_OFFSET) +# define FE310_UART0_RXDATA (FE310_UART0_BASE + UART_RXDATA_OFFSET) +# define FE310_UART0_TXCTRL (FE310_UART0_BASE + UART_TXCTRL_OFFSET) +# define FE310_UART0_RXCTRL (FE310_UART0_BASE + UART_RXCTRL_OFFSET) +# define FE310_UART0_IE (FE310_UART0_BASE + UART_IE_OFFSET) +# define FE310_UART0_IP (FE310_UART0_BASE + UART_IP_OFFSET) +# define FE310_UART0_DIV (FE310_UART0_BASE + UART_DIV_OFFSET) +#endif + +#define UART_TX_FULL (1 << 31) /* TX FIFO full (in TXDATA) */ +#define UART_RX_EMPTY (1 << 31) /* RX FIFO empty (in RXDATA) */ + +#define UART_TX_EN (1 << 0) /* Enable TX (in TXCTL) */ +#define UART_NSTOP (1 << 1) /* Number of stop bits (in TXCTL) */ + +#define UART_RX_EN (1 << 0) /* Enable RX (in RXCTL) */ + +#define UART_IE_TXWM (1 << 0) /* Enable TX wartermark int (in IE) */ +#define UART_IE_RXWM (1 << 1) /* Enable RX wartermark int (in IE) */ + +#define UART_IP_TXWM (1 << 0) /* TX wartermark pending (in IP) */ +#define UART_IP_RXWM (1 << 1) /* RX wartermark pending (in IP) */ + +#endif /* _ARCH_RISCV_SRC_FE310_CHIP_FE310_UART_H */ diff --git a/arch/risc-v/src/fe310/up_schedulesigaction.c b/arch/risc-v/src/fe310/up_schedulesigaction.c new file mode 100644 index 00000000000..23f4a557896 --- /dev/null +++ b/arch/risc-v/src/fe310/up_schedulesigaction.c @@ -0,0 +1,208 @@ +/**************************************************************************** + * arch/risc-v/src/fe310/up_schedulesigaction.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Based on arch/risc-v/src/nr5m100/up_schedulesigaction.c + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" +#include "up_arch.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'igdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + irqstate_t flags; + uint32_t int_ctx; + + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + /* Make sure that interrupts are disabled */ + + flags = enter_critical_section(); + + /* Refuse to handle nested signal actions */ + + if (!tcb->xcp.sigdeliver) + { + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. + */ + + sinfo("rtcb=0x%p g_current_regs=0x%p\n", + this_task(), g_current_regs); + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ + + if (!g_current_regs) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + * + * Hmmm... there looks like a latent bug here: The following + * logic would fail in the strange case where we are in an + * interrupt handler, the thread is signalling itself, but + * a context switch to another task has occurred so that + * g_current_regs does not refer to the thread of this_task()! + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = g_current_regs[REG_EPC]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver; + + int_ctx = g_current_regs[REG_INT_CTX]; + int_ctx &= ~MSTATUS_MIE; + + g_current_regs[REG_INT_CTX] = int_ctx; + + /* And make sure that the saved context in the TCB + * is the same as the interrupt return context. + */ + + up_savestate(tcb->xcp.regs); + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + g_current_regs[REG_EPC], g_current_regs[REG_INT_CTX]); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC]; + tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_INT_CTX]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver; + + int_ctx = tcb->xcp.regs[REG_INT_CTX]; + int_ctx &= ~MSTATUS_MIE; + + tcb->xcp.regs[REG_INT_CTX] = int_ctx; + + sinfo("PC/STATUS Saved: %08x/%08x New: %08x/%08x\n", + tcb->xcp.saved_epc, tcb->xcp.saved_status, + tcb->xcp.regs[REG_EPC], tcb->xcp.regs[REG_INT_CTX]); + } + } + + leave_critical_section(flags); +} diff --git a/arch/risc-v/src/rv32im/up_assert.c b/arch/risc-v/src/rv32im/up_assert.c index f13c0b2c519..6ed3b73d518 100644 --- a/arch/risc-v/src/rv32im/up_assert.c +++ b/arch/risc-v/src/rv32im/up_assert.c @@ -74,6 +74,218 @@ * Private Functions ****************************************************************************/ + +#ifdef CONFIG_ARCH_STACKDUMP + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getsp + ****************************************************************************/ + +static inline uint32_t up_getsp(void) +{ + register uint32_t sp; + __asm__ + ( + "\tadd %0, x0, x2\n" + : "=r"(sp) + ); + return sp; +} + +/**************************************************************************** + * Name: up_stackdump + ****************************************************************************/ + +static void up_stackdump(uint32_t sp, uint32_t stack_base) +{ + uint32_t stack ; + + for (stack = sp & ~0x1f; stack < stack_base; stack += 32) + { + uint32_t *ptr = (uint32_t *)stack; + _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +} + + +/**************************************************************************** + * Name: up_taskdump + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg) +{ + /* Dump interesting properties of this task */ + +#if CONFIG_TASK_NAME_SIZE > 0 + _alert("%s: PID=%d Stack Used=%lu of %lu\n", + tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb), + (unsigned long)tcb->adj_stack_size); +#else + _alert("PID: %d Stack Used=%lu of %lu\n", + tcb->pid, (unsigned long)up_check_tcbstack(tcb), + (unsigned long)tcb->adj_stack_size); +#endif +} +#endif + +/**************************************************************************** + * Name: up_showtasks + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +static inline void up_showtasks(void) +{ + /* Dump interesting properties of each task in the crash environment */ + + sched_foreach(up_taskdump, NULL); +} +#else +# define up_showtasks() +#endif + +/**************************************************************************** + * Name: up_registerdump + ****************************************************************************/ + +static inline void up_registerdump(void) +{ + /* Are user registers available from interrupt processing? */ + + if (g_current_regs) + { + _alert("EPC:%08x \n", + g_current_regs[REG_EPC]); + _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", + g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], + g_current_regs[REG_A3], g_current_regs[REG_A4], g_current_regs[REG_A5], + g_current_regs[REG_A6], g_current_regs[REG_A7]); + _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", + g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], + g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], + g_current_regs[REG_T6]); + _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], + g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], + g_current_regs[REG_S6], g_current_regs[REG_S7]); + _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n", + g_current_regs[REG_S8], g_current_regs[REG_S9], g_current_regs[REG_S10], + g_current_regs[REG_S11]); +#ifdef RISCV_SAVE_GP + _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], + g_current_regs[REG_TP], g_current_regs[REG_RA]); +#else + _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n", + g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP], + g_current_regs[REG_RA]); +#endif + } +} + +/**************************************************************************** + * Name: up_dumpstate + ****************************************************************************/ + +static void up_dumpstate(void) +{ + struct tcb_s *rtcb = running_task(); + uint32_t sp = up_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Dump the registers (if available) */ + + up_registerdump(); + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */ + { + ustackbase = g_idle_topstack - 4; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint32_t)rtcb->adj_stack_size; + } + + /* Get the limits on the interrupt stack memory */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = (uint32_t)&g_intstackbase; + istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; + + /* Show interrupt stack info */ + + _alert("sp: %08x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %08x\n", istackbase); + _alert(" size: %08x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + up_stackdump(sp, istackbase); + + /* Extract the user stack pointer which should lie + * at the base of the interrupt stack. + */ + + sp = (uint32_t)&g_intstackbase; + _alert("sp: %08x\n", sp); + } + else if (g_current_regs) + { + _alert("ERROR: Stack pointer is not within the interrupt stack\n"); + up_stackdump(istackbase - istacksize, istackbase); + } + + /* Show user stack info */ + + _alert("User stack:\n"); + _alert(" base: %08x\n", ustackbase); + _alert(" size: %08x\n", ustacksize); +#else + _alert("sp: %08x\n", sp); + _alert("stack base: %08x\n", ustackbase); + _alert("stack size: %08x\n", ustacksize); +#endif + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { + _alert("ERROR: Stack pointer is not within allocated stack\n"); + up_stackdump(ustackbase - ustacksize, ustackbase); + } + else + { + up_stackdump(sp, ustackbase); + } +} + +#endif /* CONFIG_ARCH_STACKDUMP */ + + /**************************************************************************** * Name: _up_assert ****************************************************************************/ @@ -167,6 +379,10 @@ void up_assert(const uint8_t *filename, int lineno) up_dumpstate(); + /* Dump the state of all tasks (if available) */ + + up_showtasks(); + #ifdef CONFIG_ARCH_USBDUMP /* Dump USB trace data */ diff --git a/arch/risc-v/src/rv32im/up_dumpstate.c b/arch/risc-v/src/rv32im/up_dumpstate.c index 4c422732d6e..c4f1fb9a8f2 100644 --- a/arch/risc-v/src/rv32im/up_dumpstate.c +++ b/arch/risc-v/src/rv32im/up_dumpstate.c @@ -57,179 +57,3 @@ #include "sched/sched.h" #include "up_internal.h" -#ifdef CONFIG_ARCH_STACKDUMP - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_getsp - ****************************************************************************/ - -static inline uint32_t up_getsp(void) -{ - register uint32_t sp; - __asm__ - ( - "\tadd %0, x0, x2\n" - : "=r"(sp) - ); - return sp; -} - -/**************************************************************************** - * Name: up_stackdump - ****************************************************************************/ - -static void up_stackdump(uint32_t sp, uint32_t stack_base) -{ - uint32_t stack ; - - for (stack = sp & ~0x1f; stack < stack_base; stack += 32) - { - uint32_t *ptr = (uint32_t *)stack; - _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n", - stack, ptr[0], ptr[1], ptr[2], ptr[3], - ptr[4], ptr[5], ptr[6], ptr[7]); - } -} - -/**************************************************************************** - * Name: up_registerdump - ****************************************************************************/ - -static inline void up_registerdump(void) -{ - /* Are user registers available from interrupt processing? */ - - if (g_current_regs) - { - _alert("EPC:%08x \n", - g_current_regs[REG_EPC]); - _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x A6:%08x A7:%08x\n", - g_current_regs[REG_A0], g_current_regs[REG_A1], g_current_regs[REG_A2], - g_current_regs[REG_A3], g_current_regs[REG_A4], g_current_regs[REG_A5], - g_current_regs[REG_A6], g_current_regs[REG_A7]); - _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n", - g_current_regs[REG_T0], g_current_regs[REG_T1], g_current_regs[REG_T2], - g_current_regs[REG_T3], g_current_regs[REG_T4], g_current_regs[REG_T5], - g_current_regs[REG_T6]); - _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", - g_current_regs[REG_S0], g_current_regs[REG_S1], g_current_regs[REG_S2], - g_current_regs[REG_S3], g_current_regs[REG_S4], g_current_regs[REG_S5], - g_current_regs[REG_S6], g_current_regs[REG_S7]); - _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n", - g_current_regs[REG_S8], g_current_regs[REG_S9], g_current_regs[REG_S10], - g_current_regs[REG_S11]); -#ifdef RISCV_SAVE_GP - _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n", - g_current_regs[REG_GP], g_current_regs[REG_SP], g_current_regs[REG_FP], - g_current_regs[REG_TP], g_current_regs[REG_RA]); -#else - _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n", - g_current_regs[REG_SP], g_current_regs[REG_FP], g_current_regs[REG_TP], - g_current_regs[REG_RA]); -#endif - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_dumpstate - ****************************************************************************/ - -void up_dumpstate(void) -{ - struct tcb_s *rtcb = running_task(); - uint32_t sp = up_getsp(); - uint32_t ustackbase; - uint32_t ustacksize; -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - uint32_t istackbase; - uint32_t istacksize; -#endif - - /* Dump the registers (if available) */ - - up_registerdump(); - - /* Get the limits on the user stack memory */ - - if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */ - { - ustackbase = g_idle_topstack - 4; - ustacksize = CONFIG_IDLETHREAD_STACKSIZE; - } - else - { - ustackbase = (uint32_t)rtcb->adj_stack_ptr; - ustacksize = (uint32_t)rtcb->adj_stack_size; - } - - /* Get the limits on the interrupt stack memory */ - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - istackbase = (uint32_t)&g_intstackbase; - istacksize = (CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4; - - /* Show interrupt stack info */ - - _alert("sp: %08x\n", sp); - _alert("IRQ stack:\n"); - _alert(" base: %08x\n", istackbase); - _alert(" size: %08x\n", istacksize); - - /* Does the current stack pointer lie within the interrupt - * stack? - */ - - if (sp <= istackbase && sp > istackbase - istacksize) - { - /* Yes.. dump the interrupt stack */ - - up_stackdump(sp, istackbase); - - /* Extract the user stack pointer which should lie - * at the base of the interrupt stack. - */ - - sp = g_intstackbase; - _alert("sp: %08x\n", sp); - } - else if (g_current_regs) - { - _alert("ERROR: Stack pointer is not within the interrupt stack\n"); - up_stackdump(istackbase - istacksize, istackbase); - } - - /* Show user stack info */ - - _alert("User stack:\n"); - _alert(" base: %08x\n", ustackbase); - _alert(" size: %08x\n", ustacksize); -#else - _alert("sp: %08x\n", sp); - _alert("stack base: %08x\n", ustackbase); - _alert("stack size: %08x\n", ustacksize); -#endif - - /* Dump the user stack if the stack pointer lies within the allocated user - * stack memory. - */ - - if (sp > ustackbase || sp <= ustackbase - ustacksize) - { - _alert("ERROR: Stack pointer is not within allocated stack\n"); - up_stackdump(ustackbase - ustacksize, ustackbase); - } - else - { - up_stackdump(sp, ustackbase); - } -} - -#endif /* CONFIG_ARCH_STACKDUMP */ diff --git a/boards/Kconfig b/boards/Kconfig index 7939d795fcf..935e02ee14a 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -297,6 +297,13 @@ config ARCH_BOARD_GAPUINO ---help--- Nuttx port for gapuino, a GAP8 evaluation board. +config ARCH_BOARD_HIFIVE1_REVB + bool "HiFive1 Rev B board" + depends on ARCH_CHIP_FE310 + ---help--- + This is the board configuration for the port of NuttX to the SiFive HiFive1 + Rev B board. This board features the RISC-V FE310-G002 + config ARCH_BOARD_HYMINI_STM32V bool "HY-Mini STM32v board" depends on ARCH_CHIP_STM32F103VC @@ -1998,6 +2005,7 @@ config ARCH_BOARD default "freedom-kl25z" if ARCH_BOARD_FREEDOM_KL25Z default "freedom-kl26z" if ARCH_BOARD_FREEDOM_KL26Z default "gapuino" if ARCH_BOARD_GAPUINO + default "hifive1-revb" if ARCH_BOARD_HIFIVE1_REVB default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V default "imxrt1020-evk" if ARCH_BOARD_IMXRT1020_EVK default "imxrt1050-evk" if ARCH_BOARD_IMXRT1050_EVK @@ -2710,6 +2718,9 @@ endif if ARCH_BOARD_NR5M100_NEXYS4 source "boards/risc-v/nr5m100/nr5m100-nexys4/Kconfig" endif +if ARCH_BOARD_HIFIVE_REVB +source "boards/risc-v/fe310/hifive1-revb/Kconfig" +endif if ARCH_BOARD_SIM source "boards/sim/sim/sim/Kconfig" endif diff --git a/boards/risc-v/fe310/drivers/Kconfig b/boards/risc-v/fe310/drivers/Kconfig new file mode 100644 index 00000000000..f72f3c094ce --- /dev/null +++ b/boards/risc-v/fe310/drivers/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/boards/risc-v/fe310/hifive1-revb/Kconfig b/boards/risc-v/fe310/hifive1-revb/Kconfig new file mode 100644 index 00000000000..83d99d09fc0 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_HIFIVE1_REVB + +endif diff --git a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig new file mode 100644 index 00000000000..231c422058e --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="hifive1-revb" +CONFIG_ARCH_BOARD_HIFIVE1_REVB=y +CONFIG_ARCH_CHIP="fe310" +CONFIG_ARCH_CHIP_FE310=y +CONFIG_ARCH_CHIP_FE310_G002=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ERROR=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_DEV_ZERO=y +CONFIG_DISABLE_MQUEUE=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_WRITABLE=y +CONFIG_IDLETHREAD_STACKSIZE=1536 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_MAX_TASKS=8 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_SMALL=y +CONFIG_NFILE_DESCRIPTORS=6 +CONFIG_NFILE_STREAMS=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_CD=y +CONFIG_NSH_DISABLE_CP=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_MKDIR=y +CONFIG_NSH_DISABLE_RM=y +CONFIG_NSH_DISABLE_RMDIR=y +CONFIG_NSH_DISABLE_UMOUNT=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_PTHREAD_STACK_DEFAULT=1536 +CONFIG_RAM_SIZE=16384 +CONFIG_RAM_START=0x80000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/boards/risc-v/fe310/hifive1-revb/include/board.h b/boards/risc-v/fe310/hifive1-revb/include/board.h new file mode 100644 index 00000000000..c62bbd3ca68 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/include/board.h @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/risc-v/fe310/hifive1-revb/include/board.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_FE310_HIFIVE_REVB_INCLUDE_BOARD_H +#define __BOARDS_RISCV_FE310_HIFIVE_REVB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#include "fe310.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: fe310_boardinitialize + ****************************************************************************/ + +void fe310_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISC-V_FE310_HIFIVE-REVB_INCLUDE_BOARD_H */ + diff --git a/boards/risc-v/fe310/hifive1-revb/scripts/Make.defs b/boards/risc-v/fe310/hifive1-revb/scripts/Make.defs new file mode 100644 index 00000000000..1af651664b4 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/scripts/Make.defs @@ -0,0 +1,116 @@ +############################################################################ +# boards/risc-v/fe310/hifive1-revb/scripts/Make.defs +# +# Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. +# Author: Masayuki Ishikawa +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/risc-v/src/rv32im/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g + ASARCHCPUFLAGS += -Wa,-g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCPUFLAGS = -march=rv32imac -mabi=ilp32 +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS) + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs -melf32lriscv +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g -melf32lriscv +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/boards/risc-v/fe310/hifive1-revb/scripts/ld.script b/boards/risc-v/fe310/hifive1-revb/scripts/ld.script new file mode 100644 index 00000000000..a67c37b5768 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/scripts/ld.script @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/risc-v/fe310/hifive1-revb/scripts/ld.script + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x20400000, LENGTH = 4096K + sram (rwx) : ORIGIN = 0x80000000, LENGTH = 16K +} + +OUTPUT_ARCH("riscv") + +ENTRY(_stext) +EXTERN(_vectors) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/fe310/hifive1-revb/src/Makefile b/boards/risc-v/fe310/hifive1-revb/src/Makefile new file mode 100644 index 00000000000..f57822806fa --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/src/Makefile @@ -0,0 +1,44 @@ +############################################################################ +# boards/risc-v/fe310/hifive1-revb/src/Makefile +# +# Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. +# Author: Masayuki Ishikawa +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CSRCS = fe310_bringup.c fe310_boot.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += fe310_appinit.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/risc-v/fe310/hifive1-revb/src/fe310_appinit.c b/boards/risc-v/fe310/hifive1-revb/src/fe310_appinit.c new file mode 100644 index 00000000000..cf44b427d01 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/src/fe310_appinit.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * boards/risc-v/fe310/hifive1-revb/src/fe310_appinit.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "fe310.h" +#include "hifive1-revb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return fe310_bringup(); +#endif +} diff --git a/boards/risc-v/fe310/hifive1-revb/src/fe310_boot.c b/boards/risc-v/fe310/hifive1-revb/src/fe310_boot.c new file mode 100644 index 00000000000..7fbcf443ba1 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/src/fe310_boot.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/risc-v/fe310/hifive1-revb/src/fe310_boot.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fe310_boardinitialize + * + * Description: + * All FE310 architectures must provide the following entry point. + * This entry point is called early in the intitialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void fe310_boardinitialize(void) +{ +} diff --git a/boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c b/boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c new file mode 100644 index 00000000000..f2b203f27c4 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/risc-v/fe310/hifive1-revb/src/fe310_bringup.c + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "fe310.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: fe310_bringup + ****************************************************************************/ + +int fe310_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", "/proc", ret); + } +#endif + + return ret; +} diff --git a/boards/risc-v/fe310/hifive1-revb/src/hifive1-revb.h b/boards/risc-v/fe310/hifive1-revb/src/hifive1-revb.h new file mode 100644 index 00000000000..c07caf89672 --- /dev/null +++ b/boards/risc-v/fe310/hifive1-revb/src/hifive1-revb.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * boards/risc-v/fe310/hifive1-revb/src/hifive1-revb.h + * + * Copyright (C) 2019 Masayuki Ishikawa. All rights reserved. + * Author: Masayuki Ishikawa + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_FE310_HIFIVE1_REVB_SRC_HIFIVE1_REVB_H +#define __BOARDS_RISCV_FE310_HIFIVE1_REVB_SRC_HIFIVE1_REVB_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +int fe310_bringup(void); + +#endif /* __BOARDS_RISCV_FE310_HIFIVE1_REVB_SRC_HIFIVE1_REVB_H */ diff --git a/tools/configure.sh b/tools/configure.sh index db9a489368c..d18edd002b4 100755 --- a/tools/configure.sh +++ b/tools/configure.sh @@ -149,7 +149,7 @@ chips="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450 lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52 nuc1xx rx65n s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7 stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx - pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811 + pic32mz lm32 mor1kx m32262f8 sh7032 fe310 gap8 nr5m100 sim qemu esp32 z16f2811 ez80 z180 z8 z80" for arc in ${archs}; do