diff --git a/arch/arm/src/calypso/calypso_timer.c b/arch/arm/src/calypso/calypso_timer.c
index 86c98b8aa6d..548e2240638 100644
--- a/arch/arm/src/calypso/calypso_timer.c
+++ b/arch/arm/src/calypso/calypso_timer.c
@@ -47,118 +47,128 @@
 
 #include "up_arch.h"
 
-#define BASE_ADDR_TIMER		0xfffe3800
-#define TIMER2_OFFSET		0x3000
+#define BASE_ADDR_TIMER        0xfffe3800
+#define TIMER2_OFFSET        0x3000
 
-#define TIMER_REG(n, m)		(((n)-1) ? (BASE_ADDR_TIMER + TIMER2_OFFSET + (m)) : (BASE_ADDR_TIMER + (m)))
+#define TIMER_REG(n, m)        (((n)-1) ? (BASE_ADDR_TIMER + TIMER2_OFFSET + (m)) : (BASE_ADDR_TIMER + (m)))
 
-enum timer_reg {
-	CNTL_TIMER	= 0x00,
-	LOAD_TIMER	= 0x02,
-	READ_TIMER	= 0x04,
+enum timer_reg
+{
+  CNTL_TIMER    = 0x00,
+  LOAD_TIMER    = 0x02,
+  READ_TIMER    = 0x04,
 };
 
-enum timer_ctl {
-	CNTL_START		= (1 << 0),
-	CNTL_AUTO_RELOAD	= (1 << 1),
-	CNTL_CLOCK_ENABLE	= (1 << 5),
+enum timer_ctl
+{
+  CNTL_START        = (1 << 0),
+  CNTL_AUTO_RELOAD  = (1 << 1),
+  CNTL_CLOCK_ENABLE = (1 << 5),
 };
 
 /* Regular Timers (1 and 2) */
 
 void hwtimer_enable(int num, int on)
 {
-	uint8_t ctl;
+  uint8_t ctl;
 
-	if (num < 1 || num > 2) {
-		printf("Unknown timer %d\n", num);
-		return;
-	}
+  if (num < 1 || num > 2)
+    {
+      printf("Unknown timer %d\n", num);
+      return;
+    }
 
-	ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
-	if (on)
-		ctl |= CNTL_START|CNTL_CLOCK_ENABLE;
-	else
-		ctl &= ~CNTL_START;
-	putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
+  ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
+  if (on)
+      ctl |= CNTL_START|CNTL_CLOCK_ENABLE;
+  else
+      ctl &= ~CNTL_START;
+
+  putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
 }
 
 void hwtimer_config(int num, uint8_t pre_scale, int auto_reload)
 {
-	uint8_t ctl;
+  uint8_t ctl;
 
-	ctl = (pre_scale & 0x7) << 2;
-	if (auto_reload)
-		ctl |= CNTL_AUTO_RELOAD;
+  ctl = (pre_scale & 0x7) << 2;
+  if (auto_reload)
+      ctl |= CNTL_AUTO_RELOAD;
 
-	putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
+  putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
 }
 
 void hwtimer_load(int num, uint16_t val)
 {
-	putreg16(val, TIMER_REG(num, LOAD_TIMER));
+  putreg16(val, TIMER_REG(num, LOAD_TIMER));
 }
 
 uint16_t hwtimer_read(int num)
 {
-	uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
+  uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
 
-	/* somehow a read results in an abort */
-	if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
-		return 0xFFFF;
-	return getreg16(TIMER_REG(num, READ_TIMER));
+  /* somehow a read results in an abort */
+
+  if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
+      return 0xFFFF;
+
+  return getreg16(TIMER_REG(num, READ_TIMER));
 }
 
 /****************************************************************************
  * Watchdog Timer
  ****************************************************************************/
 
-#define BASE_ADDR_WDOG		0xfffff800
-#define WDOG_REG(m)		(BASE_ADDR_WDOG + m)
+#define BASE_ADDR_WDOG        0xfffff800
+#define WDOG_REG(m)        (BASE_ADDR_WDOG + m)
 
 enum wdog_reg
 {
-  WD_CNTL_TIMER	= CNTL_TIMER,
-  WD_LOAD_TIMER	= LOAD_TIMER,
-  WD_READ_TIMER	= 0x02,
-  WD_MODE		= 0x04,
+  WD_CNTL_TIMER    = CNTL_TIMER,
+  WD_LOAD_TIMER    = LOAD_TIMER,
+  WD_READ_TIMER    = 0x02,
+  WD_MODE          = 0x04,
 };
 
 enum wdog_ctl
 {
-  WD_CTL_START = (1 << 7),
+  WD_CTL_START       = (1 << 7),
   WD_CTL_AUTO_RELOAD = (1 << 8)
 };
 
 enum wdog_mode
 {
-  WD_MODE_DIS_ARM = 0xF5,
+  WD_MODE_DIS_ARM     = 0xF5,
   WD_MODE_DIS_CONFIRM = 0xA0,
-  WD_MODE_ENABLE = (1 << 15)
+  WD_MODE_ENABLE      = (1 << 15)
 };
 
 #define WD_CTL_PRESCALE(value) (((value)&0x07) << 9)
 
 static void wdog_irq(__unused enum irq_nr nr)
 {
-	puts("=> WATCHDOG\n");
+  puts("=> WATCHDOG\n");
 }
 
 void wdog_enable(int on)
 {
-	if (!on) {
-		putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
-		putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
-	}
+  if (!on)
+    {
+      putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
+      putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
+    }
 }
 
 void wdog_reset(void)
 {
-	// enable watchdog
-	putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
-	// force expiration
-	putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
-	putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
+  // enable watchdog
+
+  putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
+
+  // force expiration
+
+  putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
+  putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
 }
 
 /****************************************************************************
@@ -176,10 +186,10 @@ void wdog_reset(void)
 
 int up_timerisr(int irq, uint32_t *regs)
 {
-   /* Process timer interrupt */
+ /* Process timer interrupt */
 
-   sched_process_timer();
-   return 0;
+ sched_process_timer();
+ return 0;
 }
 
 /****************************************************************************
@@ -199,12 +209,13 @@ void up_timer_initialize(void)
 
   /* The timer runs at 13MHz / 32, i.e. 406.25kHz */
   /* 4062 ticks until expiry yields 100Hz interrupt */
+
   hwtimer_load(2, 4062);
   hwtimer_config(2, 0, 1);
   hwtimer_enable(2, 1);
 
   /* Attach and enable the timer interrupt */
+
   irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr);
   up_enable_irq(IRQ_SYSTIMER);
 }
-
diff --git a/arch/arm/src/calypso/calypso_uwire.c b/arch/arm/src/calypso/calypso_uwire.c
index eaf62db9868..d837a7abdc2 100644
--- a/arch/arm/src/calypso/calypso_uwire.c
+++ b/arch/arm/src/calypso/calypso_uwire.c
@@ -46,107 +46,116 @@
 
 #include "up_arch.h"
 
-#define BASE_ADDR_UWIRE	0xfffe4000
-#define UWIRE_REG(n)	(BASE_ADDR_UWIRE+(n))
+#define BASE_ADDR_UWIRE    0xfffe4000
+#define UWIRE_REG(n)    (BASE_ADDR_UWIRE+(n))
 
-enum uwire_regs {
-	REG_DATA	= 0x00,
-	REG_CSR		= 0x02,
-	REG_SR1		= 0x04,
-	REG_SR2		= 0x06,
-	REG_SR3		= 0x08,
+enum uwire_regs
+{
+  REG_DATA    = 0x00,
+  REG_CSR     = 0x02,
+  REG_SR1     = 0x04,
+  REG_SR2     = 0x06,
+  REG_SR3     = 0x08,
 };
 
-#define UWIRE_CSR_BITS_RD(n)	(((n) & 0x1f) << 0)
-#define UWIRE_CSR_BITS_WR(n)	(((n) & 0x1f) << 5)
-#define UWIRE_CSR_IDX(n)	(((n) & 3) << 10)
-#define UWIRE_CSR_CS_CMD	(1 << 12)
-#define UWIRE_CSR_START		(1 << 13)
-#define UWIRE_CSR_CSRB		(1 << 14)
-#define UWIRE_CSR_RDRB		(1 << 15)
+#define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0)
+#define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5)
+#define UWIRE_CSR_IDX(n)     (((n) & 3) << 10)
+#define UWIRE_CSR_CS_CMD     (1 << 12)
+#define UWIRE_CSR_START      (1 << 13)
+#define UWIRE_CSR_CSRB       (1 << 14)
+#define UWIRE_CSR_RDRB       (1 << 15)
 
-#define UWIRE_CSn_EDGE_RD	(1 << 0)	/* 1=falling 0=rising */
-#define UWIRE_CSn_EDGE_WR	(1 << 1)	/* 1=falling 0=rising */
-#define UWIRE_CSn_CS_LVL	(1 << 2)
-#define UWIRE_CSn_FRQ_DIV2	(0 << 3)
-#define UWIRE_CSn_FRQ_DIV4	(1 << 3)
-#define UWIRE_CSn_FRQ_DIV8	(2 << 3)
+#define UWIRE_CSn_EDGE_RD    (1 << 0)    /* 1=falling 0=rising */
+#define UWIRE_CSn_EDGE_WR    (1 << 1)    /* 1=falling 0=rising */
+#define UWIRE_CSn_CS_LVL     (1 << 2)
+#define UWIRE_CSn_FRQ_DIV2   (0 << 3)
+#define UWIRE_CSn_FRQ_DIV4   (1 << 3)
+#define UWIRE_CSn_FRQ_DIV8   (2 << 3)
 #define UWIRE_CSn_CKH
 
-#define UWIRE_CSn_SHIFT(n)	(((n) & 1) ? 6 : 0)
-#define UWIRE_CSn_REG(n)	(((n) & 2) ? REG_SR2 : REG_SR1)
+#define UWIRE_CSn_SHIFT(n)   (((n) & 1) ? 6 : 0)
+#define UWIRE_CSn_REG(n)     (((n) & 2) ? REG_SR2 : REG_SR1)
 
-#define UWIRE_SR3_CLK_EN	(1 << 0)
-#define UWIRE_SR3_CLK_DIV2	(0 << 1)
-#define UWIRE_SR3_CLK_DIV4	(1 << 1)
-#define UWIRE_SR3_CLK_DIV7	(2 << 1)
-#define UWIRE_SR3_CLK_DIV10	(3 << 1)
+#define UWIRE_SR3_CLK_EN     (1 << 0)
+#define UWIRE_SR3_CLK_DIV2   (0 << 1)
+#define UWIRE_SR3_CLK_DIV4   (1 << 1)
+#define UWIRE_SR3_CLK_DIV7   (2 << 1)
+#define UWIRE_SR3_CLK_DIV10  (3 << 1)
 
 static inline void _uwire_wait(int mask, int val)
 {
-	while ((getreg16(UWIRE_REG(REG_CSR)) & mask) != val);
+  while ((getreg16(UWIRE_REG(REG_CSR)) & mask) != val);
 }
 
 void uwire_init(void)
 {
-	putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));
-	/* FIXME only init CS0 for now */
-	putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
-		UWIRE_REG(UWIRE_CSn_REG(0)));
-	putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
-	_uwire_wait(UWIRE_CSR_CSRB, 0);
+  putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));
+
+  /* FIXME only init CS0 for now */
+
+  putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
+           UWIRE_REG(UWIRE_CSn_REG(0)));
+  putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
+  _uwire_wait(UWIRE_CSR_CSRB, 0);
 }
 
 int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
 {
-	uint16_t tmp = 0;
+  uint16_t tmp = 0;
 
-	if (bitlen <= 0 || bitlen > 16)
-		return -1;
-	if (cs < 0 || cs > 4)
-		return -1;
+  if (bitlen <= 0 || bitlen > 16)
+      return -1;
 
-	/* FIXME uwire_init always selects CS0 for now */
+  if (cs < 0 || cs > 4)
+      return -1;
 
-	dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
+  /* FIXME uwire_init always selects CS0 for now */
 
-	/* select the chip */
-	putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
-	_uwire_wait(UWIRE_CSR_CSRB, 0);
+  dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
 
-	if (dout) {
-		if (bitlen <= 8)
-			tmp = *(uint8_t *)dout;
-		else if (bitlen <= 16)
-			tmp = *(uint16_t *)dout;
-		tmp <<= 16 - bitlen; /* align to MSB */
-		putreg16(tmp, UWIRE_REG(REG_DATA));
-		dbg(", data_out=0x%04hx", tmp);
-	}
+  /* select the chip */
 
-	tmp =	(dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
-		(din  ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
-		UWIRE_CSR_START;
-	putreg16(tmp, UWIRE_REG(REG_CSR));
+  putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
+  _uwire_wait(UWIRE_CSR_CSRB, 0);
 
-	_uwire_wait(UWIRE_CSR_CSRB, 0);
+  if (dout)
+    {
+      if (bitlen <= 8)
+          tmp = *(uint8_t *)dout;
+      else if (bitlen <= 16)
+          tmp = *(uint16_t *)dout;
 
-	if (din) {
-		_uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
+      tmp <<= 16 - bitlen; /* align to MSB */
+      putreg16(tmp, UWIRE_REG(REG_DATA));
+      dbg(", data_out=0x%04hx", tmp);
+    }
 
-		tmp = getreg16(UWIRE_REG(REG_DATA));
-		dbg(", data_in=0x%08x", tmp);
+  tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
+        (din  ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
+         UWIRE_CSR_START;
+  putreg16(tmp, UWIRE_REG(REG_CSR));
+  _uwire_wait(UWIRE_CSR_CSRB, 0);
 
-		if (bitlen <= 8)
-			*(uint8_t *)din = tmp & 0xff;
-		else if (bitlen <= 16)
-			*(uint16_t *)din = tmp & 0xffff;
-	}
-	/* unselect the chip */
-	putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
-	_uwire_wait(UWIRE_CSR_CSRB, 0);
+  if (din)
+    {
+      _uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
 
-	dbg(")\n");
+      tmp = getreg16(UWIRE_REG(REG_DATA));
+      dbg(", data_in=0x%08x", tmp);
 
-	return 0;
+      if (bitlen <= 8)
+          *(uint8_t *)din = tmp & 0xff;
+      else if (bitlen <= 16)
+          *(uint16_t *)din = tmp & 0xffff;
+    }
+
+  /* unselect the chip */
+
+  putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
+  _uwire_wait(UWIRE_CSR_CSRB, 0);
+
+  dbg(")\n");
+
+  return 0;
 }
diff --git a/arch/arm/src/calypso/clock.c b/arch/arm/src/calypso/clock.c
index 497300e2875..29dc2f8273a 100644
--- a/arch/arm/src/calypso/clock.c
+++ b/arch/arm/src/calypso/clock.c
@@ -49,172 +49,182 @@
 
 #include "up_arch.h"
 
-#define REG_DPLL		0xffff9800
-#define DPLL_LOCK		(1 << 0)
-#define DPLL_BREAKLN		(1 << 1)
-#define DPLL_BYPASS_DIV_SHIFT	2		/* 2 bits */
-#define DPLL_PLL_ENABLE		(1 << 4)
-#define DPLL_PLL_DIV_SHIFT	5		/* 2 bits */
-#define DPLL_PLL_MULT_SHIFT	7		/* 5 bits */
-#define DPLL_TEST		(1 << 12)
-#define DPLL_IOB		(1 << 13)	/* Initialize on break */
-#define DPLL_IAI		(1 << 14)	/* Initialize after Idle */
+#define REG_DPLL              0xffff9800
+#define DPLL_LOCK             (1 << 0)
+#define DPLL_BREAKLN          (1 << 1)
+#define DPLL_BYPASS_DIV_SHIFT 2         /* 2 bits */
+#define DPLL_PLL_ENABLE       (1 << 4)
+#define DPLL_PLL_DIV_SHIFT    5         /* 2 bits */
+#define DPLL_PLL_MULT_SHIFT   7         /* 5 bits */
+#define DPLL_TEST             (1 << 12)
+#define DPLL_IOB              (1 << 13) /* Initialize on break */
+#define DPLL_IAI              (1 << 14) /* Initialize after Idle */
 
-#define BASE_ADDR_CLKM	0xfffffd00
-#define CLKM_REG(m)	(BASE_ADDR_CLKM+(m))
+#define BASE_ADDR_CLKM        0xfffffd00
+#define CLKM_REG(m)           (BASE_ADDR_CLKM+(m))
 
-enum clkm_reg {
-	CNTL_ARM_CLK	= 0,
-	CNTL_CLK	= 2,
-	CNTL_RST	= 4,
-	CNTL_ARM_DIV	= 8,
+enum clkm_reg
+{
+  CNTL_ARM_CLK  = 0,
+  CNTL_CLK      = 2,
+  CNTL_RST      = 4,
+  CNTL_ARM_DIV  = 8,
 };
 
 /* CNTL_ARM_CLK */
-#define ARM_CLK_BIG_SLEEP	(1 << 0)	/* MCU Master Clock enabled? */
-#define ARM_CLK_CLKIN_SEL0	(1 << 1)	/* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */
-#define ARM_CLK_CLKIN_SEL	(1 << 2)	/* 0 = VTCXO or 1 = CLKIN */
-#define ARM_CLK_MCLK_DIV5	(1 << 3)	/* enable 1.5 or 2.5 division factor */
-#define ARM_CLK_MCLK_DIV_SHIFT	4		/* 3 bits */
-#define ARM_CLK_DEEP_POWER_SHIFT	8
-#define ARM_CLK_DEEP_SLEEP	12
+
+#define ARM_CLK_BIG_SLEEP     (1 << 0)    /* MCU Master Clock enabled? */
+#define ARM_CLK_CLKIN_SEL0    (1 << 1)    /* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */
+#define ARM_CLK_CLKIN_SEL     (1 << 2)    /* 0 = VTCXO or 1 = CLKIN */
+#define ARM_CLK_MCLK_DIV5     (1 << 3)    /* enable 1.5 or 2.5 division factor */
+#define ARM_CLK_MCLK_DIV_SHIFT   4        /* 3 bits */
+#define ARM_CLK_DEEP_POWER_SHIFT 8
+#define ARM_CLK_DEEP_SLEEP       12
 
 /* CNTL_CLK */
-#define CLK_IRQ_CLK_DIS		(1 << 0)	/* IRQ clock control (0 always, 1 according ARM_MCLK_EN) */
-#define CLK_BRIDGE_CLK_DIS	(1 << 1)
-#define CLK_TIMER_CLK_DIS	(1 << 2)
-#define CLK_DPLL_DIS		(1 << 3)	/* 0: DPLL is not stopped during SLEEP */
-#define CLK_CLKOUT_EN		(1 << 4)	/* Enable CLKOUT output pins */
-#define CLK_EN_IDLE3_FLG	(1 << 5)	/* DSP idle flag control (1 =
-						 * SAM/HOM register forced to HOM when DSP IDLE3) */
-#define CLK_VCLKOUT_DIV2	(1 << 6)	/* 1: VCLKOUT-FR is divided by 2 */
-#define CLK_VTCXO_DIV2		(1 << 7)	/* 1: VTCXO is dividied by 2 */
+#define CLK_IRQ_CLK_DIS       (1 << 0)    /* IRQ clock control (0 always, 1 according ARM_MCLK_EN) */
+#define CLK_BRIDGE_CLK_DIS    (1 << 1)
+#define CLK_TIMER_CLK_DIS     (1 << 2)
+#define CLK_DPLL_DIS          (1 << 3)    /* 0: DPLL is not stopped during SLEEP */
+#define CLK_CLKOUT_EN         (1 << 4)    /* Enable CLKOUT output pins */
+#define CLK_EN_IDLE3_FLG      (1 << 5)    /* DSP idle flag control (1 =
+                                           * SAM/HOM register forced to HOM when DSP IDLE3) */
+#define CLK_VCLKOUT_DIV2      (1 << 6)    /* 1: VCLKOUT-FR is divided by 2 */
+#define CLK_VTCXO_DIV2        (1 << 7)    /* 1: VTCXO is dividied by 2 */
 
-#define BASE_ADDR_MEMIF		0xfffffb00
-#define MEMIF_REG(x)		(BASE_ADDR_MEMIF+(x))
+#define BASE_ADDR_MEMIF       0xfffffb00
+#define MEMIF_REG(x)          (BASE_ADDR_MEMIF+(x))
 
-enum memif_reg {
-	API_RHEA_CTL	= 0x0e,
-	EXTRA_CONF	= 0x10,
+enum memif_reg
+{
+  API_RHEA_CTL  = 0x0e,
+  EXTRA_CONF    = 0x10,
 };
 
 static void dump_reg16(uint32_t addr, char *name)
 {
-	printf("%s=0x%04x\n", name, getreg16(addr));
+  printf("%s=0x%04x\n", name, getreg16(addr));
 }
 
 void calypso_clk_dump(void)
 {
-	dump_reg16(REG_DPLL, "REG_DPLL");
-	dump_reg16(CLKM_REG(CNTL_ARM_CLK), "CNTL_ARM_CLK");
-	dump_reg16(CLKM_REG(CNTL_CLK), "CNTL_CLK");
-	dump_reg16(CLKM_REG(CNTL_RST), "CNTL_RST");
-	dump_reg16(CLKM_REG(CNTL_ARM_DIV), "CNTL_ARM_DIV");
+  dump_reg16(REG_DPLL, "REG_DPLL");
+  dump_reg16(CLKM_REG(CNTL_ARM_CLK), "CNTL_ARM_CLK");
+  dump_reg16(CLKM_REG(CNTL_CLK), "CNTL_CLK");
+  dump_reg16(CLKM_REG(CNTL_RST), "CNTL_RST");
+  dump_reg16(CLKM_REG(CNTL_ARM_DIV), "CNTL_ARM_DIV");
 }
 
 void calypso_pll_set(uint16_t inp)
 {
-	uint8_t mult = inp >> 8;
-	uint8_t div = inp & 0xff;
-	uint16_t reg = getreg16(REG_DPLL);
+  uint8_t mult = inp >> 8;
+  uint8_t div = inp & 0xff;
+  uint16_t reg = getreg16(REG_DPLL);
 
-	reg &= ~0x0fe0;
-	reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT;
-	reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT;
-	reg |= DPLL_PLL_ENABLE;
+  reg &= ~0x0fe0;
+  reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT;
+  reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT;
+  reg |= DPLL_PLL_ENABLE;
 
-	putreg16(reg, REG_DPLL);
+  putreg16(reg, REG_DPLL);
 }
 
 void calypso_reset_set(enum calypso_rst calypso_rst, int active)
 {
-	uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
+  uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
 
-	if (active)
-		reg |= calypso_rst;
-	else
-		reg &= ~calypso_rst;
+  if (active)
+      reg |= calypso_rst;
+  else
+      reg &= ~calypso_rst;
 
-	putreg8(reg, CLKM_REG(CNTL_RST));
+  putreg8(reg, CLKM_REG(CNTL_RST));
 }
 
 int calypso_reset_get(enum calypso_rst calypso_rst)
 {
-	uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
+  uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
 
-	if (reg & calypso_rst)
-		return 1;
-	else
-		return 0;
+  if (reg & calypso_rst)
+      return 1;
+  else
+      return 0;
 }
 
 void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
 {
-	uint16_t cntl_clock = getreg16(CLKM_REG(CNTL_CLK));
-	uint16_t cntl_arm_clk = getreg16(CLKM_REG(CNTL_ARM_CLK));
+  uint16_t cntl_clock = getreg16(CLKM_REG(CNTL_CLK));
+  uint16_t cntl_arm_clk = getreg16(CLKM_REG(CNTL_ARM_CLK));
 
-	/* First set the vtcxo_div2 */
-	cntl_clock &= ~CLK_VCLKOUT_DIV2;
-	if (vtcxo_div2)
-		cntl_clock |= CLK_VTCXO_DIV2;
-	else
-		cntl_clock &= ~CLK_VTCXO_DIV2;
-	putreg16(cntl_clock, CLKM_REG(CNTL_CLK));
+  /* First set the vtcxo_div2 */
 
-	/* Then configure the MCLK divider */
-	cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0;
-	if (mclk_div & 0x80) {
-		mclk_div &= ~0x80;
-		cntl_arm_clk |= ARM_CLK_MCLK_DIV5;
-	} else
-		cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5;
-	cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT);
-	cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT);
-	putreg16(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
+  cntl_clock &= ~CLK_VCLKOUT_DIV2;
+  if (vtcxo_div2)
+      cntl_clock |= CLK_VTCXO_DIV2;
+  else
+      cntl_clock &= ~CLK_VTCXO_DIV2;
 
-	/* Then finally set the PLL */
-	calypso_pll_set(inp);
+  putreg16(cntl_clock, CLKM_REG(CNTL_CLK));
+
+  /* Then configure the MCLK divider */
+
+  cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0;
+  if (mclk_div & 0x80)
+    {
+      mclk_div &= ~0x80;
+      cntl_arm_clk |= ARM_CLK_MCLK_DIV5;
+    }
+  else
+    cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5;
+
+  cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT);
+  cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT);
+  putreg16(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
+
+  /* Then finally set the PLL */
+
+  calypso_pll_set(inp);
 }
 
 void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
-		     enum calypso_mem_width width, int we)
+                     enum calypso_mem_width width, int we)
 {
-	putreg16((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7),
-	       BASE_ADDR_MEMIF + bank);
+  putreg16((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7),
+           BASE_ADDR_MEMIF + bank);
 }
 
 void calypso_bootrom(int enable)
 {
-	uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
+  uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
 
-	conf |= (3 << 8);
+  conf |= (3 << 8);
 
-	if (enable)
-		conf &= ~(1 << 9);
+  if (enable)
+      conf &= ~(1 << 9);
 
-	putreg16(conf, MEMIF_REG(EXTRA_CONF));
+  putreg16(conf, MEMIF_REG(EXTRA_CONF));
 }
 
 void calypso_debugunit(int enable)
 {
-	uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
+  uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
 
-	if (enable)
-		conf &= ~(1 << 11);
-	else
-		conf |= (1 << 11);
+  if (enable)
+      conf &= ~(1 << 11);
+  else
+      conf |= (1 << 11);
 
-	putreg16(conf, MEMIF_REG(EXTRA_CONF));
+  putreg16(conf, MEMIF_REG(EXTRA_CONF));
 }
 
-#define REG_RHEA_CNTL	0xfffff900
-#define REG_API_CNTL	0xfffff902
-#define REG_ARM_RHEA	0xfffff904
+#define REG_RHEA_CNTL   0xfffff900
+#define REG_API_CNTL    0xfffff902
+#define REG_ARM_RHEA    0xfffff904
 
 void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
-		      uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1)
+                      uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1)
 {
-	putreg16(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL);
-	putreg16(ws_h | (ws_l << 5), REG_API_CNTL);
-	putreg16(w_en0 | (w_en1 << 1), REG_ARM_RHEA);
+  putreg16(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL);
+  putreg16(ws_h | (ws_l << 5), REG_API_CNTL);
+  putreg16(w_en0 | (w_en1 << 1), REG_ARM_RHEA);
 }
diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c
index 27e7cbfc59a..59dbecc179e 100644
--- a/arch/arm/src/dm320/dm320_serial.c
+++ b/arch/arm/src/dm320/dm320_serial.c
@@ -71,14 +71,14 @@
 
 struct up_dev_s
 {
-  uint32_t uartbase;	/* Base address of UART registers */
-  uint32_t baud;		/* Configured baud */
-  uint16_t msr;			/* Saved MSR value */
-  uint8_t  irq;			/* IRQ associated with this UART */
-  uint8_t  parity;		/* 0=none, 1=odd, 2=even */
-  uint8_t  bits;		/* Number of bits (7 or 8) */
-  bool     stopbits2;	/* true: Configure with 2
-						 * stop bits instead of 1 */
+  uint32_t uartbase;    /* Base address of UART registers */
+  uint32_t baud;        /* Configured baud */
+  uint16_t msr;         /* Saved MSR value */
+  uint8_t  irq;         /* IRQ associated with this UART */
+  uint8_t  parity;      /* 0=none, 1=odd, 2=even */
+  uint8_t  bits;        /* Number of bits (7 or 8) */
+  bool     stopbits2;   /* true: Configure with 2
+                         * stop bits instead of 1 */
 };
 
 /****************************************************************************
diff --git a/arch/arm/src/kinetis/kinetis_wdog.c b/arch/arm/src/kinetis/kinetis_wdog.c
index 3c48ebe7d15..f506db2802f 100644
--- a/arch/arm/src/kinetis/kinetis_wdog.c
+++ b/arch/arm/src/kinetis/kinetis_wdog.c
@@ -108,7 +108,7 @@ void kinetis_wddisable(void)
   /* Unlock the watchdog so that we can write to registers */
 
   kinetis_wdunlock();
-	
+
   /* Clear the WDOGEN bit to disable the watchdog */
 
   regval  = getreg16(KINETIS_WDOG_STCTRLH);
diff --git a/arch/arm/src/str71x/str71x_xti.c b/arch/arm/src/str71x/str71x_xti.c
index 17997b85e3d..51d14e08669 100644
--- a/arch/arm/src/str71x/str71x_xti.c
+++ b/arch/arm/src/str71x/str71x_xti.c
@@ -119,7 +119,7 @@ static int str71x_xtiinterrupt(int irq, FAR void *context)
 
       if ((pending & mask) != 0)
         {
-	  /* Deliver the IRQ */
+          /* Deliver the IRQ */
 
           irq_dispatch(irq, context);
           pending &= ~mask;
diff --git a/arch/avr/src/at32uc3/at32uc3_gpioirq.c b/arch/avr/src/at32uc3/at32uc3_gpioirq.c
index 16e6cb5f08a..9a0b18075ce 100644
--- a/arch/avr/src/at32uc3/at32uc3_gpioirq.c
+++ b/arch/avr/src/at32uc3/at32uc3_gpioirq.c
@@ -94,14 +94,14 @@ static inline uint32_t gpio_baseaddress(unsigned int irq)
   if (irq < __IRQ_GPIO_PB0)
     {
       return AVR32_GPIO0_BASE;
-	}
+    }
   else
 #endif
 #if CONFIG_AVR32_GPIOIRQSETB != 0
   if (irq < NR_GPIO_IRQS)
     {
       return AVR32_GPIO1_BASE;
-	}
+    }
   else
 #endif
     {
@@ -132,7 +132,7 @@ static inline int gpio_pin(unsigned int irq)
     {
       pinset = CONFIG_AVR32_GPIOIRQSETA;
       pinirq = __IRQ_GPIO_PA0;
-	}
+    }
   else
 #endif
 #if CONFIG_AVR32_GPIOIRQSETB != 0
@@ -140,7 +140,7 @@ static inline int gpio_pin(unsigned int irq)
     {
       pinset = CONFIG_AVR32_GPIOIRQSETB;
       pinirq = __IRQ_GPIO_PB0;
-	}
+    }
   else
 #endif
     {
diff --git a/arch/avr/src/at32uc3/at32uc3_irq.c b/arch/avr/src/at32uc3/at32uc3_irq.c
index f22c72821bf..c5d7b8bc410 100644
--- a/arch/avr/src/at32uc3/at32uc3_irq.c
+++ b/arch/avr/src/at32uc3/at32uc3_irq.c
@@ -223,8 +223,8 @@ void up_irqinitialize(void)
 
   for (irq = 0; irq < AVR32_IRQ_NEVENTS; irq++)
     {
-	  irq_attach(irq, avr32_xcptn);
-	}
+      irq_attach(irq, avr32_xcptn);
+    }
 
   /* Initialize GPIO interrupt facilities */
 
diff --git a/arch/avr/src/at90usb/at90usb_serial.c b/arch/avr/src/at90usb/at90usb_serial.c
index 7732e427780..8af0aae45a4 100644
--- a/arch/avr/src/at90usb/at90usb_serial.c
+++ b/arch/avr/src/at90usb/at90usb_serial.c
@@ -373,7 +373,7 @@ static int usart1_receive(struct uart_dev_s *dev, FAR unsigned int *status)
 
   if (status)
     {
-	  *status = (FAR unsigned int)UCSR1A;
+      *status = (FAR unsigned int)UCSR1A;
     }
 
   /* Then return the actual received byte */
diff --git a/arch/mips/src/mips32/up_dumpstate.c b/arch/mips/src/mips32/up_dumpstate.c
index 714e9a882b0..0ed660cfa72 100644
--- a/arch/mips/src/mips32/up_dumpstate.c
+++ b/arch/mips/src/mips32/up_dumpstate.c
@@ -84,7 +84,7 @@ static inline uint32_t up_getsp(void)
   register uint32_t sp;
   __asm__
   (
-  	"\tadd  %0, $0, $29\n"
+    "\tadd  %0, $0, $29\n"
     : "=r"(sp)
   );
   return sp;
diff --git a/arch/rgmp/src/arm/arch_nuttx.c b/arch/rgmp/src/arm/arch_nuttx.c
index 0b6a638775e..dd737946d9d 100644
--- a/arch/rgmp/src/arm/arch_nuttx.c
+++ b/arch/rgmp/src/arm/arch_nuttx.c
@@ -43,38 +43,37 @@
 #include <arch/arch.h>
 #include <nuttx/sched.h>
 
-
 void nuttx_arch_init(void)
 {
-
 }
 
 void nuttx_arch_exit(void)
 {
-
 }
 
 void up_initial_state(struct tcb_s *tcb)
 {
-    struct Trapframe *tf;
+  struct Trapframe *tf;
 
-    if (tcb->pid != 0) {
-	tf = (struct Trapframe *)tcb->adj_stack_ptr-1;
-	memset(tf, 0, sizeof(struct Trapframe));
-	tf->tf_cpsr = SVC_MOD;
-	tf->tf_pc = (uint32_t)tcb->start;
-	tcb->xcp.tf = tf;
+  if (tcb->pid != 0)
+    {
+      tf = (struct Trapframe *)tcb->adj_stack_ptr-1;
+      memset(tf, 0, sizeof(struct Trapframe));
+      tf->tf_cpsr = SVC_MOD;
+      tf->tf_pc = (uint32_t)tcb->start;
+      tcb->xcp.tf = tf;
     }
 }
 
 void push_xcptcontext(struct xcptcontext *xcp)
 {
-    xcp->save_eip = xcp->tf->tf_pc;
-    xcp->save_eflags = xcp->tf->tf_cpsr;
+  xcp->save_eip = xcp->tf->tf_pc;
+  xcp->save_eflags = xcp->tf->tf_cpsr;
 
-    // set  interrupts disabled
-    xcp->tf->tf_pc = (uint32_t)up_sigentry;
-    xcp->tf->tf_cpsr |= CPSR_IF;
+  // set  interrupts disabled
+
+  xcp->tf->tf_pc = (uint32_t)up_sigentry;
+  xcp->tf->tf_cpsr |= CPSR_IF;
 }
 
 void pop_xcptcontext(struct xcptcontext *xcp)
diff --git a/arch/rgmp/src/bridge.c b/arch/rgmp/src/bridge.c
index 19aa7ef6887..46f45a8f593 100644
--- a/arch/rgmp/src/bridge.c
+++ b/arch/rgmp/src/bridge.c
@@ -51,81 +51,84 @@
 
 struct bridge
 {
-	struct rgmp_bridge *b;
-	sem_t rd_lock;
-	sem_t wr_lock;
+  struct rgmp_bridge *b;
+  sem_t rd_lock;
+  sem_t wr_lock;
 };
 
 static ssize_t up_bridge_read(struct file *filep, char *buffer, size_t len)
 {
-	ssize_t ret;
-    struct bridge *b = filep->f_inode->i_private;
+  ssize_t ret;
+  struct bridge *b = filep->f_inode->i_private;
 
-	sem_wait(&b->rd_lock);
-    ret = rgmp_bridge_read(b->b, buffer, len, 0);
-	sem_post(&b->rd_lock);
-	return ret;
+  sem_wait(&b->rd_lock);
+  ret = rgmp_bridge_read(b->b, buffer, len, 0);
+  sem_post(&b->rd_lock);
+  return ret;
 }
 
 static ssize_t up_bridge_write(struct file *filep, const char *buffer, size_t len)
 {
-	ssize_t ret;
-    struct bridge *b = filep->f_inode->i_private;
+  ssize_t ret;
+  struct bridge *b = filep->f_inode->i_private;
 
-	sem_wait(&b->wr_lock);
-    ret = rgmp_bridge_write(b->b, (char *)buffer, len, 0);
-	sem_post(&b->wr_lock);
-	return ret;
+  sem_wait(&b->wr_lock);
+  ret = rgmp_bridge_write(b->b, (char *)buffer, len, 0);
+  sem_post(&b->wr_lock);
+  return ret;
 }
 
 static int up_bridge_open(struct file *filep)
 {
-    return 0;
+  return 0;
 }
 
 static int up_bridge_close(struct file *filep)
 {
-    return 0;
+  return 0;
 }
 
 static const struct file_operations up_bridge_fops =
 {
-    .read = up_bridge_read,
-    .write = up_bridge_write,
-    .open = up_bridge_open,
-    .close = up_bridge_close,
+  .read = up_bridge_read,
+  .write = up_bridge_write,
+  .open = up_bridge_open,
+  .close = up_bridge_close,
 };
 
 int rtos_bridge_init(struct rgmp_bridge *b)
 {
-    int err;
-	struct bridge *bridge;
-    char path[30] = {'/', 'd', 'e', 'v', '/'};
+  int err;
+  struct bridge *bridge;
+  char path[30] = {'/', 'd', 'e', 'v', '/'};
 
-	if ((bridge = kmm_malloc(sizeof(*bridge))) == NULL)
-		goto err0;
+  if ((bridge = kmm_malloc(sizeof(*bridge))) == NULL)
+    goto err0;
 
-	bridge->b = b;
-	if ((err = sem_init(&bridge->rd_lock, 0, 1)) == ERROR)
-		goto err1;
-	if ((err = sem_init(&bridge->wr_lock, 0, 1)) == ERROR)
-		goto err1;
+  bridge->b = b;
+  if ((err = sem_init(&bridge->rd_lock, 0, 1)) == ERROR)
+    goto err1;
 
-	// make rgmp_bridge0 to be the console
-	if (strcmp(b->vdev->name, "rgmp_bridge0") == 0)
-	    strlcpy(path + 5, "console", 25);
-	else
-	    strlcpy(path + 5, b->vdev->name, 25);
+  if ((err = sem_init(&bridge->wr_lock, 0, 1)) == ERROR)
+    goto err1;
 
-	if ((err = register_driver(path, &up_bridge_fops, 0666, bridge)) == ERROR) {
-	    cprintf("NuttX: register bridge %s fail\n", b->vdev->name);
-		goto err1;
-	}
+  // make rgmp_bridge0 to be the console
 
-	return 0;
+  if (strcmp(b->vdev->name, "rgmp_bridge0") == 0)
+      strlcpy(path + 5, "console", 25);
+  else
+      strlcpy(path + 5, b->vdev->name, 25);
+
+  if ((err = register_driver(path, &up_bridge_fops, 0666, bridge)) == ERROR)
+    {
+      cprintf("NuttX: register bridge %s fail\n", b->vdev->name);
+      goto err1;
+    }
+
+  return 0;
 
 err1:
-	kmm_free(bridge);
+  kmm_free(bridge);
 err0:
-	return -1;
+  return -1;
 }
diff --git a/arch/rgmp/src/cxx.c b/arch/rgmp/src/cxx.c
index 99f42dfd274..8dfc6a697bf 100644
--- a/arch/rgmp/src/cxx.c
+++ b/arch/rgmp/src/cxx.c
@@ -5,15 +5,15 @@ int stderr = 2;
 
 void __stack_chk_fail_local(void)
 {
-	panic("stack check fail\n");
+  panic("stack check fail\n");
 }
 
 int __sprintf_chk(char *str, int flag, size_t strlen, const char *format)
 {
-	return snprintf(str, strlen, format);
+  return snprintf(str, strlen, format);
 }
 
 int dl_iterate_phdr(void* arg1, void* arg2)
 {
-    return -1;
+  return -1;
 }
diff --git a/arch/rgmp/src/rgmp.c b/arch/rgmp/src/rgmp.c
index 32289f55d30..12830090d14 100644
--- a/arch/rgmp/src/rgmp.c
+++ b/arch/rgmp/src/rgmp.c
@@ -65,106 +65,108 @@ const unsigned int rtos_tick_time = 10;
 
 void rtos_entry(void)
 {
-    os_start();
+  os_start();
 }
 
 void *rtos_get_page(void)
 {
-    return memalign(PTMEMSIZE, PTMEMSIZE);
+  return memalign(PTMEMSIZE, PTMEMSIZE);
 }
 
 void rtos_free_page(void *page)
 {
-    free(page);
+  free(page);
 }
 
 void *rtos_kmalloc(int size)
 {
-	return kmm_malloc(size);
+  return kmm_malloc(size);
 }
 
 void rtos_kfree(void *addr)
 {
-	kmm_free(addr);
+  kmm_free(addr);
 }
 
-/**
- * The interrupt can be nested. The pair of rtos_enter_interrupt()
+/* The interrupt can be nested. The pair of rtos_enter_interrupt()
  * and rtos_exit_interrupt() make sure the context switch is
  * performed only in the last IRQ exit.
  */
+
 void rtos_enter_interrupt(void)
 {
-    nest_irq++;
+  nest_irq++;
 }
 
 void rtos_exit_interrupt(void)
 {
-    local_irq_disable();
-    nest_irq--;
-    if (!nest_irq) {
-		struct tcb_s *rtcb = current_task;
-		struct tcb_s *ntcb;
+  local_irq_disable();
+  nest_irq--;
+  if (!nest_irq)
+    {
+      struct tcb_s *rtcb = current_task;
+      struct tcb_s *ntcb;
 
-		if (rtcb->xcp.sigdeliver) {
-			rtcb->xcp.ctx.tf = current_regs;
-			push_xcptcontext(&rtcb->xcp);
-		}
-		ntcb = (struct tcb_s*)g_readytorun.head;
-		// switch needed
-		if (rtcb != ntcb) {
-			rtcb->xcp.ctx.tf = current_regs;
-			current_task = ntcb;
-			rgmp_switch_to(&ntcb->xcp.ctx);
-		}
+      if (rtcb->xcp.sigdeliver)
+        {
+          rtcb->xcp.ctx.tf = current_regs;
+          push_xcptcontext(&rtcb->xcp);
+        }
+
+      ntcb = (struct tcb_s*)g_readytorun.head;
+
+      // switch needed
+
+      if (rtcb != ntcb)
+        {
+          rtcb->xcp.ctx.tf = current_regs;
+          current_task = ntcb;
+          rgmp_switch_to(&ntcb->xcp.ctx);
+        }
     }
 }
 
 void rtos_timer_isr(void *data)
 {
-    sched_process_timer();
+  sched_process_timer();
 }
 
-/**
- * RTOS semaphore operation
- */
+/* RTOS semaphore operation */
+
 int rtos_sem_init(struct semaphore *sem, int val)
 {
-	if ((sem->sem = kmm_malloc(sizeof(sem_t))) == NULL)
-		return -1;
-    return sem_init(sem->sem, 0, val);
+  if ((sem->sem = kmm_malloc(sizeof(sem_t))) == NULL)
+    return -1;
+  return sem_init(sem->sem, 0, val);
 }
 
 int rtos_sem_up(struct semaphore *sem)
 {
-    return sem_post(sem->sem);
+  return sem_post(sem->sem);
 }
 
 int rtos_sem_down(struct semaphore *sem)
 {
-    return sem_wait(sem->sem);
+  return sem_wait(sem->sem);
 }
 
 void rtos_stop_running(void)
 {
-    extern void nuttx_arch_exit(void);
+  extern void nuttx_arch_exit(void);
 
-    local_irq_disable();
+  local_irq_disable();
 
-    nuttx_arch_exit();
+  nuttx_arch_exit();
 
-    while (1)
-      {
-	arch_hlt();
-      }
+  while (1)
+    {
+      arch_hlt();
+    }
 }
 
 int rtos_vnet_init(struct rgmp_vnet *vnet)
 {
-	extern int vnet_init(struct rgmp_vnet *vnet);
+  extern int vnet_init(struct rgmp_vnet *vnet);
 
-	return vnet_init(vnet);
+  return vnet_init(vnet);
 }
-
-
-
diff --git a/arch/rgmp/src/x86/arch_nuttx.c b/arch/rgmp/src/x86/arch_nuttx.c
index 2ca3d02e046..d5ae6916862 100644
--- a/arch/rgmp/src/x86/arch_nuttx.c
+++ b/arch/rgmp/src/x86/arch_nuttx.c
@@ -62,34 +62,37 @@ void nuttx_arch_init(void)
 
 void nuttx_arch_exit(void)
 {
-    extern void e1000_mod_exit(void);
+  extern void e1000_mod_exit(void);
 
 #ifdef CONFIG_NET_E1000
-    e1000_mod_exit();
+  e1000_mod_exit();
 #endif
-
 }
 
 void up_initial_state(struct tcb_s *tcb)
 {
-    struct Trapframe *tf;
+  struct Trapframe *tf;
 
-    if (tcb->pid) {
-		tf = (struct Trapframe *)tcb->adj_stack_ptr - 1;
-		rgmp_setup_context(&tcb->xcp.ctx, tf, tcb->start, 1);
+  if (tcb->pid)
+    {
+      tf = (struct Trapframe *)tcb->adj_stack_ptr - 1;
+      rgmp_setup_context(&tcb->xcp.ctx, tf, tcb->start, 1);
+    }
+  else
+    {
+      rgmp_setup_context(&tcb->xcp.ctx, NULL, NULL, 0);
     }
-	else
-		rgmp_setup_context(&tcb->xcp.ctx, NULL, NULL, 0);
 }
 
 void push_xcptcontext(struct xcptcontext *xcp)
 {
-    xcp->save_eip = xcp->ctx.tf->tf_eip;
-    xcp->save_eflags = xcp->ctx.tf->tf_eflags;
+  xcp->save_eip = xcp->ctx.tf->tf_eip;
+  xcp->save_eflags = xcp->ctx.tf->tf_eflags;
 
-    // set up signal entry with interrupts disabled
-    xcp->ctx.tf->tf_eip = (uint32_t)up_sigentry;
-    xcp->ctx.tf->tf_eflags = 0;
+  // set up signal entry with interrupts disabled
+
+  xcp->ctx.tf->tf_eip = (uint32_t)up_sigentry;
+  xcp->ctx.tf->tf_eflags = 0;
 }
 
 void pop_xcptcontext(struct xcptcontext *xcp)
diff --git a/arch/sh/src/m16c/m16c_lowputc.c b/arch/sh/src/m16c/m16c_lowputc.c
index 830a25427c5..f38d75b06f7 100644
--- a/arch/sh/src/m16c/m16c_lowputc.c
+++ b/arch/sh/src/m16c/m16c_lowputc.c
@@ -167,7 +167,7 @@
  */
 
 #define M16C_UART_BRG_VALUE \
-	((M16C_XIN_FREQ / (16 * M16C_XIN_PRESCALER * M16C_UART_BAUD)) - 1)
+  ((M16C_XIN_FREQ / (16 * M16C_XIN_PRESCALER * M16C_UART_BAUD)) - 1)
 
 #endif /* HAVE_SERIALCONSOLE */
 
@@ -256,7 +256,7 @@ static inline void up_lowserialsetup(void)
   /* Set UART transmit/receive control register 1 to enable transmit and receive */
 
   putreg8(UART_C1_TE|UART_C1_RE, M16C_UART_BASE + M16C_UART_C1);
-	
+
   /* Set UART transmit/receive mode register data bits, stop bits, parity */
 
   putreg8(M16C_MR_VALUE, M16C_UART_BASE + M16C_UART_MR);
diff --git a/arch/sh/src/m16c/m16c_serial.c b/arch/sh/src/m16c/m16c_serial.c
index 69a33e626e7..9fb7cc56d30 100644
--- a/arch/sh/src/m16c/m16c_serial.c
+++ b/arch/sh/src/m16c/m16c_serial.c
@@ -594,7 +594,7 @@ static int up_setup(struct uart_dev_s *dev)
   /* Set UART transmit/receive control register 1 to enable transmit and receive */
 
   up_serialout(priv, M16C_UART_C1, UART_C1_TE|UART_C1_RE);
-	
+
   /* Set UART transmit/receive mode register data bits, stop bits, parity */
 
   regval = 0;
diff --git a/arch/sh/src/m16c/m16c_timerisr.c b/arch/sh/src/m16c/m16c_timerisr.c
index d26ff845e5f..adaa18af022 100644
--- a/arch/sh/src/m16c/m16c_timerisr.c
+++ b/arch/sh/src/m16c/m16c_timerisr.c
@@ -81,7 +81,7 @@
 
 #define M16C_DIVISOR (65535 * CLK_TCK)
 #define M16C_IDEAL_PRESCALER \
-	((M16C_XIN_FREQ + M16C_DIVISOR - 1) / M16C_DIVISOR)
+  ((M16C_XIN_FREQ + M16C_DIVISOR - 1) / M16C_DIVISOR)
 
 /* Now, given this idel prescaler value, pick between available choices: 1, 8, and 32 */
 
@@ -99,12 +99,12 @@
 /* Timer 0 Mode Settings */
 
 #define M16C_TA0MODE_CONFIG \
-	(TAnMR_TMOD_TIMER|TAnMR_MR_TMNOOUT|TAnMR_MR_TMNOGATE|M16C_PRESCALE_BITS)
+  (TAnMR_TMOD_TIMER|TAnMR_MR_TMNOOUT|TAnMR_MR_TMNOGATE|M16C_PRESCALE_BITS)
 
 /* The actual reload value matching the selected prescaler value */
 
 #define M16C_RELOAD_VALUE \
-	((M16C_XIN_FREQ / M16C_PRESCALE_VALUE / CLK_TCK)  - 1)
+  ((M16C_XIN_FREQ / M16C_PRESCALE_VALUE / CLK_TCK)  - 1)
 
 /****************************************************************************
  * Private Type Definitions
diff --git a/arch/sim/src/up_devconsole.c b/arch/sim/src/up_devconsole.c
index f17945e7763..6c4e519d0cf 100644
--- a/arch/sim/src/up_devconsole.c
+++ b/arch/sim/src/up_devconsole.c
@@ -69,10 +69,10 @@ static int     devconsole_poll(FAR struct file *filep, FAR struct pollfd *fds,
 
 static const struct file_operations devconsole_fops =
 {
-  .read		= devconsole_read,
-  .write	= devconsole_write,
+  .read   = devconsole_read,
+  .write  = devconsole_write,
 #ifndef CONFIG_DISABLE_POLL
-  .poll         = devconsole_poll,
+  .poll   = devconsole_poll,
 #endif
 };
 
@@ -108,7 +108,7 @@ static ssize_t devconsole_read(struct file *filep, char *buffer, size_t len)
         }
 
       *buffer++ = ch;
-	  nread++;
+       nread++;
 
       /* We have at least one character.  Return now if no further
        * characters are available without waiting.
diff --git a/arch/x86/src/i486/up_savestate.c b/arch/x86/src/i486/up_savestate.c
index ad280e4fd48..e8d1c6d612b 100644
--- a/arch/x86/src/i486/up_savestate.c
+++ b/arch/x86/src/i486/up_savestate.c
@@ -108,6 +108,6 @@ void up_savestate(uint32_t *regs)
     }
   else
     {
-	  DEBUGASSERT(regs[REG_SP] == current_regs[REG_ESP] + 4*BOTTOM_PRIO);
-	}
+      DEBUGASSERT(regs[REG_SP] == current_regs[REG_ESP] + 4*BOTTOM_PRIO);
+    }
 }
diff --git a/arch/z80/src/z180/z180_io.c b/arch/z80/src/z180/z180_io.c
index 7e738c953a6..e5b13a7eb7c 100644
--- a/arch/z80/src/z180/z180_io.c
+++ b/arch/z80/src/z180/z180_io.c
@@ -70,9 +70,9 @@
 void outp(char p, char c)
 {
   __asm
-	ld      c, 4(ix)	; port
-	ld      a, 5(ix)	; value
-	out     (c), a
+	ld	c, 4(ix)	; port
+	ld	a, 5(ix)	; value
+	out	(c), a
   __endasm;
 }
 
@@ -88,7 +88,7 @@ void outp(char p, char c)
 char inp(char p) __naked
 {
   __asm
-	ld      c, 4(ix)	;port
-	in      l, (c)
+	ld	c, 4(ix)	;port
+	in	l, (c)
   __endasm;
 }
diff --git a/arch/z80/src/z180/z180_irq.c b/arch/z80/src/z180/z180_irq.c
index 258be895288..d55bd34fc86 100644
--- a/arch/z80/src/z180/z180_irq.c
+++ b/arch/z80/src/z180/z180_irq.c
@@ -97,8 +97,8 @@ extern uintptr_t up_vectors[16];
 static void z180_seti(uint8_t value) __naked
 {
   __asm
-	ld      a, 4(ix)	;value
-	ld      l, a
+	ld	a, 4(ix)	; value
+	ld	l, a
   __endasm;
 }
 
diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c
index a821f1863eb..1faacb808db 100644
--- a/arch/z80/src/z8/z8_serial.c
+++ b/arch/z80/src/z8/z8_serial.c
@@ -77,15 +77,15 @@ extern uint32_t get_freq(void);
 
 struct z8_uart_s
 {
-  uint8_t volatile far* uartbase;		/* Base address of UART registers */
-  uint32_t     baud;		/* Configured baud */
-  bool         rxenabled;	/* RX interrupt enabled */
-  bool         txenabled;	/* TX interrupt enabled */
-  uint8_t      rxirq;		/* RX IRQ associated with this UART */
-  uint8_t      txirq;		/* RX IRQ associated with this UART */
-  uint8_t      parity;		/* 0=none, 1=odd, 2=even */
-  bool         stopbits2;	/* true: Configure with 2 stop bits
-							 * (instead of 1) */
+  uint8_t volatile far* uartbase; /* Base address of UART registers */
+  uint32_t     baud;              /* Configured baud */
+  bool         rxenabled;         /* RX interrupt enabled */
+  bool         txenabled;         /* TX interrupt enabled */
+  uint8_t      rxirq;             /* RX IRQ associated with this UART */
+  uint8_t      txirq;             /* RX IRQ associated with this UART */
+  uint8_t      parity;            /* 0=none, 1=odd, 2=even */
+  bool         stopbits2;         /* true: Configure with 2 stop bits
+                                   * (instead of 1) */
 };
 
 /****************************************************************************
diff --git a/arch/z80/src/z80/z80_io.c b/arch/z80/src/z80/z80_io.c
index 1db636d30e2..a44be35597e 100644
--- a/arch/z80/src/z80/z80_io.c
+++ b/arch/z80/src/z80/z80_io.c
@@ -70,9 +70,9 @@
 void outp(char p, char c)
 {
   __asm
-	ld      c, 4(ix)	; port
-	ld      a, 5(ix)	; value
-	out     (c), a
+	ld	c, 4(ix)	; port
+	ld	a, 5(ix)	; value
+	out	(c), a
   __endasm;
 }
 
@@ -88,7 +88,7 @@ void outp(char p, char c)
 char inp(char p) __naked
 {
   __asm
-	ld      c, 4(ix)	;port
-	in      l, (c)
+	ld	c, 4(ix)	;port
+	in	l, (c)
   __endasm;
 }