viewtool configuration will not support boad with STM32F103VC mounted; converted one stm3210e-eval configuration to use kconfig-frontends

configs/Kconfig

@@ -739,7 +739,7 @@ config ARCH_BOARD_US7032EVB1
 
 config ARCH_BOARD_VIEWTOOL_STM32F107
 	bool "ViewTool STM32F103/F107 with STM32F107"
-	depends on ARCH_CHIP_STM32F107VC
+	depends on ARCH_CHIP_STM32F107VC || ARCH_CHIP_STM32F103VCT6
 	select ARCH_HAVE_LEDS
 	select ARCH_HAVE_BUTTONS
 	---help---

configs/stm3210e-eval/buttons/appconfig

@@ -1,39 +0,0 @@
-############################################################################
-# configs/stm3210e-eval/buttons/appconfig
-#
-#   Copyright (C) 2011 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/buttons
-

configs/stm3210e-eval/composite/defconfig

@@ -44,7 +44,9 @@ CONFIG_INTELHEX_BINARY=y
 #
 # CONFIG_DEBUG is not set
 CONFIG_ARCH_HAVE_STACKCHECK=y
+CONFIG_ARCH_HAVE_HEAPCHECK=y
 # CONFIG_DEBUG_SYMBOLS is not set
+# CONFIG_DEBUG_NOOPT is not set
 
 #
 # System Type
@@ -65,6 +67,7 @@ CONFIG_ARCH="arm"
 #
 # ARM Options
 #
+# CONFIG_ARCH_CHIP_A1X is not set
 # CONFIG_ARCH_CHIP_C5471 is not set
 # CONFIG_ARCH_CHIP_CALYPSO is not set
 # CONFIG_ARCH_CHIP_DM320 is not set
@@ -112,7 +115,6 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
 # CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set
 # CONFIG_SERIAL_TERMIOS is not set
 CONFIG_SDIO_DMA=y
-CONFIG_SDIO_PREFLIGHT=y
 CONFIG_SDIO_DMAPRIO=0x00001000
 # CONFIG_SDIO_WIDTH_D1_ONLY is not set
 
@@ -151,7 +153,13 @@ CONFIG_SDIO_DMAPRIO=0x00001000
 # CONFIG_ARCH_CHIP_STM32F100VE is not set
 # CONFIG_ARCH_CHIP_STM32F103C4 is not set
 # CONFIG_ARCH_CHIP_STM32F103C8 is not set
+# CONFIG_ARCH_CHIP_STM32F103T8 is not set
+# CONFIG_ARCH_CHIP_STM32F103TB is not set
+# CONFIG_ARCH_CHIP_STM32F103CB is not set
+# CONFIG_ARCH_CHIP_STM32F103R8 is not set
 # CONFIG_ARCH_CHIP_STM32F103RB is not set
+# CONFIG_ARCH_CHIP_STM32F103V8 is not set
+# CONFIG_ARCH_CHIP_STM32F103VB is not set
 # CONFIG_ARCH_CHIP_STM32F103RET6 is not set
 # CONFIG_ARCH_CHIP_STM32F103VCT6 is not set
 # CONFIG_ARCH_CHIP_STM32F103VET6 is not set
@@ -159,6 +167,7 @@ CONFIG_ARCH_CHIP_STM32F103ZET6=y
 # CONFIG_ARCH_CHIP_STM32F105VBT7 is not set
 # CONFIG_ARCH_CHIP_STM32F107VC is not set
 # CONFIG_ARCH_CHIP_STM32F207IG is not set
+# CONFIG_ARCH_CHIP_STM32F207ZE is not set
 # CONFIG_ARCH_CHIP_STM32F302CB is not set
 # CONFIG_ARCH_CHIP_STM32F302CC is not set
 # CONFIG_ARCH_CHIP_STM32F302RB is not set
@@ -183,6 +192,11 @@ CONFIG_ARCH_CHIP_STM32F103ZET6=y
 # CONFIG_ARCH_CHIP_STM32F427V is not set
 # CONFIG_ARCH_CHIP_STM32F427Z is not set
 # CONFIG_ARCH_CHIP_STM32F427I is not set
+# CONFIG_ARCH_CHIP_STM32F429V is not set
+# CONFIG_ARCH_CHIP_STM32F429Z is not set
+# CONFIG_ARCH_CHIP_STM32F429I is not set
+# CONFIG_ARCH_CHIP_STM32F429B is not set
+# CONFIG_ARCH_CHIP_STM32F429N is not set
 # CONFIG_STM32_STM32L15XX is not set
 # CONFIG_STM32_ENERGYLITE is not set
 CONFIG_STM32_STM32F10XX=y
@@ -278,10 +292,11 @@ CONFIG_SDIO_PRI=128
 # CONFIG_ARCH_NOINTC is not set
 # CONFIG_ARCH_VECNOTIRQ is not set
 CONFIG_ARCH_DMA=y
-CONFIG_ARCH_IRQPRIO=y
+CONFIG_ARCH_HAVE_IRQPRIO=y
 # CONFIG_CUSTOM_STACK is not set
 # CONFIG_ADDRENV is not set
 CONFIG_ARCH_HAVE_VFORK=y
+CONFIG_ARCH_IRQPRIO=y
 CONFIG_ARCH_STACKDUMP=y
 # CONFIG_ENDIAN_BIG is not set
 # CONFIG_ARCH_HAVE_RAMFUNCS is not set
@@ -293,8 +308,14 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
 #
 CONFIG_BOARD_LOOPSPERMSEC=5483
 # CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
 CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
 CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
 
 #
 # Boot options
@@ -340,6 +361,7 @@ CONFIG_ARCH_HAVE_IRQBUTTONS=y
 #
 # CONFIG_BOARD_INITIALIZE is not set
 CONFIG_MSEC_PER_TICK=10
+# CONFIG_SYSTEM_TIME64 is not set
 CONFIG_RR_INTERVAL=200
 # CONFIG_SCHED_INSTRUMENTATION is not set
 CONFIG_TASK_NAME_SIZE=0
@@ -408,14 +430,17 @@ CONFIG_DEV_NULL=y
 # CONFIG_LOOP is not set
 # CONFIG_RAMDISK is not set
 # CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
 # CONFIG_PWM is not set
-# CONFIG_I2C is not set
 CONFIG_ARCH_HAVE_I2CRESET=y
+# CONFIG_I2C is not set
 # CONFIG_SPI is not set
+# CONFIG_I2S is not set
 # CONFIG_RTC is not set
 # CONFIG_WATCHDOG is not set
 # CONFIG_ANALOG is not set
 # CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
 # CONFIG_BCH is not set
 # CONFIG_INPUT is not set
 # CONFIG_LCD is not set
@@ -427,6 +452,7 @@ CONFIG_MMCSD_NSLOTS=1
 # CONFIG_MMCSD_HAVECARDDETECT is not set
 CONFIG_ARCH_HAVE_SDIO=y
 CONFIG_MMCSD_SDIO=y
+CONFIG_SDIO_PREFLIGHT=y
 # CONFIG_SDIO_MUXBUS is not set
 # CONFIG_SDIO_BLOCKSETUP is not set
 CONFIG_MTD=y
@@ -436,10 +462,14 @@ CONFIG_MTD=y
 #
 # CONFIG_MTD_PARTITION is not set
 # CONFIG_MTD_BYTE_WRITE is not set
+# CONFIG_MTD_CONFIG is not set
+# CONFIG_MTD_CONFIG_RAM_CONSOLIDATE is not set
 
 #
 # MTD Device Drivers
 #
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_MTD_NAND is not set
 # CONFIG_RAMMTD is not set
 # CONFIG_MTD_AT24XX is not set
 # CONFIG_MTD_AT25 is not set
@@ -448,12 +478,14 @@ CONFIG_MTD=y
 # CONFIG_MTD_SMART is not set
 # CONFIG_MTD_RAMTRON is not set
 # CONFIG_MTD_SST25 is not set
+# CONFIG_MTD_SST25XX is not set
 # CONFIG_MTD_SST39FV is not set
 # CONFIG_MTD_W25 is not set
 # CONFIG_PIPES is not set
 # CONFIG_PM is not set
 # CONFIG_POWER is not set
 # CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
 CONFIG_SERIAL=y
 # CONFIG_DEV_LOWCONSOLE is not set
 CONFIG_SERIAL_REMOVABLE=y
@@ -580,6 +612,8 @@ CONFIG_USBMSC_REMOVABLE=y
 #
 # Networking Support
 #
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
 # CONFIG_NET is not set
 
 #
@@ -590,7 +624,10 @@ CONFIG_USBMSC_REMOVABLE=y
 # File system configuration
 #
 CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_FS_READABLE=y
+CONFIG_FS_WRITABLE=y
 # CONFIG_FS_RAMMAP is not set
+# CONFIG_FS_PROCFS is not set
 
 #
 # System Logging
@@ -687,6 +724,7 @@ CONFIG_SCHED_WORKSTACKSIZE=1024
 #
 # CONFIG_EXAMPLES_BUTTONS is not set
 # CONFIG_EXAMPLES_CAN is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
 # CONFIG_EXAMPLES_DHCPD is not set
 # CONFIG_EXAMPLES_ELF is not set
 # CONFIG_EXAMPLES_FTPC is not set
@@ -781,6 +819,11 @@ CONFIG_SCHED_WORKSTACKSIZE=1024
 # NxWidgets/NxWM
 #
 
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
 #
 # System NSH Add-Ons
 #
@@ -824,6 +867,11 @@ CONFIG_SYSTEM_COMPOSITE_BUFSIZE=256
 # FLASH Erase-all Command
 #
 
+#
+# NxPlayer media player library / command Line
+#
+# CONFIG_SYSTEM_NXPLAYER is not set
+
 #
 # RAM test
 #

configs/viewtool-stm32f107/README.txt

@@ -4,16 +4,16 @@ README
   This README discusses issues unique to NuttX configurations for the
   ViewTool STM32F103/F107 V1.2 board.  This board may be fitted with either
 
-  - STM32F107VCT6, or
+    - STM32F107VCT6, or
-  - STM32F103VCT6
+    - STM32F103VCT6
 
-  The board is vary module with connectors for a variety of peripherals.
+  The board is vary modular with connectors for a variety of peripherals.
   Features on the base board include:
 
-  - User and Wake-Up Keys
+    - User and Wake-Up Keys
-  - LEDs
+    - LEDs
 
-  http://www.viewtool.com/ for further information.
+  See http://www.viewtool.com/ for further information.
 
 Contents
 ========
@@ -23,7 +23,7 @@ Contents
   o Serial Console
     - Console Configuration
     - J5 - USART1
-    - PL-2013 USB-to-Serial Intface
+    - PL-2013 USB-to-Serial Interface
     - RS-232 Module
   o Toolchains
     - NOTE about Windows native toolchains
@@ -79,7 +79,7 @@ Serial Console
 
   Console Configuration
   ---------------------
-  The NuttX console is configurated by default on USART1 at 115200 BAUD 8N1
+  The NuttX console is configured by default on USART1 at 115200 BAUD 8N1
   (8-bits, not parity, one stop bit).  These setting can, of course, easily
   be changed by reconfiguring NuttX.
 
@@ -98,8 +98,8 @@ Serial Console
      5   RTS?  9  CTS?  PA12    USART1_RTS
      6   CTS?  11 RTS?  PA11    USART1_CTS
 
-  PL-2013 USB-to-Serial Intface
+  PL-2013 USB-to-Serial Interface
-  -----------------------------
+  -------------------------------
 
     J37 - CON4.  Jumper Settings:
       1 <-> 3 : Connects PA9 to the RXD1 output pin
@@ -197,7 +197,7 @@ Configurations
        CONFIG_HOST_WINDOWS=y                   : Windows operating system
        CONFIG_WINDOWS_CYGWIN=y                 : POSIX environment under windows
 
-  4. All of these configurations use the Code Sourcery for Windows toolchain
+  4. All of these configurations use the CodeSourcery for Windows toolchain
      (unless stated otherwise in the description of the configuration).  That
      toolchain selection can easily be reconfigured using 'make menuconfig'.
      Here are the relevant current settings:
@@ -212,6 +212,15 @@ Configurations
      See also the "NOTE about Windows native toolchains" in the section call
      "GNU Toolchain Options" above.
 
+  4. These configurations all assume that the STM32F107VCT6 is mounted on
+     board.  This is configurable; you can select the STM32F103VCT6 as an
+     alternative.
+
+  5. These configurations all assume that you are loading code using
+     something like the ST-Link v2 JTAG.  None of these configurations are
+     setup to use the DFU bootloader but should be easily reconfigured to
+     use that bootloader is so desired.
+
   Configuration Sub-directories
   -----------------------------
 

configs/viewtool-stm32f107/include/board-stm32f103vct6.h

@@ -0,0 +1,140 @@
+/************************************************************************************
+ * configs/viewtool-stm32f107/include/board-stm32f103vct6.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIGS_VIEWTOOLS_STM32F107_INCLUDE_BOARD_STM32F103VCT6_H
+#define __CONFIGS_VIEWTOOLS_STM32F107_INCLUDE_BOARD_STM32F103VCT6_H 1
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+#include "stm32_rcc.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+
+/* On-board crystal frequency is 8MHz (HSE) */
+
+#define STM32_BOARD_XTAL        8000000ul
+
+/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
+
+#define STM32_CFGR_PLLSRC       RCC_CFGR_PLLSRC
+#define STM32_CFGR_PLLXTPRE     0
+#define STM32_CFGR_PLLMUL       RCC_CFGR_PLLMUL_CLKx9
+#define STM32_PLL_FREQUENCY     (9*STM32_BOARD_XTAL)
+
+/* Use the PLL and set the SYSCLK source to be the PLL */
+
+#define STM32_SYSCLK_SW         RCC_CFGR_SW_PLL
+#define STM32_SYSCLK_SWS        RCC_CFGR_SWS_PLL
+#define STM32_SYSCLK_FREQUENCY  STM32_PLL_FREQUENCY
+
+/* AHB clock (HCLK) is SYSCLK (72MHz) */
+
+#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK
+#define STM32_HCLK_FREQUENCY    STM32_PLL_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY    /* same as above, to satisfy compiler */
+
+/* APB2 clock (PCLK2) is HCLK (72MHz) */
+
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_APB2_CLKIN        (STM32_PCLK2_FREQUENCY)   /* Timers 2-7, 12-14 */
+
+/* APB2 timers 1 and 8 will receive PCLK2. */
+
+#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
+
+/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+
+/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (STM32_PCLK1_FREQUENCY)
+
+/* USB divider -- Divide PLL clock by 1.5 */
+
+#define STM32_CFGR_USBPRE       0
+
+/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
+ * otherwise frequency is 2xAPBx. 
+ * Note: TIM1,8 are on APB2, others on APB1 */
+
+#define STM32_TIM18_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_TIM27_FREQUENCY   STM32_HCLK_FREQUENCY
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_VIEWTOOLS_STM32F107_INCLUDE_BOARD_STM32F103VCT6_H */

configs/viewtool-stm32f107/include/board-stm32f107vct6.h

@@ -0,0 +1,143 @@
+/************************************************************************************
+ * configs/viewtool-stm32f107/include/board-stm32f107vct6.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIGS_VIEWTOOLS_STM32F107_INCLUDE_BOARD_STM32F107VCT6_H
+#define __CONFIGS_VIEWTOOLS_STM32F107_INCLUDE_BOARD_STM32F107VCT6_H 1
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+#include "stm32_rcc.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+
+/* HSI - 8 MHz RC factory-trimmed
+ * LSI - 40 KHz RC (30-60KHz, uncalibrated)
+ * HSE - On-board crystal frequency is 25MHz
+ * LSE - 32.768 kHz
+ */
+
+#define STM32_BOARD_XTAL        25000000ul
+
+#define STM32_HSI_FREQUENCY     8000000ul
+#define STM32_LSI_FREQUENCY     40000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
+/* PLL ouput is 72MHz */
+
+#define STM32_PLL_PREDIV2       RCC_CFGR2_PREDIV2d5   /* 25MHz / 5 => 5MHz */
+#define STM32_PLL_PLL2MUL       RCC_CFGR2_PLL2MULx8   /* 5MHz * 8  => 40MHz */
+#define STM32_PLL_PREDIV1       RCC_CFGR2_PREDIV1d5   /* 40MHz / 5 => 8MHz */
+#define STM32_PLL_PLLMUL        RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9  => 72Mhz */
+#define STM32_PLL_FREQUENCY     (72000000)
+
+/* SYCLLK and HCLK are the PLL frequency */
+
+#define STM32_SYSCLK_FREQUENCY  STM32_PLL_FREQUENCY
+#define STM32_HCLK_FREQUENCY    STM32_PLL_FREQUENCY
+#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
+
+/* APB2 clock (PCLK2) is HCLK (72MHz) */
+
+#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_APB2_CLKIN        (STM32_PCLK2_FREQUENCY)   /* Timers 2-7, 12-14 */
+
+/* APB2 timers 1 and 8 will receive PCLK2. */
+
+#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
+
+/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
+
+#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
+#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+
+/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
+
+#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN   (STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN   (STM32_PCLK1_FREQUENCY)
+
+/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
+ *
+ *  STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz 
+ */
+ 
+#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
+#  define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK      /* Source: PLL3 */
+#  define STM32_PLL_PLL3MUL     RCC_CFGR2_PLL3MULx10  /* MCO 5MHz * 10 = 50MHz */
+#endif
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_VIEWTOOLS_STM32F107_INCLUDE_BOARD_STM32F107VCT6_H */

configs/viewtool-stm32f107/include/board.h

@@ -56,66 +56,12 @@
 
 /* Clocking *************************************************************************/
 
-/* HSI - 8 MHz RC factory-trimmed
+#if defined(CONFIG_ARCH_CHIP_STM32F107VC)
- * LSI - 40 KHz RC (30-60KHz, uncalibrated)
+# include <arch/board/board-stm32f107vct6.h>
- * HSE - On-board crystal frequency is 25MHz
+#elif defined(CONFIG_ARCH_CHIP_STM32F103VCT6)
- * LSE - 32.768 kHz
+# include <arch/board/board-stm32f103vct6.h>
- */
+#else
-
+#  error Unregnized STM32 chip
-#define STM32_BOARD_XTAL        25000000ul
-
-#define STM32_HSI_FREQUENCY     8000000ul
-#define STM32_LSI_FREQUENCY     40000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
-#define STM32_LSE_FREQUENCY     32768
-
-/* PLL ouput is 72MHz */
-
-#define STM32_PLL_PREDIV2       RCC_CFGR2_PREDIV2d5   /* 25MHz / 5 => 5MHz */
-#define STM32_PLL_PLL2MUL       RCC_CFGR2_PLL2MULx8   /* 5MHz * 8  => 40MHz */
-#define STM32_PLL_PREDIV1       RCC_CFGR2_PREDIV1d5   /* 40MHz / 5 => 8MHz */
-#define STM32_PLL_PLLMUL        RCC_CFGR_PLLMUL_CLKx9 /* 8MHz * 9  => 72Mhz */
-#define STM32_PLL_FREQUENCY     (72000000)
-
-/* SYCLLK and HCLK are the PLL frequency */
-
-#define STM32_SYSCLK_FREQUENCY  STM32_PLL_FREQUENCY
-#define STM32_HCLK_FREQUENCY    STM32_PLL_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
-
-/* APB2 clock (PCLK2) is HCLK (72MHz) */
-
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK
-#define STM32_PCLK2_FREQUENCY   STM32_HCLK_FREQUENCY
-#define STM32_APB2_CLKIN        (STM32_PCLK2_FREQUENCY)   /* Timers 2-7, 12-14 */
-
-/* APB2 timers 1 and 8 will receive PCLK2. */
-
-#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
-
-/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
-
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
-
-/* APB1 timers 2-4 will be twice PCLK1 (I presume the remaining will receive PCLK1) */
-
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM6_CLKIN   (STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM7_CLKIN   (STM32_PCLK1_FREQUENCY)
-
-/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
- *
- *  STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz 
- */
- 
-#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
-#  define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK      /* Source: PLL3 */
-#  define STM32_PLL_PLL3MUL     RCC_CFGR2_PLL3MULx10  /* MCO 5MHz * 10 = 50MHz */
 #endif
 
 /* LED definitions ******************************************************************/

configs/viewtool-stm32f107/nsh/defconfig

@@ -46,6 +46,7 @@ CONFIG_INTELHEX_BINARY=y
 CONFIG_ARCH_HAVE_STACKCHECK=y
 CONFIG_ARCH_HAVE_HEAPCHECK=y
 # CONFIG_DEBUG_SYMBOLS is not set
+# CONFIG_DEBUG_NOOPT is not set
 
 #
 # System Type
@@ -66,6 +67,7 @@ CONFIG_ARCH="arm"
 #
 # ARM Options
 #
+# CONFIG_ARCH_CHIP_A1X is not set
 # CONFIG_ARCH_CHIP_C5471 is not set
 # CONFIG_ARCH_CHIP_CALYPSO is not set
 # CONFIG_ARCH_CHIP_DM320 is not set
@@ -277,10 +279,11 @@ CONFIG_STM32_USART=y
 # CONFIG_ARCH_NOINTC is not set
 # CONFIG_ARCH_VECNOTIRQ is not set
 # CONFIG_ARCH_DMA is not set
-CONFIG_ARCH_IRQPRIO=y
+CONFIG_ARCH_HAVE_IRQPRIO=y
 # CONFIG_CUSTOM_STACK is not set
 # CONFIG_ADDRENV is not set
 CONFIG_ARCH_HAVE_VFORK=y
+CONFIG_ARCH_IRQPRIO=y
 CONFIG_ARCH_STACKDUMP=y
 # CONFIG_ENDIAN_BIG is not set
 # CONFIG_ARCH_HAVE_RAMFUNCS is not set
@@ -292,8 +295,14 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
 #
 CONFIG_BOARD_LOOPSPERMSEC=5483
 # CONFIG_ARCH_CALIBRATION is not set
+
+#
+# Interrupt options
+#
 CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
 CONFIG_ARCH_INTERRUPTSTACK=0
+CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y
+# CONFIG_ARCH_HIPRI_INTERRUPT is not set
 
 #
 # Boot options
@@ -338,6 +347,7 @@ CONFIG_NSH_MMCSDMINOR=0
 #
 # CONFIG_BOARD_INITIALIZE is not set
 CONFIG_MSEC_PER_TICK=10
+# CONFIG_SYSTEM_TIME64 is not set
 CONFIG_RR_INTERVAL=200
 # CONFIG_SCHED_INSTRUMENTATION is not set
 CONFIG_TASK_NAME_SIZE=0
@@ -408,14 +418,15 @@ CONFIG_DEV_NULL=y
 # CONFIG_CAN is not set
 # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
 # CONFIG_PWM is not set
-# CONFIG_I2C is not set
 CONFIG_ARCH_HAVE_I2CRESET=y
+# CONFIG_I2C is not set
 # CONFIG_SPI is not set
 # CONFIG_I2S is not set
 # CONFIG_RTC is not set
 # CONFIG_WATCHDOG is not set
 # CONFIG_ANALOG is not set
 # CONFIG_AUDIO_DEVICES is not set
+# CONFIG_VIDEO_DEVICES is not set
 # CONFIG_BCH is not set
 # CONFIG_INPUT is not set
 # CONFIG_LCD is not set
@@ -425,6 +436,7 @@ CONFIG_ARCH_HAVE_I2CRESET=y
 # CONFIG_PM is not set
 # CONFIG_POWER is not set
 # CONFIG_SENSORS is not set
+# CONFIG_SERCOMM_CONSOLE is not set
 CONFIG_SERIAL=y
 # CONFIG_DEV_LOWCONSOLE is not set
 # CONFIG_16550_UART is not set