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z20x: SPI and timer fixes
arch/z80/src/ez80/ez80_spi.c: Add logic checks to eliminate unnecessary SPI reconfiguration. arch/z80/src/ez80/ez80_timerisr.c and arch/z80/src/ez80/ez80f92.h: Fix numerous places where configurations began with CONFIGS_ instead of CONFIG_
This commit is contained in:
Gregory Nutt
committed by
Abdelatif Guettouche
Abdelatif Guettouche
parent
8b1dc2825f
commit
797e45d6bf
@@ -136,6 +136,12 @@ static struct spi_dev_s g_spidev =
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static sem_t g_exclsem = SEM_INITIALIZER(1);
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/* These are used to perform reconfigurations only when necessary. */
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static uint32_t g_spi_frequency;
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static uint32_t g_spi_actual;
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static enum spi_mode_e g_spi_mode = SPIDEV_MODE3;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@@ -195,44 +201,48 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
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static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
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uint32_t frequency)
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{
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uint32_t actual;
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uint32_t brg;
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spiinfo("frequency: %lu\n", (unsigned long)frequency);
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/* We want select divisor to provide the highest frequency (SPIR) that does
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* NOT exceed the requested frequency.:
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*
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* SPIR <= System Clock Frequency / (2 * BRG)
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*
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* So
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*
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* BRG >= System Clock Frequency / (2 * SPIR)
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*/
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brg = ((EZ80_SYS_CLK_FREQ + 1) / 2 + frequency - 1) / frequency;
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/* "When configured as a Master, the 16-bit divisor value must be between
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* 0003h and FFFFh, inclusive. When configured as a Slave, the 16-bit
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* divisor value must be between 0004h and FFFFh, inclusive."
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*/
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if (brg < 3)
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if (frequency != g_spi_frequency)
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{
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brg = 3;
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}
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else if (brg > 0xffff)
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{
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brg = 0xffff;
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uint32_t brg;
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spiinfo("frequency: %lu\n", (unsigned long)frequency);
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/* We want select divisor to provide the highest frequency (SPIR) that
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* does NOT exceed the requested frequency.:
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*
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* SPIR <= System Clock Frequency / (2 * BRG)
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*
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* So
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*
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* BRG >= System Clock Frequency / (2 * SPIR)
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*/
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brg = ((EZ80_SYS_CLK_FREQ + 1) / 2 + frequency - 1) / frequency;
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/* "When configured as a Master, the 16-bit divisor value must be
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* between 0003h and FFFFh, inclusive. When configured as a Slave, the
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* 16-bit divisor value must be between 0004h and FFFFh, inclusive."
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*/
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if (brg < 3)
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{
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brg = 3;
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}
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else if (brg > 0xffff)
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{
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brg = 0xffff;
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}
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outp(EZ80_SPI_BRG_L, brg & 0xff);
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outp(EZ80_SPI_BRG_H, (brg >> 8) & 0xff);
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g_spi_actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg;
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finfo("BRG=%lu Actual=%lu\n",
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(unsigned long)brg, (unsigned long)g_spi_actual);
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}
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outp(EZ80_SPI_BRG_L, brg & 0xff);
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outp(EZ80_SPI_BRG_H, (brg >> 8) & 0xff);
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actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg;
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finfo("BRG=%lu Actual=%lu\n", (unsigned long)brg, (unsigned long)actual);
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return actual;
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return g_spi_actual;
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}
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/****************************************************************************
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@@ -252,41 +262,46 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
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static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
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{
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uint8_t modebits;
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uint8_t regval;
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spiinfo("mode: %d\n", (int)mode);
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/* Select the CTL register bits based on the selected mode */
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switch (mode)
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if (mode != g_spi_mode)
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{
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case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
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modebits = 0;
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break;
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uint8_t modebits;
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uint8_t regval;
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case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
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modebits = SPI_CTL_CPHA;
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break;
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spiinfo("mode: %d\n", (int)mode);
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case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
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modebits = SPI_CTL_CPOL;
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break;
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/* Select the CTL register bits based on the selected mode */
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case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
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modebits = (SPI_CTL_CPOL | SPI_CTL_CPHA);
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break;
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switch (mode)
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{
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case SPIDEV_MODE0: /* CPOL=0 CHPHA=0 */
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modebits = 0;
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break;
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default:
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return;
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case SPIDEV_MODE1: /* CPOL=0 CHPHA=1 */
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modebits = SPI_CTL_CPHA;
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break;
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case SPIDEV_MODE2: /* CPOL=1 CHPHA=0 */
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modebits = SPI_CTL_CPOL;
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break;
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case SPIDEV_MODE3: /* CPOL=1 CHPHA=1 */
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modebits = (SPI_CTL_CPOL | SPI_CTL_CPHA);
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break;
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default:
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return;
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}
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/* Then set those bits in the CTL register */
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regval = inp(EZ80_SPI_CTL);
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regval &= ~(SPI_CTL_CPOL | SPI_CTL_CPHA);
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regval |= modebits;
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outp(EZ80_SPI_CTL, regval);
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g_spi_mode = mode;
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}
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/* Then set those bits in the CTL register */
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regval = inp(EZ80_SPI_CTL);
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regval &= ~(SPI_CTL_CPOL | SPI_CTL_CPHA);
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regval |= modebits;
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outp(EZ80_SPI_CTL, regval);
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}
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/****************************************************************************
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@@ -394,8 +409,6 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
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uint8_t response;
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int ret;
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spiinfo("ch: %04x\n", wd);
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ret = spi_transfer((uint8_t)wd, &response);
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if (ret < 0)
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{
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@@ -403,6 +416,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
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return (uint16_t)0xff;
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}
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spiinfo("ch: %04x response: %02x\n", wd, response);
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return (uint16_t)response;
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}
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@@ -625,9 +639,12 @@ FAR struct spi_dev_s *ez80_spibus_initialize(int port)
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# error "Check GPIO initialization for this chip"
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#endif
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/* Set the initial clock frequency for identification mode < 400kHz */
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/* Set the initial clock frequency for identification mode < 400kHz
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* and Mode 0.
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*/
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spi_setfrequency(NULL, 400000);
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spi_setmode(NULL, SPIDEV_MODE0);
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/* Enable the SPI.
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* NOTE 1: Interrupts are not used in this driver version.
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@@ -51,7 +51,7 @@ static int ez80_timerisr(int irq, chipreg_t *regs, void *arg)
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{
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/* Read the appropriate timer0 register to clear the interrupt */
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#ifdef CONFIGS_ARCH_CHIP_EZ80F91
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#ifdef CONFIG_ARCH_CHIP_EZ80F91
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inp(EZ80_TMR0_IIR);
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#else
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/* _EZ80190, _EZ80L92, _EZ80F92, _EZ80F93: PRT_IRQ, is set to 1 when the
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@@ -134,37 +134,41 @@ void up_timer_initialize(void)
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outp(EZ80_TMR0_RRH, (uint8_t)(reload >> 8));
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outp(EZ80_TMR0_RRL, (uint8_t)(reload));
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#if defined(CONFIGS_ARCH_CHIP_EZ80F91)
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#if defined(CONFIG_ARCH_CHIP_EZ80F91)
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/* Clear any pending timer interrupts by reading the IIR register */
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inp(EZ80_TMR0_IIR);
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#elif defined(CONFIGS_ARCH_CHIP_EZ80L92) || defined(CONFIGS_ARCH_CHIP_EZ80F92) || \
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defined(CONFIGS_ARCH_CHIP_EZ80F93)
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#elif defined(CONFIG_ARCH_CHIP_EZ80L92) || defined(CONFIG_ARCH_CHIP_EZ80F92) || \
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defined(CONFIG_ARCH_CHIP_EZ80F93)
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/* Clear any pending timer interrupts by reading the CTL register */
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inp(EZ80_TMR0_CTL);
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#endif
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/* Configure and enable the timer */
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#if defined(_EZ80190)
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outp(EZ80_TMR0_CTL, 0x5f);
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#elif defined(CONFIGS_ARCH_CHIP_EZ80F91)
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#elif defined(CONFIG_ARCH_CHIP_EZ80F91)
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/* EZ80_TMRCTL_TIMEN: Bit 0: The programmable reload timer is enabled
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* EZ80_TMRCTL_RLD: Bit 1: Force reload
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* EZ80_TMRCTL_TIMCONT: Bit 2: The timer operates in CONTINUOUS mode.
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* EZ80_TMRCLKDIV_16: Bits 3-4: System clock divider = 16
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*/
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outp(EZ80_TMR0_CTL, (EZ80_TMRCLKDIV_16 | EZ80_TMRCTL_TIMCONT |
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EZ80_TMRCTL_RLD | EZ80_TMRCTL_TIMEN));
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outp(EZ80_TMR0_CTL, (EZ80_TMRCTL_TIMEN | EZ80_TMRCTL_RLD |
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EZ80_TMRCTL_TIMCONT | EZ80_TMRCLKDIV_16));
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/* Enable timer end-of-count interrupts */
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outp(EZ80_TMR0_IER, EZ80_TMRIER_EOCEN);
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#elif defined(CONFIGS_ARCH_CHIP_EZ80L92) || defined(CONFIGS_ARCH_CHIP_EZ80F92) || \
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defined(CONFIGS_ARCH_CHIP_EZ80F93)
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#elif defined(CONFIG_ARCH_CHIP_EZ80L92) || defined(CONFIG_ARCH_CHIP_EZ80F92) || \
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defined(CONFIG_ARCH_CHIP_EZ80F93)
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/* EZ80_TMRCTL_TIMEN: Bit 0: Programmable reload timer enabled.
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* EZ80_TMRCTL_RSTEN: Bit 1: Reload and start function enabled.
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* EZ80_TMRCLKDIV_4: Bits 2-3: Timer input clock divided by 4 (5Mhz)
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@@ -172,8 +176,9 @@ void up_timer_initialize(void)
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* EZ80_TMRCTL_EN: Bit 6: Enable timer interrupt requests
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*/
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outp(EZ80_TMR0_CTL, (EZ80_TMRCTL_TIMEN | EZ80_TMRCTL_RSTEN |
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outp(EZ80_TMR0_CTL, (EZ80_TMRCTL_TIMEN | : |
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EZ80_TMRCLKDIV_4 | EZ80_TMRCTL_TIMCONT |
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EZ80_TMRCTL_EN);
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EZ80_TMRCTL_EN));
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#endif
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}
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@@ -39,10 +39,10 @@
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#define EZ80_OFFCHIPCS1 0xc00000 /* CS1: Off chip use (usually SRAM) */
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#define EZ80_ONCHIPSRAM 0xffe000 /* On-chip SRAM (4-8Kb) on reset */
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#if defined(CONFIGS_ARCH_CHIP_EZ80L92)
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#if defined(CONFIG_ARCH_CHIP_EZ80L92)
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# define EZ80_FLASH_SIZE 0x020000 /* 128Kb on-chip flash */
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# define EZ80_SRAM_SIZE 0x002000 /* 8Kb on-chip sram */
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#elif defined(CONFIGS_ARCH_CHIP_EZ80L93)
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#elif defined(CONFIG_ARCH_CHIP_EZ80L93)
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# define EZ80_FLASH_SIZE 0x010000 /* 64Kb on-chip flash */
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# define EZ80_SRAM_SIZE 0x001000 /* 4Kb on-chip sram */
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#endif
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