diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h
index a10b3573970..3ea2074a7ca 100644
--- a/arch/arm/src/armv7-a/mmu.h
+++ b/arch/arm/src/armv7-a/mmu.h
@@ -1426,6 +1426,28 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
 #  define mmu_l1_clrentry(v) mmu_l1_restore(v,0)
 #endif
 
+/****************************************************************************
+ * Name: mmu_l2_setentry
+ *
+ * Description:
+ *   Set one small (4096B) entry in a level2 translation table.
+ *
+ * Input Parameters:
+ *   l2vaddr - the virtual address of the beginning of the L2 translation
+ *     table.
+ *   paddr - The physical address to be mapped.  Must be aligned to a 4KB
+ *     address boundary
+ *   vaddr - The virtual address to be mapped.  Must be aligned to a 4KB
+ *     address boundary
+ *   mmuflags - The MMU flags to use in the mapping.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_ROMPGTABLE
+void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
+                     uint32_t mmuflags);
+#endif
+
 /************************************************************************************
  * Name: mmu_l1_map_region
  *
diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h
index 7b675e117b6..bd352ce7c79 100644
--- a/arch/arm/src/imx6/chip/imx_memorymap.h
+++ b/arch/arm/src/imx6/chip/imx_memorymap.h
@@ -917,7 +917,8 @@
  *    the address space.
  */
 
-#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */
+#define INTERCPU_L2_PAGES 1          /* Pages allowed for inter-processor communications */
+#define L2_BASE           0x80000000 /* Beginning of L2 page table */
 
 #ifndef CONFIG_ARCH_LOWVECTORS
   /* Memory map
@@ -1007,9 +1008,15 @@
 #  define INTERCPU_L2_OFFSET      (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE)
 #  define INTERCPU_L2_SIZE        (0x00000400)
 
-/* Inter-processor communications L2 page table virtual base addresse */
+  /* on-cached inter-processor communication page table base addresses */
 
+#  define INTERCPU_L2_PBASE       (PGTABLE_BASE_PADDR + INTERCPU_L2_OFFSET)
 #  define INTERCPU_L2_VBASE       (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET)
+
+  /* on-cached inter-processor communication end addresses */
+
+#  define INTERCPU_L2_END_PADDR   (INTERCPU_L2_PBASE + INTERCPU_L2_SIZE)
+#  define INTERCPU_L2_END_VADDR   (INTERCPU_L2_VBASE + INTERCPU_L2_SIZE)
 #endif
 
 /* Base address of the interrupt vector table.
diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c
index 4455d3394ac..b635a27aec5 100644
--- a/arch/arm/src/imx6/imx_boot.c
+++ b/arch/arm/src/imx6/imx_boot.c
@@ -233,7 +233,7 @@ static void imx_vectormapping(void)
  *
  ****************************************************************************/
 
-#ifndef CONFIG_SMP
+#ifdef CONFIG_SMP
 static void imx_intercpu_mapping(void)
 {
   uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK;
@@ -256,7 +256,7 @@ static void imx_intercpu_mapping(void)
 
   /* Now set the level 1 descriptor to refer to the level 2 page table. */
 
-  mmu_l1_setentry(INTERCPU_PBASE & PMD_PTE_PADDR_MASK,
+  mmu_l1_setentry(INTERCPU_PADDR & PMD_PTE_PADDR_MASK,
                   INTERCPU_VADDR & PMD_PTE_PADDR_MASK,
                   MMU_L1_INTERCPUFLAGS);
 }
diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld
index de4b7a33ddf..b496eb23c42 100644
--- a/configs/sabre-6quad/scripts/dramboot.ld
+++ b/configs/sabre-6quad/scripts/dramboot.ld
@@ -46,7 +46,7 @@ MEMORY
 {
 	oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K
 	ddr3 (W!RX)   : ORIGIN = 0x10800000, LENGTH = 1024M - 8M
-	nocache (WR)  : ORIGIN = 0x80600000, LENGTH = 4K
+	nocache (WR)  : ORIGIN = 0xe0000000, LENGTH = 4K
 }
 
 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
@@ -128,7 +128,7 @@ SECTIONS
 		_snocache = ABSOLUTE(.);
 		*(.nocache)
 		_enocache = ABSOLUTE(.);
-	} > nocahce
+	} > nocache
 
 	/* Stabs debugging sections. */
 	.stab 0 : { *(.stab) }