Fix error in last ARMv7-M up_disable_irq checkin

arch/arm/src/kinetis/kinetis_irq.c

@@ -450,29 +450,23 @@ void up_disable_irq(int irq)
 
   if (kinetis_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
     {
-      /* Modify the appropriate bit in the register to disable the interrupt */
+      /* Modify the appropriate bit in the register to disable the interrupt.
-
+       * For normal interrupts, we need to set the bit in the associated
-      regval  = getreg32(regaddr);
+       * Interrupt Clear Enable register.  For other exceptions, we need to
-
+       * clear the bit in the System Handler Control and State Register.
-      /* This is awkward... For normal interrupts, we need to set the bit
-       * in the associated Interrupt Clear Enable register.  For other
-       * exceptions, we need to clear the bit in the System Handler Control
-       * and State Register.
        */
 
       if (irq >= KINETIS_IRQ_EXTINT)
         {
-          regval |= bit;
+          putreg32(bit, regaddr);
         }
       else
         {
+          regval  = getreg32(regaddr);
           regval &= ~bit;
-        }
-
-      /* Save the appropriately modified register */
-
           putreg32(regval, regaddr);
         }
+    }
 
   kinetis_dumpnvic("disable", irq);
 }
@@ -493,12 +487,23 @@ void up_enable_irq(int irq)
 
   if (kinetis_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
     {
-      /* Set the appropriate bit in the register to enable the interrupt */
+      /* Modify the appropriate bit in the register to enable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Set Enable register.  For other exceptions, we need to
+       * set the bit in the System Handler Control and State Register.
+       */
 
+      if (irq >= KINETIS_IRQ_EXTINT)
+        {
+          putreg32(bit, regaddr);
+        }
+      else
+        {
           regval  = getreg32(regaddr);
           regval |= bit;
           putreg32(regval, regaddr);
         }
+    }
 
   kinetis_dumpnvic("enable", irq);
 }

arch/arm/src/lm/lm_irq.c

@@ -404,29 +404,23 @@ void up_disable_irq(int irq)
 
   if (lm_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
     {
-      /* Modify the appropriate bit in the register to disable the interrupt */
+      /* Modify the appropriate bit in the register to disable the interrupt.
-
+       * For normal interrupts, we need to set the bit in the associated
-      regval  = getreg32(regaddr);
+       * Interrupt Clear Enable register.  For other exceptions, we need to
-
+       * clear the bit in the System Handler Control and State Register.
-      /* This is awkward... For normal interrupts, we need to set the bit
-       * in the associated Interrupt Clear Enable register.  For other
-       * exceptions, we need to clear the bit in the System Handler Control
-       * and State Register.
        */
 
       if (irq >= LM_IRQ_INTERRUPTS)
         {
-          regval |= bit;
+          putreg32(bit, regaddr);
         }
       else
         {
+          regval  = getreg32(regaddr);
           regval &= ~bit;
-        }
-
-      /* Save the appropriately modified register */
-
           putreg32(regval, regaddr);
         }
+    }
 
   lm_dumpnvic("disable", irq);
 }
@@ -447,12 +441,23 @@ void up_enable_irq(int irq)
 
   if (lm_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
     {
-      /* Set the appropriate bit in the register to enable the interrupt */
+      /* Modify the appropriate bit in the register to enable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Set Enable register.  For other exceptions, we need to
+       * set the bit in the System Handler Control and State Register.
+       */
 
+      if (irq >= LM_IRQ_INTERRUPTS)
+        {
+          putreg32(bit, regaddr);
+        }
+      else
+        {
           regval  = getreg32(regaddr);
           regval |= bit;
           putreg32(regval, regaddr);
         }
+    }
 
   lm_dumpnvic("enable", irq);
 }

arch/arm/src/lpc17xx/lpc17_irq.c

@@ -395,31 +395,25 @@ void up_disable_irq(int irq)
   uint32_t regval;
   uint32_t bit;
 
-  if (lpc17_irqinfo(irq, &regaddr, &bit) == 0)
+  if (lpc17_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
     {
-      /* Modify the appropriate bit in the register to disable the interrupt */
+      /* Modify the appropriate bit in the register to disable the interrupt.
-
+       * For normal interrupts, we need to set the bit in the associated
-      regval  = getreg32(regaddr);
+       * Interrupt Clear Enable register.  For other exceptions, we need to
-
+       * clear the bit in the System Handler Control and State Register.
-      /* This is awkward... For normal interrupts, we need to set the bit
-       * in the associated Interrupt Clear Enable register.  For other
-       * exceptions, we need to clear the bit in the System Handler Control
-       * and State Register.
        */
 
       if (irq >= LPC17_IRQ_EXTINT)
         {
-          regval |= bit;
+          putreg32(bit, regaddr);
         }
       else
         {
+          regval  = getreg32(regaddr);
           regval &= ~bit;
-        }
-
-      /* Save the appropriately modified register */
-
           putreg32(regval, regaddr);
         }
+    }
 #ifdef CONFIG_GPIO_IRQ
   else if (irq >= LPC17_VALID_FIRST0L)
     {
@@ -448,12 +442,23 @@ void up_enable_irq(int irq)
 
   if (lpc17_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
     {
-      /* Set the appropriate bit in the register to enable the interrupt */
+      /* Modify the appropriate bit in the register to enable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Set Enable register.  For other exceptions, we need to
+       * set the bit in the System Handler Control and State Register.
+       */
 
+      if (irq >= LPC17_IRQ_EXTINT)
+        {
+          putreg32(bit, regaddr);
+        }
+      else
+        {
           regval  = getreg32(regaddr);
           regval |= bit;
           putreg32(regval, regaddr);
         }
+    }
 #ifdef CONFIG_GPIO_IRQ
   else if (irq >= LPC17_VALID_FIRST0L)
     {

arch/arm/src/lpc43xx/lpc43_irq.c

@@ -435,29 +435,23 @@ void up_disable_irq(int irq)
 
   if (lpc43_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
     {
-      /* Modify the appropriate bit in the register to disable the interrupt */
+      /* Modify the appropriate bit in the register to disable the interrupt.
-
+       * For normal interrupts, we need to set the bit in the associated
-      regval  = getreg32(regaddr);
+       * Interrupt Clear Enable register.  For other exceptions, we need to
-
+       * clear the bit in the System Handler Control and State Register.
-      /* This is awkward... For normal interrupts, we need to set the bit
-       * in the associated Interrupt Clear Enable register.  For other
-       * exceptions, we need to clear the bit in the System Handler Control
-       * and State Register.
        */
 
       if (irq >= LPC43_IRQ_EXTINT)
         {
-          regval |= bit;
+          putreg32(bit, regaddr);
         }
       else
         {
+          regval  = getreg32(regaddr);
           regval &= ~bit;
-        }
-
-      /* Save the appropriately modified register */
-
           putreg32(regval, regaddr);
         }
+    }
 #ifdef CONFIG_GPIO_IRQ
   else if (irq >= LPC43_VALID_FIRST0L)
     {
@@ -486,12 +480,23 @@ void up_enable_irq(int irq)
 
   if (lpc43_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
     {
-      /* Set the appropriate bit in the register to enable the interrupt */
+      /* Modify the appropriate bit in the register to enable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Set Enable register.  For other exceptions, we need to
+       * set the bit in the System Handler Control and State Register.
+       */
 
+      if (irq >= LPC43_IRQ_EXTINT)
+        {
+          putreg32(bit, regaddr);
+        }
+      else
+        {
           regval  = getreg32(regaddr);
           regval |= bit;
           putreg32(regval, regaddr);
         }
+    }
 #ifdef CONFIG_GPIO_IRQ
   else if (irq >= LPC43_VALID_FIRST0L)
     {

arch/arm/src/sam34/sam_irq.c

@@ -464,29 +464,23 @@ void up_disable_irq(int irq)
 
   if (sam_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
     {
-      /* Modify the appropriate bit in the register to disable the interrupt */
+      /* Modify the appropriate bit in the register to disable the interrupt.
-
+       * For normal interrupts, we need to set the bit in the associated
-      regval  = getreg32(regaddr);
+       * Interrupt Clear Enable register.  For other exceptions, we need to
-
+       * clear the bit in the System Handler Control and State Register.
-      /* This is awkward... For normal interrupts, we need to set the bit
-       * in the associated Interrupt Clear Enable register.  For other
-       * exceptions, we need to clear the bit in the System Handler Control
-       * and State Register.
        */
 
       if (irq >= SAM_IRQ_EXTINT)
         {
-          regval |= bit;
+          putreg32(bit, regaddr);
         }
       else
         {
+          regval  = getreg32(regaddr);
           regval &= ~bit;
-        }
-
-      /* Save the appropriately modified register */
-
           putreg32(regval, regaddr);
         }
+    }
 #ifdef CONFIG_GPIO_IRQ
   else
     {
@@ -514,12 +508,23 @@ void up_enable_irq(int irq)
 
   if (sam_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
     {
-      /* Set the appropriate bit in the register to enable the interrupt */
+      /* Modify the appropriate bit in the register to enable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Set Enable register.  For other exceptions, we need to
+       * set the bit in the System Handler Control and State Register.
+       */
 
+      if (irq >= SAM_IRQ_EXTINT)
+        {
+          putreg32(bit, regaddr);
+        }
+      else
+        {
           regval  = getreg32(regaddr);
           regval |= bit;
           putreg32(regval, regaddr);
         }
+    }
 #ifdef CONFIG_GPIO_IRQ
   else
     {

arch/arm/src/stm32/stm32_irq.c

@@ -429,29 +429,23 @@ void up_disable_irq(int irq)
 
   if (stm32_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
     {
-      /* Modify the appropriate bit in the register to disable the interrupt */
+      /* Modify the appropriate bit in the register to disable the interrupt.
-
+       * For normal interrupts, we need to set the bit in the associated
-      regval  = getreg32(regaddr);
+       * Interrupt Clear Enable register.  For other exceptions, we need to
-
+       * clear the bit in the System Handler Control and State Register.
-      /* This is awkward... For normal interrupts, we need to set the bit
-       * in the associated Interrupt Clear Enable register.  For other
-       * exceptions, we need to clear the bit in the System Handler Control
-       * and State Register.
        */
 
       if (irq >= STM32_IRQ_INTERRUPTS)
         {
-          regval |= bit;
+          putreg32(bit, regaddr);
         }
       else
         {
+          regval  = getreg32(regaddr);
           regval &= ~bit;
-        }
-
-      /* Save the appropriately modified register */
-
           putreg32(regval, regaddr);
         }
+    }
 
   // stm32_dumpnvic("disable", irq);
 }
@@ -472,12 +466,23 @@ void up_enable_irq(int irq)
 
   if (stm32_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
     {
-      /* Set the appropriate bit in the register to enable the interrupt */
+      /* Modify the appropriate bit in the register to enable the interrupt.
+       * For normal interrupts, we need to set the bit in the associated
+       * Interrupt Set Enable register.  For other exceptions, we need to
+       * set the bit in the System Handler Control and State Register.
+       */
 
+      if (irq >= STM32_IRQ_INTERRUPTS)
+        {
+          putreg32(bit, regaddr);
+        }
+      else
+        {
           regval  = getreg32(regaddr);
           regval |= bit;
           putreg32(regval, regaddr);
         }
+    }
 
   // stm32_dumpnvic("enable", irq);
 }