diff --git a/arch/arm/include/sam34/chip.h b/arch/arm/include/sam34/chip.h index 3a4364c5211..f1881d1f004 100644 --- a/arch/arm/include/sam34/chip.h +++ b/arch/arm/include/sam34/chip.h @@ -95,7 +95,7 @@ * HSMCI 8 bit 4 bit 8 bit 4 bit 4 bit 4 bit */ -#if defined(CONFIG_ARCH_CHIP_AT91SAM3X8E) +#elif defined(CONFIG_ARCH_CHIP_AT91SAM3X8E) /* Internal memory */ diff --git a/arch/arm/include/sam34/sam3u_irq.h b/arch/arm/include/sam34/sam3u_irq.h index f71d66883f5..6a8c5380aa0 100644 --- a/arch/arm/include/sam34/sam3u_irq.h +++ b/arch/arm/include/sam34/sam3u_irq.h @@ -70,7 +70,7 @@ #define SAM_PID_HSMCI (17) /* High Speed Multimedia Card Interface */ #define SAM_PID_TWI0 (18) /* Two-Wire Interface 0 */ #define SAM_PID_TWI1 (19) /* Two-Wire Interface 1 */ -#define SAM_PID_SPI (20) /* Serial Peripheral Interface */ +#define SAM_PID_SPI0 (20) /* Serial Peripheral Interface */ #define SAM_PID_SSC (21) /* Synchronous Serial Controller */ #define SAM_PID_TC0 (22) /* Timer Counter 0 */ #define SAM_PID_TC1 (23) /* Timer Counter 1 */ @@ -104,7 +104,7 @@ #define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* High Speed Multimedia Card Interface */ #define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* Two-Wire Interface 0 */ #define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* Two-Wire Interface 1 */ -#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+SAM_PID_SPI) /* Serial Peripheral Interface */ +#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* Serial Peripheral Interface */ #define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* Synchronous Serial Controller */ #define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* Timer Counter 0 */ #define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* Timer Counter 1 */ diff --git a/arch/arm/include/sam34/sam4l_irq.h b/arch/arm/include/sam34/sam4l_irq.h index 713ff4f6157..c33e8e162df 100644 --- a/arch/arm/include/sam34/sam4l_irq.h +++ b/arch/arm/include/sam34/sam4l_irq.h @@ -57,7 +57,7 @@ #define SAM_PID_USART1_RHR (1) /* DIR=RX REGISTER: USART1 RHR */ #define SAM_PID_USART2_RHR (2) /* DIR=RX REGISTER: USART2 RHR */ #define SAM_PID_USART3_RHR (3) /* DIR=RX REGISTER: USART3 RHR */ -#define SAM_PID_SPI_RDR (4) /* DIR=RX REGISTER: SPI RDR */ +#define SAM_PID_SPI0_RDR (4) /* DIR=RX REGISTER: SPI RDR */ #define SAM_PID_TWIM0_RHR (5) /* DIR=RX REGISTER: TWIM0 RHR */ #define SAM_PID_TWIM1_RHR (6) /* DIR=RX REGISTER: TWIM1 RHR */ #define SAM_PID_TWIM2_RHR (7) /* DIR=RX REGISTER: TWIM2 RHR */ @@ -75,7 +75,7 @@ #define SAM_PID_USART1_THR (19) /* DIR=TX REGISTER: USART1 THR */ #define SAM_PID_USART2_THR (20) /* DIR=TX REGISTER: USART2 THR */ #define SAM_PID_USART3_THR (21) /* DIR=TX REGISTER: USART3 THR */ -#define SAM_PID_SPI_TDR (22) /* DIR=TX REGISTER: SPI TDR */ +#define SAM_PID_SPI0_TDR (22) /* DIR=TX REGISTER: SPI TDR */ #define SAM_PID_TWIM0_THR (23) /* DIR=TX REGISTER: TWIM0 THR */ #define SAM_PID_TWIM1_THR (24) /* DIR=TX REGISTER: TWIM1 THR */ #define SAM_PID_TWIM2_THR (25) /* DIR=TX REGISTER: TWIM2 THR */ @@ -149,7 +149,7 @@ #define SAM_IRQ_EIC7 (SAM_IRQ_EXTINT+51) /* 51 External Interrupt Controller 7 */ #define SAM_IRQ_EIC8 (SAM_IRQ_EXTINT+52) /* 52 External Interrupt Controller 8 */ #define SAM_IRQ_IISC (SAM_IRQ_EXTINT+53) /* 53 Inter-IC Sound (I2S) Controller */ -#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+54) /* 54 Serial Peripheral Interface */ +#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+54) /* 54 Serial Peripheral Interface */ #define SAM_IRQ_TC00 (SAM_IRQ_EXTINT+55) /* 55 Timer/Counter 0 */ #define SAM_IRQ_TC01 (SAM_IRQ_EXTINT+56) /* 56 Timer/Counter 1 */ #define SAM_IRQ_TC02 (SAM_IRQ_EXTINT+57) /* 57 Timer/Counter 2 */ diff --git a/arch/arm/include/sam34/sam4s_irq.h b/arch/arm/include/sam34/sam4s_irq.h index 8126075d9e1..fdc66808a2b 100644 --- a/arch/arm/include/sam34/sam4s_irq.h +++ b/arch/arm/include/sam34/sam4s_irq.h @@ -71,7 +71,7 @@ #define SAM_PID_HSMCI (18) /* High Speed Multimedia Card Interface */ #define SAM_PID_TWI0 (19) /* Two-Wire Interface 0 */ #define SAM_PID_TWI1 (20) /* Two-Wire Interface 1 */ -#define SAM_PID_SPI (21) /* Serial Peripheral Interface */ +#define SAM_PID_SPI0 (21) /* Serial Peripheral Interface */ #define SAM_PID_SSC (22) /* Synchronous Serial Controller */ #define SAM_PID_TC0 (23) /* Timer Counter 0 */ #define SAM_PID_TC1 (24) /* Timer Counter 1 */ @@ -110,7 +110,7 @@ #define SAM_IRQ_HSMCI (SAM_IRQ_EXTINT+SAM_PID_HSMCI) /* PID 18: High Speed Multimedia Card Interface */ #define SAM_IRQ_TWI0 (SAM_IRQ_EXTINT+SAM_PID_TWI0) /* PID 19: Two-Wire Interface 0 */ #define SAM_IRQ_TWI1 (SAM_IRQ_EXTINT+SAM_PID_TWI1) /* PID 20: Two-Wire Interface 1 */ -#define SAM_IRQ_SPI (SAM_IRQ_EXTINT+SAM_PID_SPI) /* PIC 21: Serial Peripheral Interface */ +#define SAM_IRQ_SPI0 (SAM_IRQ_EXTINT+SAM_PID_SPI0) /* PIC 21: Serial Peripheral Interface */ #define SAM_IRQ_SSC (SAM_IRQ_EXTINT+SAM_PID_SSC) /* PID 22: Synchronous Serial Controller */ #define SAM_IRQ_TC0 (SAM_IRQ_EXTINT+SAM_PID_TC0) /* PID 23: Timer Counter 0 */ #define SAM_IRQ_TC1 (SAM_IRQ_EXTINT+SAM_PID_TC1) /* PID 24: Timer Counter 1 */ diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index e295e01c032..28e49ab9647 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -222,14 +222,19 @@ config SAM34_IISC default n depends on ARCH_CHIP_SAM4L -config SAM34_SPI - bool "Serial Peripheral Interface (SPI)" +config SAM34_SPI0 + bool "Serial Peripheral Interface 0 (SPI0)" default n +config SAM34_SPI1 + bool "Serial Peripheral Interface 1 (SPI1)" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + config SAM34_SSC bool "Synchronous Serial Controller (SSC)" default n - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S config SAM34_TC0 bool "Timer/Counter 0 (TC0)" @@ -242,27 +247,42 @@ config SAM34_TC1 config SAM34_TC2 bool "Timer/Counter 2 (TC2)" default n - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S config SAM34_TC3 bool "Timer/Counter 3 (TC3)" default n - depends on ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S config SAM34_TC4 bool "Timer/Counter 4 (TC4)" default n - depends on ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S config SAM34_TC5 bool "Timer/Counter 5 (TC5)" default n - depends on ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S + +config SAM34_TC6 + bool "Timer/Counter 6 (TC6)" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + +config SAM34_TC7 + bool "Timer/Counter 7 (TC6)" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + +config SAM34_TC8 + bool "Timer/Counter 6 (TC8)" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A config SAM34_PWM bool "Pulse Width Modulation (PWM) Controller" default n - depends on ARCH_CHIP_SAM3U|| ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S config SAM34_TWIM0 bool "Two-wire Master Interface 0 (TWIM0)" @@ -293,7 +313,7 @@ config SAM34_TWIM3 config SAM34_UART0 bool "UART 0" default y - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S select ARCH_HAVE_UART0 config SAM34_UART1 @@ -322,13 +342,13 @@ config SAM34_USART2 bool "USART 2" default n select ARCH_HAVE_USART2 - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L config SAM34_USART3 bool "USART 3" default n select ARCH_HAVE_USART3 - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L config SAM34_ADC12B bool "12-bit ADC Controller" @@ -342,7 +362,7 @@ config SAM34_ADC config SAM34_DACC bool "Digital To Analog Converter (DAC)" default n - depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S config SAM34_ACC bool "Analog Comparator (AC)" @@ -362,7 +382,22 @@ config SAM34_ABDACB config SAM34_TRNG bool "True Random Number Generator (TRNG)" default n - depends on ARCH_CHIP_SAM4L + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L + +config SAM34_EMAC + bool "Ethernet MAC (EMAC)" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + +config SAM34_CAN0 + bool "CAN0" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + +config SAM34_CAN1 + bool "CAN1" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A config SAM34_PARC bool "Parallel Capture (PARC)" @@ -387,7 +422,12 @@ config SAM34_HRAMC1 config SAM34_SMC bool "Static Memory Controller (SMC)" default n - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S + +config SAM34_SDRAMC + bool "SDRAM Controller (SDRAMC)" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A config SAM34_NAND bool "NAND support" @@ -408,7 +448,7 @@ config SAM34_PDCA config SAM34_DMA bool "DMA controller" default n - depends on ARCH_CHIP_SAM3U + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A select ARCH_DMA config SAM34_CRCCU @@ -421,6 +461,11 @@ config SAM34_UDPHS default n depends on ARCH_CHIP_SAM3U +config SAM34_UOTGHS + bool "USB OTG High Speed" + default n + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X + config SAM34_UDP bool "USB Device Full Speed" default n @@ -454,12 +499,12 @@ config SAM34_AST config SAM34_RTC bool "Real Time Clock (RTC)" default n - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S config SAM34_RTT bool "Real Time Timer (RTT)" default n - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S config SAM34_WDT bool "Watchdog Timer (WDT)" @@ -473,7 +518,7 @@ config SAM34_EIC config SAM34_HSMCI bool "High Speed Multimedia Card Interface (HSMCI)" default n - depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S + depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S endmenu @@ -615,6 +660,21 @@ config GPIOC_IRQ bool "GPIOC interrupts" default n +config GPIOD_IRQ + bool "GPIOD interrupts" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + +config GPIOE_IRQ + bool "GPIOE interrupts" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + +config GPIOF_IRQ + bool "GPIOF interrupts" + default n + depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A + endif if SAM34_WDT diff --git a/arch/arm/src/sam34/Make.defs b/arch/arm/src/sam34/Make.defs index cee2763baf8..1db69314568 100644 --- a/arch/arm/src/sam34/Make.defs +++ b/arch/arm/src/sam34/Make.defs @@ -104,6 +104,6 @@ ifeq ($(CONFIG_SAM34_HSMCI),y) CHIP_CSRCS += sam_hsmci.c endif -ifeq ($(CONFIG_SAM34_SPI),y) +ifeq ($(CONFIG_SAM34_SPI0),y) CHIP_CSRCS += sam_spi.c endif diff --git a/arch/arm/src/sam34/chip/sam3u_memorymap.h b/arch/arm/src/sam34/chip/sam3u_memorymap.h index e1b9822b243..67a53303401 100644 --- a/arch/arm/src/sam34/chip/sam3u_memorymap.h +++ b/arch/arm/src/sam34/chip/sam3u_memorymap.h @@ -64,7 +64,7 @@ #define SAM_PERIPHERALS_BASE 0x40000000 /* 0x40000000-0x5fffffff: Peripherals */ # define SAM_MCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ # define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ -# define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ +# define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ /* 0x4000c000-0x4007ffff: Reserved */ # define SAM_TC_BASE 0x40080000 /* 0x40080000-0x40083fff: Timer Counters */ # define SAM_TCN_BASE(n) (0x40080000+((n)<<6)) diff --git a/arch/arm/src/sam34/chip/sam3u_pmc.h b/arch/arm/src/sam34/chip/sam3u_pmc.h index c14db672c92..817be8e0a07 100644 --- a/arch/arm/src/sam34/chip/sam3u_pmc.h +++ b/arch/arm/src/sam34/chip/sam3u_pmc.h @@ -169,6 +169,7 @@ # define SAM_PMC_PCER1 (SAM_PMC_BASE+SAM_PMC_PCER1_OFFSET) # define SAM_PMC_PCDR1 (SAM_PMC_BASE+SAM_PMC_PCDR1_OFFSET) # define SAM_PMC_PCSR1 (SAM_PMC_BASE+SAM_PMC_PCSR1_OFFSET) +#endif #if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # define SAM_PMC_PCR (SAM_PMC_BASE+SAM_PMC_PCR_OFFSET) diff --git a/arch/arm/src/sam34/chip/sam3u_vectors.h b/arch/arm/src/sam34/chip/sam3u_vectors.h index 29e9d7e2522..cd60941f213 100644 --- a/arch/arm/src/sam34/chip/sam3u_vectors.h +++ b/arch/arm/src/sam34/chip/sam3u_vectors.h @@ -74,7 +74,7 @@ VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+17: High Speed Multimedia Card Interface */ VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+18: Two-Wire Interface 0 */ VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+19: Two-Wire Interface 1 */ - VECTOR(sam_spi, SAM_IRQ_SPI) /* Vector 16+20: Serial Peripheral Interface */ + VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+20: Serial Peripheral Interface */ VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+21: Synchronous Serial Controller */ VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+22: Timer Counter 0 */ VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+23: Timer Counter 1 */ diff --git a/arch/arm/src/sam34/chip/sam4l_memorymap.h b/arch/arm/src/sam34/chip/sam4l_memorymap.h index c85e6b4b811..56810fe442c 100644 --- a/arch/arm/src/sam34/chip/sam4l_memorymap.h +++ b/arch/arm/src/sam34/chip/sam4l_memorymap.h @@ -78,7 +78,7 @@ /* Peripheral Bridge A */ /* 0x40000000-0x40003fff: Reserved */ #define SAM_I2SC_BASE 0x40004000 /* 0x40004000-0x40007fff: I2S Controller */ -#define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ +#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ /* 0x4000c000-0x4000ffff: Reserved */ #define SAM_TC0_BASE 0x40100000 /* 0x40100000-0x4013ffff: Timer Counter 0 */ #define SAM_TC1_BASE 0x40140000 /* 0x40180000-0x4017ffff: Timer Counter 1 */ diff --git a/arch/arm/src/sam34/chip/sam4l_vectors.h b/arch/arm/src/sam34/chip/sam4l_vectors.h index b4158965ff2..15948d3c836 100644 --- a/arch/arm/src/sam34/chip/sam4l_vectors.h +++ b/arch/arm/src/sam34/chip/sam4l_vectors.h @@ -108,7 +108,7 @@ VECTOR(sam_eic7, SAM_IRQ_EIC7) /* Vector 16+51: External Interrupt Controller 7 */ VECTOR(sam_eic8, SAM_IRQ_EIC8) /* Vector 16+52: External Interrupt Controller 8 */ VECTOR(sam_iisc, SAM_IRQ_IISC) /* Vector 16+53: Inter-IC Sound (I2S) Controller */ - VECTOR(sam_spi, SAM_IRQ_SPI) /* Vector 16+54: Serial Peripheral Interface */ + VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+54: Serial Peripheral Interface */ VECTOR(sam_tc00, SAM_IRQ_TC00) /* Vector 16+55: Timer/Counter 0 */ VECTOR(sam_tc01, SAM_IRQ_TC01) /* Vector 16+56: Timer/Counter 1 */ VECTOR(sam_tc02, SAM_IRQ_TC02) /* Vector 16+57: Timer/Counter 2 */ diff --git a/arch/arm/src/sam34/chip/sam4s_memorymap.h b/arch/arm/src/sam34/chip/sam4s_memorymap.h index b6f39a4bdcd..111109ae6c0 100644 --- a/arch/arm/src/sam34/chip/sam4s_memorymap.h +++ b/arch/arm/src/sam34/chip/sam4s_memorymap.h @@ -71,7 +71,7 @@ #define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */ #define SAM_SSC_BASE 0x40004000 /* 0x40004000-0x40007fff: Synchronous Serial Controller */ -#define SAM_SPI_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ +#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */ /* 0x4000c000-0x4000ffff: Reserved */ #define SAM_TC_BASE 0x40010000 /* 0x40010000-0x40017fff: Timer Counters */ # define SAM_TC0_BASE 0x40080000 /* 0x40010000-0x4001003f: Timer Counter 0 */ diff --git a/arch/arm/src/sam34/chip/sam4s_vectors.h b/arch/arm/src/sam34/chip/sam4s_vectors.h index b2587cd1219..5146cd3cc3e 100644 --- a/arch/arm/src/sam34/chip/sam4s_vectors.h +++ b/arch/arm/src/sam34/chip/sam4s_vectors.h @@ -75,7 +75,7 @@ VECTOR(sam_hsmci, SAM_IRQ_HSMCI) /* Vector 16+18: High Speed Multimedia Card Interface */ VECTOR(sam_twi0, SAM_IRQ_TWI0) /* Vector 16+19: Two-Wire Interface 0 */ VECTOR(sam_twi1, SAM_IRQ_TWI1) /* Vector 16+20: Two-Wire Interface 1 */ - VECTOR(sam_spi, SAM_PID_SPI) /* Vector 16+21: Serial Peripheral Interface */ + VECTOR(sam_spi0, SAM_IRQ_SPI0) /* Vector 16+21: Serial Peripheral Interface */ VECTOR(sam_ssc, SAM_IRQ_SSC) /* Vector 16+22: Synchronous Serial Controller */ VECTOR(sam_tc0, SAM_IRQ_TC0) /* Vector 16+23: Timer Counter 0 */ VECTOR(sam_tc1, SAM_IRQ_TC1) /* Vector 16+24: Timer Counter 1 */ diff --git a/arch/arm/src/sam34/chip/sam_spi.h b/arch/arm/src/sam34/chip/sam_spi.h index 9ae83ae20e4..b19ba1b4ed8 100644 --- a/arch/arm/src/sam34/chip/sam_spi.h +++ b/arch/arm/src/sam34/chip/sam_spi.h @@ -80,24 +80,44 @@ /* SPI register adresses ****************************************************************/ -#define SAM_SPI_CR (SAM_SPI_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ -#define SAM_SPI_MR (SAM_SPI_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ -#define SAM_SPI_RDR (SAM_SPI_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */ -#define SAM_SPI_TDR (SAM_SPI_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */ -#define SAM_SPI_SR (SAM_SPI_BASE+SAM_SPI_SR_OFFSET) /* Status Register */ -#define SAM_SPI_IER (SAM_SPI_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */ -#define SAM_SPI_IDR (SAM_SPI_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */ -#define SAM_SPI_IMR (SAM_SPI_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */ -#define SAM_SPI_CSR0 (SAM_SPI_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */ -#define SAM_SPI_CSR1 (SAM_SPI_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */ -#define SAM_SPI_CSR2 (SAM_SPI_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */ -#define SAM_SPI_CSR3 (SAM_SPI_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */ -#define SAM_SPI_WPCR (SAM_SPI_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */ -#define SAM_SPI_WPSR (SAM_SPI_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */ +#define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ +#define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ +#define SAM_SPI0_RDR (SAM_SPI0_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */ +#define SAM_SPI0_TDR (SAM_SPI0_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */ +#define SAM_SPI0_SR (SAM_SPI0_BASE+SAM_SPI_SR_OFFSET) /* Status Register */ +#define SAM_SPI0_IER (SAM_SPI0_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */ +#define SAM_SPI0_IDR (SAM_SPI0_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */ +#define SAM_SPI0_IMR (SAM_SPI0_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */ +#define SAM_SPI0_CSR0 (SAM_SPI0_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */ +#define SAM_SPI0_CSR1 (SAM_SPI0_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */ +#define SAM_SPI0_CSR2 (SAM_SPI0_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */ +#define SAM_SPI0_CSR3 (SAM_SPI0_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */ +#define SAM_SPI0_WPCR (SAM_SPI0_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */ +#define SAM_SPI0_WPSR (SAM_SPI0_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */ #ifdef CONFIG_ARCH_CHIP_SAM4L -# define SAM_SPI_FEATURES (SAM_SPI_BASE+SAM_SPI_FEATURES_OFFSET) -# define SAM_SPI_VERSION (SAM_SPI_BASE+SAM_SPI_VERSION_OFFSET) +# define SAM_SPI0_FEATURES (SAM_SPI0_BASE+SAM_SPI_FEATURES_OFFSET) +# define SAM_SPI0_VERSION (SAM_SPI0_BASE+SAM_SPI_VERSION_OFFSET) +#endif + +#define SAM_SPI1_CR (SAM_SPI1_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ +#define SAM_SPI1_MR (SAM_SPI1_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ +#define SAM_SPI1_RDR (SAM_SPI1_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */ +#define SAM_SPI1_TDR (SAM_SPI1_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */ +#define SAM_SPI1_SR (SAM_SPI1_BASE+SAM_SPI_SR_OFFSET) /* Status Register */ +#define SAM_SPI1_IER (SAM_SPI1_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */ +#define SAM_SPI1_IDR (SAM_SPI1_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */ +#define SAM_SPI1_IMR (SAM_SPI1_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */ +#define SAM_SPI1_CSR0 (SAM_SPI1_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */ +#define SAM_SPI1_CSR1 (SAM_SPI1_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */ +#define SAM_SPI1_CSR2 (SAM_SPI1_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */ +#define SAM_SPI1_CSR3 (SAM_SPI1_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */ +#define SAM_SPI1_WPCR (SAM_SPI1_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */ +#define SAM_SPI1_WPSR (SAM_SPI1_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */ + +#ifdef CONFIG_ARCH_CHIP_SAM4L +# define SAM_SPI1_FEATURES (SAM_SPI1_BASE+SAM_SPI_FEATURES_OFFSET) +# define SAM_SPI1_VERSION (SAM_SPI1_BASE+SAM_SPI_VERSION_OFFSET) #endif /* SPI register bit definitions *********************************************************/ diff --git a/arch/arm/src/sam34/sam3u_periphclks.h b/arch/arm/src/sam34/sam3u_periphclks.h index 09c1abb4d27..5152297052e 100644 --- a/arch/arm/src/sam34/sam3u_periphclks.h +++ b/arch/arm/src/sam34/sam3u_periphclks.h @@ -73,7 +73,7 @@ #define sam_hsmci_enableclk() sam_enableperipheral(SAM_PID_HSMCI) #define sam_twi0_enableclk() sam_enableperipheral(SAM_PID_TWI0) #define sam_twi1_enableclk() sam_enableperipheral(SAM_PID_TWI1) -#define sam_spi_enableclk() sam_enableperipheral(SAM_PID_SPI) +#define sam_spi0_enableclk() sam_enableperipheral(SAM_PID_SPI0) #define sam_ssc_enableclk() sam_enableperipheral(SAM_PID_SSC) #define sam_tc0_enableclk() sam_enableperipheral(SAM_PID_TC0) #define sam_tc1_enableclk() sam_enableperipheral(SAM_PID_TC1) @@ -103,7 +103,7 @@ #define sam_hsmci_disableclk() sam_disableperipheral(SAM_PID_HSMCI) #define sam_twi0_disableclk() sam_disableperipheral(SAM_PID_TWI0) #define sam_twi1_disableclk() sam_disableperipheral(SAM_PID_TWI1) -#define sam_spi_disableclk() sam_disableperipheral(SAM_PID_SPI) +#define sam_spi0_disableclk() sam_disableperipheral(SAM_PID_SPI0) #define sam_ssc_disableclk() sam_disableperipheral(SAM_PID_SSC) #define sam_tc0_disableclk() sam_disableperipheral(SAM_PID_TC0) #define sam_tc1_disableclk() sam_disableperipheral(SAM_PID_TC1) diff --git a/arch/arm/src/sam34/sam4l_periphclks.c b/arch/arm/src/sam34/sam4l_periphclks.c index 2c55ab6b012..f86ca0175be 100644 --- a/arch/arm/src/sam34/sam4l_periphclks.c +++ b/arch/arm/src/sam34/sam4l_periphclks.c @@ -186,7 +186,7 @@ static inline void sam_init_pbamask(void) #ifdef CONFIG_SAM34_IISC mask |= PM_PBAMASK_IISC; /* IISC */ #endif -#ifdef CONFIG_SAM34_SPI +#ifdef CONFIG_SAM34_SPI0 mask |= PM_PBAMASK_SPI; /* SPI */ #endif #ifdef CONFIG_SAM34_TC0 diff --git a/arch/arm/src/sam34/sam4l_periphclks.h b/arch/arm/src/sam34/sam4l_periphclks.h index f7509e278c9..c092e243aa4 100644 --- a/arch/arm/src/sam34/sam4l_periphclks.h +++ b/arch/arm/src/sam34/sam4l_periphclks.h @@ -72,7 +72,7 @@ #define sam_aesa_enableclk() sam_hsb_enableperipheral(PM_HSBMASK_AESA) #define sam_iisc_enableclk() sam_pba_enableperipheral(PM_PBAMASK_IISC) -#define sam_spi_enableclk() sam_pba_enableperipheral(PM_PBAMASK_SPI) +#define sam_spi0_enableclk() sam_pba_enableperipheral(PM_PBAMASK_SPI) #define sam_tc0_enableclk() \ do { \ @@ -170,7 +170,7 @@ #define sam_aesa_disableclk() sam_hsb_disableperipheral(PM_HSBMASK_AESA) #define sam_iisc_disableclk() sam_pba_disableperipheral(PM_PBAMASK_IISC) -#define sam_spi_disableclk() sam_pba_disableperipheral(PM_PBAMASK_SPI) +#define sam_spi0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_SPI) #define sam_tc0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TC0) #define sam_tc1_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TC1) #define sam_twim0_disableclk() sam_pba_disableperipheral(PM_PBAMASK_TWIM0) diff --git a/arch/arm/src/sam34/sam_gpio.h b/arch/arm/src/sam34/sam_gpio.h index 04151158c9c..efa34e462a4 100644 --- a/arch/arm/src/sam34/sam_gpio.h +++ b/arch/arm/src/sam34/sam_gpio.h @@ -49,7 +49,7 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "sam3u_gpio.h" -#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) +#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) # include "sam3x_gpio.h" #elif defined(CONFIG_ARCH_CHIP_SAM4L) # include "sam4l_gpio.h" diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 716cebb37b6..5005003c642 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -63,7 +63,7 @@ #include "chip/sam_spi.h" #include "chip/sam_pinmap.h" -#ifdef CONFIG_SAM34_SPI +#ifdef CONFIG_SAM34_SPI0 /**************************************************************************** * Definitions @@ -203,7 +203,7 @@ static bool g_spinitialized = false; static const uint32_t g_csraddr[4] = { - SAM_SPI_CSR0, SAM_SPI_CSR1, SAM_SPI_CSR2, SAM_SPI_CSR3 + SAM_SPI0_CSR0, SAM_SPI0_CSR1, SAM_SPI0_CSR2, SAM_SPI0_CSR3 }; /**************************************************************************** @@ -233,13 +233,13 @@ static void spi_dumpregs(FAR const char *msg) { spivdbg("%s:\n", msg); spivdbg(" MR:%08x SR:%08x IMR:%08x\n", - getreg32(SAM_SPI_MR), getreg32(SAM_SPI_SR), - getreg32(SAM_SPI_IMR)); + getreg32(SAM_SPI0_MR), getreg32(SAM_SPI0_SR), + getreg32(SAM_SPI0_IMR)); spivdbg(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n", - getreg32(SAM_SPI_CSR0), getreg32(SAM_SPI_CSR1), - getreg32(SAM_SPI_CSR2), getreg32(SAM_SPI_CSR3)); + getreg32(SAM_SPI0_CSR0), getreg32(SAM_SPI0_CSR1), + getreg32(SAM_SPI0_CSR2), getreg32(SAM_SPI0_CSR3)); spivdbg(" WPCR:%08x WPSR:%08x\n", - getreg32(SAM_SPI_WPCR), getreg32(SAM_SPI_WPSR)); + getreg32(SAM_SPI0_WPCR), getreg32(SAM_SPI0_WPSR)); } #endif @@ -261,15 +261,15 @@ static inline void spi_flush(void) { /* Make sure the no TX activity is in progress... waiting if necessary */ - while ((getreg32(SAM_SPI_SR) & SPI_INT_TXEMPTY) == 0); + while ((getreg32(SAM_SPI0_SR) & SPI_INT_TXEMPTY) == 0); /* Then make sure that there is no pending RX data .. reading as * discarding as necessary. */ - while ((getreg32(SAM_SPI_SR) & SPI_INT_RDRF) != 0) + while ((getreg32(SAM_SPI0_SR) & SPI_INT_RDRF) != 0) { - (void)getreg32(SAM_SPI_RDR); + (void)getreg32(SAM_SPI0_RDR); } } @@ -385,10 +385,10 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock) * in order to select a slave. */ - regval = getreg32(SAM_SPI_MR); + regval = getreg32(SAM_SPI0_MR); regval &= ~SPI_MR_PCS_MASK; regval |= (spi_cs2pcs(priv) << SPI_MR_PCS_SHIFT); - putreg32(regval, SAM_SPI_MR); + putreg32(regval, SAM_SPI0_MR); } /* Perform any board-specific chip select operations. PIO chip select @@ -784,24 +784,24 @@ static void spi_exchange(FAR struct spi_dev_s *dev, * to the serializer. */ - while ((getreg32(SAM_SPI_SR) & SPI_INT_TDRE) == 0); + while ((getreg32(SAM_SPI0_SR) & SPI_INT_TDRE) == 0); /* Write the data to transmitted to the Transmit Data Register (TDR) */ - putreg32(data, SAM_SPI_TDR); + putreg32(data, SAM_SPI0_TDR); /* Wait for the read data to be available in the RDR. * TODO: Data transfer rates would be improved using the RX FIFO * (and also DMA) */ - while ((getreg32(SAM_SPI_SR) & SPI_INT_RDRF) == 0); + while ((getreg32(SAM_SPI0_SR) & SPI_INT_RDRF) == 0); /* Read the received data from the SPI Data Register.. * TODO: The following only works if nbits <= 8. */ - data = getreg32(SAM_SPI_RDR); + data = getreg32(SAM_SPI0_RDR); if (rxptr) { *rxptr++ = (uint8_t)data; @@ -931,7 +931,7 @@ FAR struct spi_dev_s *up_spiinitialize(int cs) /* Enable clocking to the SPI block */ flags = irqsave(); - sam_spi_enableclk(); + sam_spi0_enableclk(); /* Configure multiplexed pins as connected on the board. Chip select * pins must be configured by board-specific logic. @@ -943,27 +943,27 @@ FAR struct spi_dev_s *up_spiinitialize(int cs) /* Disable SPI clocking */ - putreg32(SPI_CR_SPIDIS, SAM_SPI_CR); + putreg32(SPI_CR_SPIDIS, SAM_SPI0_CR); /* Execute a software reset of the SPI (twice) */ - putreg32(SPI_CR_SWRST, SAM_SPI_CR); - putreg32(SPI_CR_SWRST, SAM_SPI_CR); + putreg32(SPI_CR_SWRST, SAM_SPI0_CR); + putreg32(SPI_CR_SWRST, SAM_SPI0_CR); irqrestore(flags); /* Configure the SPI mode register */ - putreg32(SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI_MR); + putreg32(SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI0_MR); /* And enable the SPI */ - putreg32(SPI_CR_SPIEN, SAM_SPI_CR); + putreg32(SPI_CR_SPIEN, SAM_SPI0_CR); up_mdelay(20); /* Flush any pending transfers */ - (void)getreg32(SAM_SPI_SR); - (void)getreg32(SAM_SPI_RDR); + (void)getreg32(SAM_SPI0_SR); + (void)getreg32(SAM_SPI0_RDR); #ifndef CONFIG_SPI_OWNBUS /* Initialize the SPI semaphore that enforces mutually exclusive @@ -978,4 +978,4 @@ FAR struct spi_dev_s *up_spiinitialize(int cs) return &priv->spidev; } -#endif /* CONFIG_SAM34_SPI */ +#endif /* CONFIG_SAM34_SPI0 */ diff --git a/arch/arm/src/sam34/sam_spi.h b/arch/arm/src/sam34/sam_spi.h index dfcfe20b3aa..a3150fffd68 100644 --- a/arch/arm/src/sam34/sam_spi.h +++ b/arch/arm/src/sam34/sam_spi.h @@ -111,7 +111,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_SAM34_SPI +#ifdef CONFIG_SAM34_SPI0 struct spi_dev_s; enum spi_dev_e; @@ -187,7 +187,7 @@ uint8_t sam_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid); #ifdef CONFIG_SPI_CMDDATA int sam_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); #endif -#endif /* CONFIG_SAM34_SPI */ +#endif /* CONFIG_SAM34_SPI0 */ #undef EXTERN #if defined(__cplusplus)