diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig index acd40f25c25..effdea65133 100644 --- a/arch/arm/src/nrf52/Kconfig +++ b/arch/arm/src/nrf52/Kconfig @@ -94,6 +94,10 @@ config NRF52_TIMER bool default n +config NRF52_RTC + bool + default n + config NRF52_SPI_MASTER_WORKAROUND_1BYTE_TRANSFER bool "SPI Master 1 Byte transfer anomaly workaround" depends on NRF52_SPI_MASTER && ARCH_FAMILY_NRF52832 @@ -210,14 +214,17 @@ config NRF52_TIMER4 config NRF52_RTC0 bool "RTC0" + select NRF52_RTC default n config NRF52_RTC1 bool "RTC1" + select NRF52_RTC default n config NRF52_RTC2 bool "RTC2" + select NRF52_RTC default n config NRF52_I2S diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs index 74f172a1fba..ecdfa7c80ba 100644 --- a/arch/arm/src/nrf52/Make.defs +++ b/arch/arm/src/nrf52/Make.defs @@ -133,3 +133,7 @@ endif ifeq ($(CONFIG_NRF52_TIMER),y) CHIP_CSRCS += nrf52_tim.c endif + +ifeq ($(CONFIG_NRF52_RTC),y) +CHIP_CSRCS += nrf52_rtc.c +endif diff --git a/arch/arm/src/nrf52/hardware/nrf52_rtc.h b/arch/arm/src/nrf52/hardware/nrf52_rtc.h new file mode 100644 index 00000000000..b6c79e556db --- /dev/null +++ b/arch/arm/src/nrf52/hardware/nrf52_rtc.h @@ -0,0 +1,108 @@ +/************************************************************************************ + * arch/arm/src/nrf52/hardware/nrf52_rtc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RTC_H +#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "hardware/nrf52_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets for RTC *********************************************************/ + +#define NRF52_RTC_TASKS_START_OFFSET 0x0000 /* Start RTC counter */ +#define NRF52_RTC_TASKS_STOP_OFFSET 0x0004 /* Stop RTC counter */ +#define NRF52_RTC_TASKS_CLEAR_OFFSET 0x0008 /* Clear RTC counter */ +#define NRF52_RTC_TASKS_TRIGOVRFLW_OFFSET 0x000c /* Clear Set counter to 0xfffff0 */ +#define NRF52_RTC_EVENTS_TICK_OFFSET 0x0100 /* Event on counter increment */ +#define NRF52_RTC_EVENTS_OVRFLW_OFFSET 0x0104 /* Event on counter overflow */ +#define NRF52_RTC_EVENTS_COMPARE_OFFSET(x) (0x0140 + ((x) * 0x04)) /* Compare event on CC[x] match */ +#define NRF52_RTC_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_RTC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_RTC_EVTEN_OFFSET 0x0340 /* Enable or disable event routing */ +#define NRF52_RTC_EVTENSET_OFFSET 0x0344 /* Enable event routing */ +#define NRF52_RTC_EVTENCLR_OFFSET 0x0348 /* Disable event routing */ +#define NRF52_RTC_COUNTER_OFFSET 0x0504 /* Current counter value */ +#define NRF52_RTC_PRESCALER_OFFSET 0x0508 /* 12 bit prescaler for counter frequency */ +#define NRF52_RTC_CC_OFFSET(x) (0x0540 + ((x) * 0x04)) /* Compare register x */ + +/* Register offsets for RTC *********************************************************/ + +/* TASKS_START Register */ + +#define RTC_TASKS_START (1 << 0) /* Bit 0: Start RTC counter */ + +/* TASKS_STOP Register */ + +#define RTC_TASKS_STOP (1 << 0) /* Bit 0: Stop RTC counter */ + +/* TASKS_CLEAR Register */ + +#define RTC_TASKS_CLEAR (1 << 0) /* Bit 0: Clear RTC counter */ + +/* TASKS_TRIGOVRFLW Register */ + +#define RTC_TASKS_TRIGOVRFLW (1 << 0) /* Bit 0: Set counter to 0xfffff0 */ + +/* EVENTS_TICK Register */ + +#define RTC_EVENTS_TICK (1 << 0) /* Bit 0: Event on counter increment */ + +/* EVENTS_OVRFLW Register */ + +#define RTC_EVENTS_OVRFLW (1 << 0) /* Bit 0: Event on counter overflow */ + +/* EVENTS_COMPARE Register */ + +#define RTC_EVENTS_COMPARE (1 << 0) /* Bit 0: Eompare event on CC[x] match */ + +/* INTENSET/INTENCLR Register */ + +#define RTC_INT_TICK (1 << 0) /* Bit 0: TICK interrupt*/ +#define RTC_INT_OVRFLW (1 << 1) /* Bit 1: OVRFLW interrupt */ +#define RTC_INT_COMPARE(x) (1 << (16 + (x))) /* Bit 16-19: COMPARE[x] interrupt */ + +/* EVTEN/EVTENSET/EVTSENCLR Register */ + +#define RTC_EVTEN_TICK (1 << 0) /* Bit 0: TICK event */ +#define RTC_EVTEN_OVRFLW (1 << 1) /* Bit 1: OVRFLW event */ +#define RTC_EVTEN_COMPARE(x) (1 << (16 + (x))) /* Bit 16-19: COMPARE[x] event */ + +/* COUNTER Register */ + +#define RTC_COUNTER_MASK (0x00ffffff) /* Bits 0-23: Counter value */ + +/* PRESCALER Register */ + +#define RTC_PRESCALER_MASK (0x00000fff) /* Bits 0-11: Prescaler value */ +#define RTC_PRESCALER_MAX (0x00000fff) + +/* CC Register */ + +#define RTC_CC_MASK (0x00ffffff) /* Bits 0-23: Comapre register */ + +#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_RTC_H */ diff --git a/arch/arm/src/nrf52/nrf52_rtc.c b/arch/arm/src/nrf52/nrf52_rtc.c new file mode 100644 index 00000000000..51f9b990b7d --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_rtc.c @@ -0,0 +1,672 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_rtc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_arch.h" + +#include "hardware/nrf52_rtc.h" + +#include "nrf52_rtc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct nrf52_rtc_priv_s +{ + FAR struct nrf52_rtc_ops_s *ops; + uint32_t base; + uint32_t irq; + uint8_t chan; + bool inuse; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* RTC registers access *****************************************************/ + +static uint32_t nrf52_rtc_getreg(FAR struct nrf52_rtc_dev_s *dev, + uint32_t offset); +static void nrf52_rtc_putreg(FAR struct nrf52_rtc_dev_s *dev, + uint32_t offset, + uint32_t value); + +/* RTC helpers **************************************************************/ + +static uint32_t nrf52_rtc_irq2reg(FAR struct nrf52_rtc_dev_s *dev, + uint8_t s); + +/* RTC operations ***********************************************************/ + +static int nrf52_rtc_start(FAR struct nrf52_rtc_dev_s *dev); +static int nrf52_rtc_stop(FAR struct nrf52_rtc_dev_s *dev); +static int nrf52_rtc_clear(FAR struct nrf52_rtc_dev_s *dev); +static int nrf52_rtc_trgovrflw(FAR struct nrf52_rtc_dev_s *dev); +static int nrf52_rtc_setcc(FAR struct nrf52_rtc_dev_s *dev, uint8_t i, + uint32_t cc); +static int nrf52_rtc_getcc(FAR struct nrf52_rtc_dev_s *dev, uint8_t i, + FAR uint32_t *cc); +static int nrf52_rtc_setpre(FAR struct nrf52_rtc_dev_s *dev, uint16_t pre); +static int nrf52_rtc_setisr(FAR struct nrf52_rtc_dev_s *dev, xcpt_t handler, + FAR void * arg); +static int nrf52_rtc_enableint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s); +static int nrf52_rtc_disableint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s); +static int nrf52_rtc_checkint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s); +static int nrf52_rtc_ackint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* NRF52 RTC ops */ + +struct nrf52_rtc_ops_s nrf52_rtc_ops = +{ + .start = nrf52_rtc_start, + .stop = nrf52_rtc_stop, + .clear = nrf52_rtc_clear, + .trgovrflw = nrf52_rtc_trgovrflw, + .setcc = nrf52_rtc_setcc, + .getcc = nrf52_rtc_getcc, + .setpre = nrf52_rtc_setpre, + .setisr = nrf52_rtc_setisr, + .enableint = nrf52_rtc_enableint, + .disableint = nrf52_rtc_disableint, + .checkint = nrf52_rtc_checkint, + .ackint = nrf52_rtc_ackint +}; + +#ifdef CONFIG_NRF52_RTC0 +/* RTC0 */ + +struct nrf52_rtc_priv_s g_nrf52_rtc0_priv = +{ + .ops = &nrf52_rtc_ops, + .base = NRF52_RTC0_BASE, + .irq = NRF52_IRQ_RTC0, + .chan = 3, + .inuse = false, +}; +#endif + +#ifdef CONFIG_NRF52_RTC1 +/* RTC1 */ + +struct nrf52_rtc_priv_s g_nrf52_rtc1_priv = +{ + .ops = &nrf52_rtc_ops, + .base = NRF52_RTC1_BASE, + .irq = NRF52_IRQ_RTC1, + .chan = 4, + .inuse = false, +}; +#endif + +#ifdef CONFIG_NRF52_RTC2 +/* RTC2 */ + +struct nrf52_rtc_priv_s g_nrf52_rtc2_priv = +{ + .ops = &nrf52_rtc_ops, + .base = NRF52_RTC2_BASE, + .irq = NRF52_IRQ_RTC2, + .chan = 4, + .inuse = false, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_rtc_getreg + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static uint32_t nrf52_rtc_getreg(FAR struct nrf52_rtc_dev_s *dev, + uint32_t offset) +{ + DEBUGASSERT(dev); + + return getreg32(((struct nrf52_rtc_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: nrf52_rtc_putreg + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static void nrf52_rtc_putreg(FAR struct nrf52_rtc_dev_s *dev, + uint32_t offset, + uint32_t value) +{ + DEBUGASSERT(dev); + + putreg32(value, ((struct nrf52_rtc_priv_s *)dev)->base + offset); +} + +/**************************************************************************** + * Name: nrf52_rtc_irq2reg + * + * Description: + * Get the vaule of the interrupt register corresponding to the given + * interrupt source + * + ****************************************************************************/ + +static uint32_t nrf52_rtc_irq2reg(FAR struct nrf52_rtc_dev_s *dev, uint8_t s) +{ + uint32_t regval = 0; + + switch (s) + { + case NRF52_RTC_INT_TICK: + { + regval = RTC_INT_TICK; + break; + } + + case NRF52_RTC_INT_OVRFLW: + { + regval = RTC_INT_OVRFLW; + break; + } + + case NRF52_RTC_INT_COMPARE0: + { + regval = RTC_INT_COMPARE(0); + break; + } + + case NRF52_RTC_INT_COMPARE1: + { + regval = RTC_INT_COMPARE(1); + break; + } + + case NRF52_RTC_INT_COMPARE2: + { + regval = RTC_INT_COMPARE(2); + break; + } + + case NRF52_RTC_INT_COMPARE3: + { + regval = RTC_INT_COMPARE(3); + break; + } + + default: + { + rtcerr("ERROR: unsupported IRQ source %d\n", s); + regval = 0; + goto errout; + } + } + +errout: + return regval; +} + +/**************************************************************************** + * Name: nrf52_rtc_start + ****************************************************************************/ + +static int nrf52_rtc_start(FAR struct nrf52_rtc_dev_s *dev) +{ + DEBUGASSERT(dev); + + nrf52_rtc_putreg(dev, NRF52_RTC_TASKS_START_OFFSET, RTC_TASKS_START); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_rtc_stop + ****************************************************************************/ + +static int nrf52_rtc_stop(FAR struct nrf52_rtc_dev_s *dev) +{ + DEBUGASSERT(dev); + + nrf52_rtc_putreg(dev, NRF52_RTC_TASKS_STOP_OFFSET, RTC_TASKS_STOP); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_rtc_clear + ****************************************************************************/ + +static int nrf52_rtc_clear(FAR struct nrf52_rtc_dev_s *dev) +{ + DEBUGASSERT(dev); + + nrf52_rtc_putreg(dev, NRF52_RTC_TASKS_CLEAR_OFFSET, RTC_TASKS_CLEAR); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_rtc_trgovrflw + ****************************************************************************/ + +static int nrf52_rtc_trgovrflw(FAR struct nrf52_rtc_dev_s *dev) +{ + DEBUGASSERT(dev); + + nrf52_rtc_putreg(dev, NRF52_RTC_TASKS_TRIGOVRFLW_OFFSET, + RTC_TASKS_TRIGOVRFLW); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_rtc_setcc + ****************************************************************************/ + +static int nrf52_rtc_setcc(FAR struct nrf52_rtc_dev_s *dev, uint8_t i, + uint32_t cc) +{ + FAR struct nrf52_rtc_priv_s *rtc = NULL; + int ret = OK; + + DEBUGASSERT(dev); + + rtc = (FAR struct nrf52_rtc_priv_s *)dev; + + /* Is the channel supported? */ + + if (i > rtc->chan) + { + rtcerr("ERROR: unsupported RTCER channel %d\n", i); + ret = -EINVAL; + goto errout; + } + + nrf52_rtc_putreg(dev, NRF52_RTC_CC_OFFSET(i), cc); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_rtc_getcc + ****************************************************************************/ + +static int nrf52_rtc_getcc(FAR struct nrf52_rtc_dev_s *dev, uint8_t i, + FAR uint32_t *cc) +{ + FAR struct nrf52_rtc_priv_s *rtc = NULL; + int ret = OK; + + DEBUGASSERT(dev); + DEBUGASSERT(cc); + + rtc = (FAR struct nrf52_rtc_priv_s *)dev; + + /* Is the channel supported? */ + + if (i > rtc->chan) + { + rtcerr("ERROR: unsupported RTCER channel %d\n", i); + ret = -EINVAL; + goto errout; + } + + *cc = nrf52_rtc_getreg(dev, NRF52_RTC_CC_OFFSET(i)); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_rtc_setpre + ****************************************************************************/ + +static int nrf52_rtc_setpre(FAR struct nrf52_rtc_dev_s *dev, uint16_t pre) +{ + int ret = OK; + + DEBUGASSERT(dev); + + if (pre > RTC_PRESCALER_MAX) + { + rtcerr("ERROR: unsupported RTC prescaler %d\n", pre); + ret = -EINVAL; + goto errout; + } + + nrf52_rtc_putreg(dev, NRF52_RTC_PRESCALER_OFFSET, pre); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_rtc_setisr + ****************************************************************************/ + +static int nrf52_rtc_setisr(FAR struct nrf52_rtc_dev_s *dev, xcpt_t handler, + FAR void *arg) +{ + FAR struct nrf52_rtc_priv_s *rtc = NULL; + int ret = OK; + + DEBUGASSERT(dev); + + rtc = (FAR struct nrf52_rtc_priv_s *)dev; + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(rtc->irq); + irq_detach(rtc->irq); + ret = OK; + goto errout; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(rtc->irq, handler, arg); + up_enable_irq(rtc->irq); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_rtc_enableint + ****************************************************************************/ + +static int nrf52_rtc_enableint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s) +{ + uint32_t regval = 0; + int ret = OK; + + DEBUGASSERT(dev); + + /* Get register value for given interrupt source */ + + regval = nrf52_rtc_irq2reg(dev, s); + if (regval == 0) + { + ret = -EINVAL; + goto errout; + } + + nrf52_rtc_putreg(dev, NRF52_RTC_INTENSET_OFFSET, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_rtc_disableint + ****************************************************************************/ + +static int nrf52_rtc_disableint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s) +{ + uint32_t regval = 0; + int ret = OK; + + DEBUGASSERT(dev); + + /* Get register value for given interrupt source */ + + regval = nrf52_rtc_irq2reg(dev, s); + if (regval == 0) + { + ret = -EINVAL; + goto errout; + } + + nrf52_rtc_putreg(dev, NRF52_RTC_INTENCLR_OFFSET, regval); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_rtc_checkint + ****************************************************************************/ + +static int nrf52_rtc_checkint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s) +{ + int ret = 0; + + DEBUGASSERT(dev); + + switch (s) + { + case NRF52_RTC_INT_TICK: + { + ret = nrf52_rtc_getreg(dev, NRF52_RTC_EVENTS_TICK_OFFSET); + break; + } + + case NRF52_RTC_INT_OVRFLW: + { + ret = nrf52_rtc_getreg(dev, NRF52_RTC_EVENTS_OVRFLW_OFFSET); + break; + } + + case NRF52_RTC_INT_COMPARE0: + { + ret = nrf52_rtc_getreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(0)); + break; + } + + case NRF52_RTC_INT_COMPARE1: + { + ret = nrf52_rtc_getreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(0)); + break; + } + + case NRF52_RTC_INT_COMPARE2: + { + ret = nrf52_rtc_getreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(2)); + break; + } + + case NRF52_RTC_INT_COMPARE3: + { + ret = nrf52_rtc_getreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(3)); + break; + } + + default: + { + rtcerr("ERROR: unsupported IRQ source %d\n", s); + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_rtc_ackint + ****************************************************************************/ + +static int nrf52_rtc_ackint(FAR struct nrf52_rtc_dev_s *dev, uint8_t s) +{ + int ret = 0; + + DEBUGASSERT(dev); + + switch (s) + { + case NRF52_RTC_INT_TICK: + { + nrf52_rtc_putreg(dev, NRF52_RTC_EVENTS_TICK_OFFSET, 0); + break; + } + + case NRF52_RTC_INT_OVRFLW: + { + nrf52_rtc_putreg(dev, NRF52_RTC_EVENTS_OVRFLW_OFFSET, 0); + break; + } + + case NRF52_RTC_INT_COMPARE0: + { + nrf52_rtc_putreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(0), 0); + break; + } + + case NRF52_RTC_INT_COMPARE1: + { + nrf52_rtc_putreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(1), 0); + break; + } + + case NRF52_RTC_INT_COMPARE2: + { + nrf52_rtc_putreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(2), 0); + break; + } + + case NRF52_RTC_INT_COMPARE3: + { + nrf52_rtc_putreg(dev, NRF52_RTC_EVENTS_COMPARE_OFFSET(3), 0); + break; + } + + default: + { + rtcerr("ERROR: unsupported IRQ source %d\n", s); + ret = -EINVAL; + goto errout; + } + } + +errout: + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_rtc_init + * + * Description: + * Initialize RTC device + * + ****************************************************************************/ + +FAR struct nrf52_rtc_dev_s *nrf52_rtc_init(int rtc) +{ + FAR struct nrf52_rtc_priv_s *priv = NULL; + + /* Get RTC instance */ + + switch (rtc) + { +#ifdef CONFIG_NRF52_RTC0 + case 0: + { + priv = &g_nrf52_rtc0_priv; + break; + } +#endif + +#ifdef CONFIG_NRF52_RTC1 + case 1: + { + priv = &g_nrf52_rtc1_priv; + break; + } +#endif + +#ifdef CONFIG_NRF52_RTC2 + case 2: + { + priv = &g_nrf52_rtc2_priv; + break; + } +#endif + + default: + { + rtcerr("ERROR: unsupported RTC %d\n", rtc); + goto errout; + } + } + + if (priv->inuse != false) + { + /* RTC already in use */ + + priv = NULL; + } + +errout: + return (FAR struct nrf52_rtc_dev_s *)priv; +} + +/**************************************************************************** + * Name: nrf52_rtc_deinit + * + * Description: + * Deinit RTC device + * + ****************************************************************************/ + +int nrf52_rtc_deinit(FAR struct nrf52_rtc_dev_s *dev) +{ + FAR struct nrf52_rtc_priv_s *rtc = NULL; + + DEBUGASSERT(dev); + + rtc = (FAR struct nrf52_rtc_priv_s *)dev; + + rtc->inuse = false; + + return OK; +} diff --git a/arch/arm/src/nrf52/nrf52_rtc.h b/arch/arm/src/nrf52/nrf52_rtc.h new file mode 100644 index 00000000000..03dbb26369b --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_rtc.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_rtc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_RTC_H +#define __ARCH_ARM_SRC_NRF52_NRF52_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define NRF52_RTC_START(d) ((d)->ops->start(d)) +#define NRF52_RTC_STOP(d) ((d)->ops->stop(d)) +#define NRF52_RTC_CLEAR(d) ((d)->ops->clear(d)) +#define NRF52_RTC_TRGOVRFLW(d) ((d)->ops->trgovrflw(d)) +#define NRF52_RTC_SETCC(d, i, cc) ((d)->ops->setcc(d, i, cc)) +#define NRF52_RTC_GETCC(d, i, cc) ((d)->ops->setcc(d, i, cc)) +#define NRF52_RTC_SETPRE(d, pre) ((d)->ops->setpre(d, pre)) +#define NRF52_RTC_SETISR(d, hnd, arg, s) ((d)->ops->setisr(d, hnd, arg, s)) +#define NRF52_RTC_ENABLEINT(d, s) ((d)->ops->enableint(d, s)) +#define NRF52_RTC_DISABLEINT(d, s) ((d)->ops->disableint(d, s)) +#define NRF52_RTC_CHECKINT(d, s) ((d)->ops->checkint(d, s)) +#define NRF52_RTC_ACKINT(d, s) ((d)->ops->ackint(d, s)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* RTC CC index */ + +enum nrf52_rtc_cc_e +{ + NRF52_RTC_CC0 = 0, + NRF52_RTC_CC1 = 1, + NRF52_RTC_CC2 = 2, + NRF52_RTC_CC3 = 3, +}; + +/* RTC IRQ source */ + +enum nrf52_rtc_irq_e +{ + NRF52_RTC_INT_TICK = 0, + NRF52_RTC_INT_OVRFLW = 1, + NRF52_RTC_INT_COMPARE0 = 2, + NRF52_RTC_INT_COMPARE1 = 3, + NRF52_RTC_INT_COMPARE2 = 4, + NRF52_RTC_INT_COMPARE3 = 5, +}; + +/* NRF52 RTC device */ + +struct nrf52_rtc_dev_s +{ + struct nrf52_rtc_ops_s *ops; +}; + +/* NRF52 RTC ops */ + +struct nrf52_rtc_ops_s +{ + /* RTC tasks */ + + CODE int (*start)(FAR struct nrf52_rtc_dev_s *dev); + CODE int (*stop)(FAR struct nrf52_rtc_dev_s *dev); + CODE int (*clear)(FAR struct nrf52_rtc_dev_s *dev); + CODE int (*trgovrflw)(FAR struct nrf52_rtc_dev_s *dev); + + /* RTC operations */ + + CODE int (*setcc)(FAR struct nrf52_rtc_dev_s *dev, uint8_t i, uint32_t cc); + CODE int (*getcc)(FAR struct nrf52_rtc_dev_s *dev, uint8_t i, + FAR uint32_t *cc); + CODE int (*setpre)(FAR struct nrf52_rtc_dev_s *dev, uint16_t pre); + + /* RTC interrupts */ + + CODE int (*setisr)(FAR struct nrf52_rtc_dev_s *dev, xcpt_t handler, + FAR void * arg); + CODE int (*enableint)(FAR struct nrf52_rtc_dev_s *dev, uint8_t source); + CODE int (*disableint)(FAR struct nrf52_rtc_dev_s *dev, uint8_t source); + CODE int (*checkint)(FAR struct nrf52_rtc_dev_s *dev, uint8_t source); + CODE int (*ackint)(FAR struct nrf52_rtc_dev_s *dev, uint8_t source); +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +FAR struct nrf52_rtc_dev_s *nrf52_rtc_init(int rtc); +int nrf52_rtc_deinit(FAR struct nrf52_rtc_dev_s *dev); + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_RTC_H */