diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h
index 46154061f37..6c31d2c788d 100644
--- a/arch/xtensa/include/esp32/irq.h
+++ b/arch/xtensa/include/esp32/irq.h
@@ -332,9 +332,9 @@
  * CPU peripheral interrupts can be a assigned to a CPU interrupt using the
  * PRO_*_MAP_REG or APP_*_MAP_REG.  There are a pair of these registers for
  * each peripheral source.  Multiple peripheral interrupt sources can be
- * mapped to the same.
+ * mapped to the same CPU interrupt.
  *
- * The remaining, five, internal CPU interrupts are:
+ * The remaining, six, internal CPU interrupts are:
  *
  *   6   Timer0    - Priority 1
  *   7   Software  - Priority 1
diff --git a/arch/xtensa/src/common/xtensa_assert.c b/arch/xtensa/src/common/xtensa_assert.c
index 0c5d4fefecf..88e8ea4d673 100644
--- a/arch/xtensa/src/common/xtensa_assert.c
+++ b/arch/xtensa/src/common/xtensa_assert.c
@@ -235,8 +235,8 @@ void xtensa_panic(int xptcode, uint32_t *regs)
  * Name: xtensa_user
  *
  * Description:
- *   PANIC if certain User Exceptions are received received.  All values for
- *   EXCCAUSE are listed below (not all generate PANICs):
+ *   PANIC if certain User Exceptions are received.  All values for EXCCAUSE
+ *   are listed below (not all generate PANICs):
  *
  *   0  IllegalInstructionCause
  *      Illegal instruction
diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c
index 0a0df84f5e1..fb16154fd92 100644
--- a/arch/xtensa/src/common/xtensa_exit.c
+++ b/arch/xtensa/src/common/xtensa_exit.c
@@ -135,7 +135,7 @@ static void _xtensa_dumponexit(FAR struct tcb_s *tcb, FAR void *arg)
  *   This function causes the currently executing task to cease
  *   to exist.  This is a special case of task_delete() where the task to
  *   be deleted is the currently executing task.  It is more complex because
- *   a context switch must be perform to the next ready to run task.
+ *   a context switch must be performed to the next ready to run task.
  *
  ****************************************************************************/
 
diff --git a/arch/xtensa/src/common/xtensa_sigdeliver.c b/arch/xtensa/src/common/xtensa_sigdeliver.c
index 5afdd23ca38..92879f731bb 100644
--- a/arch/xtensa/src/common/xtensa_sigdeliver.c
+++ b/arch/xtensa/src/common/xtensa_sigdeliver.c
@@ -90,8 +90,9 @@ void xtensa_sig_deliver(void)
   saved_irqcount = rtcb->irqcount - 1;
   DEBUGASSERT(saved_irqcount >= 0);
 
-  /* Now we need call leave_critical_section() repeatedly to get the irqcount
-   * to zero, freeing all global spinlocks that enforce the critical section.
+  /* Now we need to call leave_critical_section() repeatedly to get the
+   * irqcount to zero, freeing all global spinlocks that enforce the critical
+   * section.
    */
 
   do
diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c
index aeae8455712..aa41b1d4ed7 100644
--- a/arch/xtensa/src/esp32/esp32_cpuint.c
+++ b/arch/xtensa/src/esp32/esp32_cpuint.c
@@ -233,7 +233,7 @@ static inline void xtensa_disable_all(void)
  *
  ****************************************************************************/
 
-int esp32_alloc_cpuint(uint32_t intmask)
+static int esp32_alloc_cpuint(uint32_t intmask)
 {
   irqstate_t flags;
   uint32_t *freeints;
@@ -375,7 +375,7 @@ int esp32_cpuint_initialize(void)
    *   CPU interrupt bit           IRQ number
    *   --------------------------- ---------------------
    *   ESP32_CPUINT_TIMER0      6  XTENSA_IRQ_TIMER0  0
-   *   SP32_CPUINT_SOFTWARE0    7  Not yet defined
+   *   ESP32_CPUINT_SOFTWARE0   7  Not yet defined
    *   ESP32_CPUINT_PROFILING  11  Not yet defined
    *   ESP32_CPUINT_TIMER1     15  XTENSA_IRQ_TIMER1  1
    *   ESP32_CPUINT_TIMER2     16  XTENSA_IRQ_TIMER2  2
@@ -446,7 +446,7 @@ void up_enable_irq(int cpuint)
  *   priority - Priority of the CPU interrupt (1-5)
  *
  * Returned Value:
- *   On success, the allocated level-sensitive, CPU interrupt numbr is
+ *   On success, the allocated level-sensitive, CPU interrupt number is
  *   returned.  A negated errno is returned on failure.  The only possible
  *   failure is that all level-sensitive CPU interrupts have already been
  *   allocated.
diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c
index 43322a5b5f2..cb22cabc3c1 100644
--- a/arch/xtensa/src/esp32/esp32_irq.c
+++ b/arch/xtensa/src/esp32/esp32_irq.c
@@ -55,8 +55,8 @@
  * Public Data
  ****************************************************************************/
 
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure.  If is non-NULL only during interrupt
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure.  It is non-NULL only during interrupt
  * processing.  Access to g_current_regs[] must be through the macro
  * CURRENT_REGS for portability.
  */