diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ea608d65be5..1a27451741b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -789,6 +789,14 @@ config ARM_THUMB
 	default n
 	depends on ARCH_ARMV7A
 
+config ARM_HAVE_FPU_D32
+	bool
+	select ARCH_HAVE_FPU
+	default n
+	---help---
+		FPU implemented in the VFPv3-D32 format that supports
+		32 double-precision floating-point registers.
+
 config ARM_HAVE_MPU_UNIFIED
 	bool
 	default n
diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h
index a70ff80d8d4..8d44f90e214 100644
--- a/arch/arm/include/armv7-a/irq.h
+++ b/arch/arm/include/armv7-a/irq.h
@@ -151,8 +151,29 @@
 #  define REG_D15           (ARM_CONTEXT_REGS+30) /* D15 */
 #  define REG_S30           (ARM_CONTEXT_REGS+30) /* S30 */
 #  define REG_S31           (ARM_CONTEXT_REGS+31) /* S31 */
-#  define REG_FPSCR         (ARM_CONTEXT_REGS+32) /* Floating point status and control */
-#  define FPU_CONTEXT_REGS  (33)
+#  ifdef CONFIG_ARM_HAVE_FPU_D32
+#    define REG_D16         (ARM_CONTEXT_REGS+32) /* D16 */
+#    define REG_D17         (ARM_CONTEXT_REGS+34) /* D17 */
+#    define REG_D18         (ARM_CONTEXT_REGS+36) /* D18 */
+#    define REG_D19         (ARM_CONTEXT_REGS+38) /* D19 */
+#    define REG_D20         (ARM_CONTEXT_REGS+40) /* D20 */
+#    define REG_D21         (ARM_CONTEXT_REGS+42) /* D21 */
+#    define REG_D22         (ARM_CONTEXT_REGS+44) /* D22 */
+#    define REG_D23         (ARM_CONTEXT_REGS+46) /* D23 */
+#    define REG_D24         (ARM_CONTEXT_REGS+48) /* D24 */
+#    define REG_D25         (ARM_CONTEXT_REGS+50) /* D25 */
+#    define REG_D26         (ARM_CONTEXT_REGS+52) /* D26 */
+#    define REG_D27         (ARM_CONTEXT_REGS+54) /* D27 */
+#    define REG_D28         (ARM_CONTEXT_REGS+56) /* D28 */
+#    define REG_D29         (ARM_CONTEXT_REGS+58) /* D29 */
+#    define REG_D30         (ARM_CONTEXT_REGS+60) /* D30 */
+#    define REG_D31         (ARM_CONTEXT_REGS+62) /* D31 */
+#    define REG_FPSCR       (ARM_CONTEXT_REGS+64) /* Floating point status and control */
+#    define FPU_CONTEXT_REGS  (65)
+#  else
+#    define REG_FPSCR       (ARM_CONTEXT_REGS+32) /* Floating point status and control */
+#    define FPU_CONTEXT_REGS  (33)
+#  endif
 #else
 #  define FPU_CONTEXT_REGS  (0)
 #endif
diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h
index ffc9952c8aa..94e8eab5bc2 100644
--- a/arch/arm/include/armv7-r/irq.h
+++ b/arch/arm/include/armv7-r/irq.h
@@ -151,8 +151,29 @@
 #  define REG_D15           (ARM_CONTEXT_REGS+30) /* D15 */
 #  define REG_S30           (ARM_CONTEXT_REGS+30) /* S30 */
 #  define REG_S31           (ARM_CONTEXT_REGS+31) /* S31 */
-#  define REG_FPSCR         (ARM_CONTEXT_REGS+32) /* Floating point status and control */
-#  define FPU_CONTEXT_REGS  (33)
+#  ifdef CONFIG_ARM_HAVE_FPU_D32
+#    define REG_D16         (ARM_CONTEXT_REGS+32) /* D16 */
+#    define REG_D17         (ARM_CONTEXT_REGS+34) /* D17 */
+#    define REG_D18         (ARM_CONTEXT_REGS+36) /* D18 */
+#    define REG_D19         (ARM_CONTEXT_REGS+38) /* D19 */
+#    define REG_D20         (ARM_CONTEXT_REGS+40) /* D20 */
+#    define REG_D21         (ARM_CONTEXT_REGS+42) /* D21 */
+#    define REG_D22         (ARM_CONTEXT_REGS+44) /* D22 */
+#    define REG_D23         (ARM_CONTEXT_REGS+46) /* D23 */
+#    define REG_D24         (ARM_CONTEXT_REGS+48) /* D24 */
+#    define REG_D25         (ARM_CONTEXT_REGS+50) /* D25 */
+#    define REG_D26         (ARM_CONTEXT_REGS+52) /* D26 */
+#    define REG_D27         (ARM_CONTEXT_REGS+54) /* D27 */
+#    define REG_D28         (ARM_CONTEXT_REGS+56) /* D28 */
+#    define REG_D29         (ARM_CONTEXT_REGS+58) /* D29 */
+#    define REG_D30         (ARM_CONTEXT_REGS+60) /* D30 */
+#    define REG_D31         (ARM_CONTEXT_REGS+62) /* D31 */
+#    define REG_FPSCR       (ARM_CONTEXT_REGS+64) /* Floating point status and control */
+#    define FPU_CONTEXT_REGS  (65)
+#  else
+#    define REG_FPSCR       (ARM_CONTEXT_REGS+32) /* Floating point status and control */
+#    define FPU_CONTEXT_REGS  (33)
+#  endif
 #else
 #  define FPU_CONTEXT_REGS  (0)
 #endif
diff --git a/arch/arm/src/armv7-a/arm_fullcontextrestore.S b/arch/arm/src/armv7-a/arm_fullcontextrestore.S
index b80820d38ac..ef135b226ee 100644
--- a/arch/arm/src/armv7-a/arm_fullcontextrestore.S
+++ b/arch/arm/src/armv7-a/arm_fullcontextrestore.S
@@ -79,7 +79,12 @@ arm_fullcontextrestore:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vldmia.64	r1!, {d0-d15}			/* Restore the full FP context */
+	vldmia.64	r1!, {d16-d31}
+#else
 	vldmia		r1!, {s0-s31}			/* Restore the full FP context */
+#endif
 
 	/* Load the floating point control and status register.   At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.
diff --git a/arch/arm/src/armv7-a/arm_restorefpu.S b/arch/arm/src/armv7-a/arm_restorefpu.S
index 9e38154adc3..b3eb162a69f 100644
--- a/arch/arm/src/armv7-a/arm_restorefpu.S
+++ b/arch/arm/src/armv7-a/arm_restorefpu.S
@@ -72,7 +72,12 @@ arm_restorefpu:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vldmia.64	r1!, {d0-d15}			/* Restore the full FP context */
+	vldmia.64	r1!, {d16-d31}
+#else
 	vldmia		r1!, {s0-s31}			/* Restore the full FP context */
+#endif
 
 	/* Load the floating point control and status register.   At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.
diff --git a/arch/arm/src/armv7-a/arm_savefpu.S b/arch/arm/src/armv7-a/arm_savefpu.S
index fa19d8331cf..76ae123a3e0 100644
--- a/arch/arm/src/armv7-a/arm_savefpu.S
+++ b/arch/arm/src/armv7-a/arm_savefpu.S
@@ -76,7 +76,12 @@ arm_savefpu:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vstmia.64	r1!, {d0-d15}			/* Save the full FP context */
+	vstmia.64	r1!, {d16-d31}
+#else
 	vstmia		r1!, {s0-s31}			/* Save the full FP context */
+#endif
 
 	/* Store the floating point control and status register.  At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.
diff --git a/arch/arm/src/armv7-a/arm_saveusercontext.S b/arch/arm/src/armv7-a/arm_saveusercontext.S
index 3bce55627e3..9479db73bb1 100644
--- a/arch/arm/src/armv7-a/arm_saveusercontext.S
+++ b/arch/arm/src/armv7-a/arm_saveusercontext.S
@@ -107,7 +107,12 @@ arm_saveusercontext:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vstmia.64	r1!, {d0-d15}		/* Save the full FP context */
+	vstmia.64	r1!, {d16-d31}
+#else
 	vstmia		r1!, {s0-s31}		/* Save the full FP context */
+#endif
 
 	/* Store the floating point control and status register.  At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.
diff --git a/arch/arm/src/armv7-r/arm_fullcontextrestore.S b/arch/arm/src/armv7-r/arm_fullcontextrestore.S
index 93580bf6410..8aefda3eeb4 100644
--- a/arch/arm/src/armv7-r/arm_fullcontextrestore.S
+++ b/arch/arm/src/armv7-r/arm_fullcontextrestore.S
@@ -83,7 +83,12 @@ arm_fullcontextrestore:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vldmia.64	r1!, {d0-d15}			/* Restore the full FP context */
+	vldmia.64	r1!, {d16-d31}
+#else
 	vldmia		r1!, {s0-s31}			/* Restore the full FP context */
+#endif
 
 	/* Load the floating point control and status register.   At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.
diff --git a/arch/arm/src/armv7-r/arm_restorefpu.S b/arch/arm/src/armv7-r/arm_restorefpu.S
index c1c38020d15..3305c0df3ea 100644
--- a/arch/arm/src/armv7-r/arm_restorefpu.S
+++ b/arch/arm/src/armv7-r/arm_restorefpu.S
@@ -78,7 +78,12 @@ arm_restorefpu:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vldmia.64	r1!, {d0-d15}			/* Restore the full FP context */
+	vldmia.64	r1!, {d16-d31}
+#else
 	vldmia		r1!, {s0-s31}			/* Restore the full FP context */
+#endif
 
 	/* Load the floating point control and status register.   At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.
diff --git a/arch/arm/src/armv7-r/arm_savefpu.S b/arch/arm/src/armv7-r/arm_savefpu.S
index 4daa445b5c5..4234e9146bb 100644
--- a/arch/arm/src/armv7-r/arm_savefpu.S
+++ b/arch/arm/src/armv7-r/arm_savefpu.S
@@ -76,7 +76,12 @@ arm_savefpu:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vstmia.64	r1!, {d0-d15}			/* Save the full FP context */
+	vstmia.64	r1!, {d16-d31}
+#else
 	vstmia		r1!, {s0-s31}			/* Save the full FP context */
+#endif
 
 	/* Store the floating point control and status register.  At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.
diff --git a/arch/arm/src/armv7-r/arm_saveusercontext.S b/arch/arm/src/armv7-r/arm_saveusercontext.S
index b4550219868..91e6784b0fd 100644
--- a/arch/arm/src/armv7-r/arm_saveusercontext.S
+++ b/arch/arm/src/armv7-r/arm_saveusercontext.S
@@ -111,7 +111,12 @@ arm_saveusercontext:
 	 * s0, s1, ... in increasing address order.
 	 */
 
+#ifdef CONFIG_ARM_HAVE_FPU_D32
+	vstmia.64	r1!, {d0-d15}		/* Save the full FP context */
+	vstmia.64	r1!, {d16-d31}
+#else
 	vstmia		r1!, {s0-s31}		/* Save the full FP context */
+#endif
 
 	/* Store the floating point control and status register.  At the end of the
 	 * vstmia, r1 will point to the FPCSR storage location.