diff --git a/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h index c27b480002c..49e4294860d 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/****************************************************************************************** * arch/arm/src/kinetis/hardware/kinetis_k28memorymap.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ******************************************************************************************/ #ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H #define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28MEMORYMAP_H -/************************************************************************************ +/****************************************************************************************** * Included Files - ************************************************************************************/ + ******************************************************************************************/ #include @@ -46,11 +46,11 @@ #ifdef KINETIS_K28 -/************************************************************************************ +/****************************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ******************************************************************************************/ -/* Memory Map ***********************************************************************/ +/* Memory Map *****************************************************************************/ /* K28 Family * @@ -89,22 +89,29 @@ # define KINETIS_BME2_BASE 0x44000000 /* Bit Manipulation Engine (BME2) access * to AIPS0 peripheral slots 0-127 and * AIPS1 peripheral slots 0-123 */ -# define KINETIS_FLEXBUS_BASE 0x60000000 /* FlexBus (External Memory - Write-back) */ +# define KINETIS_FLEXBUS_BASE 0x60000000 /* FlexBus + * (External Memory - Write-back) */ # define KINETIS_QSPIRX_BASE 0x67000000 /* QuadSPI0 Rx Buffer */ # define KINETIS_QSPI0_BASE 0x68000000 /* QuadSPI0 (External Memory) */ -# define KINETIS_SDRAMWB_BASE 0x70000000 /* SDRAM (External Memory - Write-back) */ -# define KINETIS_SDRAMWT1_BASE 0x80000000 /* SDRAM (External Memory - Write-through) */ -# define KINETIS_SDRAMWT2_BASE 0x88000000 /* SDRAM (External Memory - Write-through) */ -# define KINETIS_FLEXBUSWT_BASE 0x98000000 /* FlexBus (External Memory - Write-through) */ -# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* FlexBus External Peripheral - Not executable)*/ +# define KINETIS_SDRAMWB_BASE 0x70000000 /* SDRAM + * (External Memory - Write-back) */ +# define KINETIS_SDRAMWT1_BASE 0x80000000 /* SDRAM + * (External Memory - Write-through) */ +# define KINETIS_SDRAMWT2_BASE 0x88000000 /* SDRAM + * (External Memory - Write-through) */ +# define KINETIS_FLEXBUSWT_BASE 0x98000000 /* FlexBus + * (External Memory - Write-through) */ +# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* FlexBus + * External Peripheral - Not executable)*/ # define KINETIS_PERIPH_BASE 0xe0000000 /* Private peripherals */ -/* Peripheral Bridge 0 Memory Map ***************************************************/ +/* Peripheral Bridge 0 Memory Map *********************************************************/ # define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ # define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ # define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ -# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control + * descriptors */ # define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ # define KINETIS_MPU_BASE 0x4000d000 /* System MPU */ # define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */ @@ -147,14 +154,15 @@ # define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ # define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ # define KINETIS_2C2D_BASE 0x40073000 /* 2C2D (Analog comparator (CMP) / - * 6-bit digital-to-analog converter (DAC)) */ + * 6-bit digital-to-analog + * converter (DAC)) */ # define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ # define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ # define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ # define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ # define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */ -/* Peripheral Bridge 1 Memory Map ***************************************************/ +/* Peripheral Bridge 1 Memory Map *********************************************************/ # define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ # define KINETIS_RNGA_BASE 0x400a0000 /* True Random Number Generator (TRNG) */ @@ -173,17 +181,18 @@ # define KINETIS_LPUART3_BASE 0x400c7000 /* LPUART3 */ # define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */ # define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */ -# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit digital-to-analog - * converter (DAC) 0 */ +# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit + * digital-to-analog converter (DAC) 0 */ # define KINETIS_LPUART4_BASE 0x400d6000 /* LPUART4 */ # define KINETIS_QSPI0C_BASE 0x400da000 /* QSPI0 controller */ # define KINETIS_FLEXIO0_BASE 0x400df000 /* FlexIO0 */ # define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */ # define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */ -# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general - * purpose input/output module that shares the - * crossbar switch slave port with the AIPS-Lite - * is accessed at this address. */ +# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit + * general purpose input/output module + * that shares the crossbar switch slave + * port with the AIPS-Lite is accessed at + * this address. */ # define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) # define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ # define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ @@ -191,18 +200,21 @@ # define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ # define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ +/* Private Peripheral Bus (PPB) Memory Map ************************************************/ # define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ # define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ # define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ -# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC and FPU) */ +# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) + * (for NVIC and FPU) */ # define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ # define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ # define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (MTM) */ -# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ +# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic + * Acceleration Unit (MMCAU) */ # define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */ -# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ +# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection + * of debug components */ #else /* The memory map for other parts is defined in other documents and may or may not