diff --git a/arch/risc-v/src/rv32im/riscv_syscall.S b/arch/risc-v/src/rv32im/riscv_syscall.S
index f2a6833bf68..5545fa7ffac 100644
--- a/arch/risc-v/src/rv32im/riscv_syscall.S
+++ b/arch/risc-v/src/rv32im/riscv_syscall.S
@@ -95,7 +95,7 @@ sys_call5:	/* a0 holds the syscall number, arguments in a1, a2, a3, a4 and a5 */
 
 	/* Issue the ECALL opcode to perform a SW interrupt to the OS */
 
-   ecall
+	ecall
 
 	/* The actual interrupt may not a occur for a few more cycles.  Let's
 	 * put a few nop's here in hope that the SW interrupt occurs during