Finally... renamed all CONFIG_DRAM_ settings to CONFIG_RAM_

ChangeLog

@@ -5200,4 +5200,9 @@
 	  Fix a bug (uninitialized register error) that crept in the ARM9
 	  boot-up code several years ago and was cloned into the Cortex-A5
 	  code.  Obviously no one has used the ARM9 NuttX port for years!
+	* Many files:  Finally... I changed the naming to of configuration
+	  variables like CONFIG_DRAM_ to CONFIG_RAM_.  This has bothered
+	  me for a long time since most boards don't have DRAM.  The more
+	  generic RAM naming should not produce so much cognitive dissonance
+	  (2013-7-26).
 

Documentation/NuttxPortingGuide.html

@@ -12,7 +12,7 @@
       <h1><big><font color="#3c34ec">
         <i>NuttX RTOS Porting Guide</i>
       </font></big></h1>
-      <p>Last Updated: June 11, 2013</p>
+      <p>Last Updated: July 26, 2013</p>
     </td>
   </tr>
 </table>
@@ -4367,12 +4367,12 @@ void (*notify)(FAR struct pm_callback_s *cb, enum pm_state_e pmstate);
   Some architectures require a description of the RAM configuration:
 </p>
 <ul>
-  <li><code>CONFIG_DRAM_SIZE</code>:
+  <li><code>CONFIG_RAM_SIZE</code>:
-    Describes the installed DRAM.</li>
+    Describes the primary installed RAM.</li>
-  <li><code>CONFIG_DRAM_START</code>:
+  <li><code>CONFIG_RAM_START</code>:
-    The start address of DRAM (physical)</li>
+    The start address of primary RAM (physical)</li>
-  <li><code>CONFIG_DRAM_VSTART</code>:
+  <li><code>CONFIG_RAM_VSTART</code>:
-    The start address of DRAM (virtual)</li>
+    The start address of primary RAM (virtual).  This is only needed on platforms that support address mapping.</li>
 </ul>
 
 <h2>Build Options</h2>
@@ -5063,14 +5063,14 @@ int ret = sigaction(SIGCHLD, &sa, NULL);
   <li>
     <code>CONFIG_PAGING_NLOCKED</code>:
     This is the number of locked pages in the memory map.
-    The locked address region will then be from <code>CONFIG_DRAM_VSTART</code> through
+    The locked address region will then be from <code>CONFIG_RAM_VSTART</code> through
-    (<code>CONFIG_DRAM_VSTART</code> + <code>CONFIG_PAGING_PAGESIZE</code>*<code>CONFIG_PAGING_NLOCKED</code>)
+    (<code>CONFIG_RAM_VSTART</code> + <code>CONFIG_PAGING_PAGESIZE</code>*<code>CONFIG_PAGING_NLOCKED</code>)
   </li>
   <li>
     <code>CONFIG_PAGING_LOCKED_PBASE</code> and <code>CONFIG_PAGING_LOCKED_VBASE</code>:
     These may be defined to determine the base address of the locked page regions.
-    If neither are defined, the logic will be set the bases to <code>CONFIG_DRAM_START</code>
+    If neither are defined, the logic will be set the bases to <code>CONFIG_RAM_START</code>
-    and <code>CONFIG_DRAM_VSTART</code> (i.e., it assumes that the base address of the locked
+    and <code>CONFIG_RAM_VSTART</code> (i.e., it assumes that the base address of the locked
     region is at the beginning of RAM).
     <b>NOTE</b>:
     In some architectures, it may be necessary to take some memory from the beginning

arch/Kconfig

@@ -194,30 +194,33 @@ config ARCH_CALIBRATION
 		watch to measure the actual delay then adjust BOARD_LOOPSPERMSEC until
 		the actual delay is 100 seconds.
 
-config DRAM_START
+config RAM_START
-	hex "DRAM start physical address"
+	hex "Primary RAM start address (physical)"
 	default 0x0
 	help
-		The physical start address of installed RAM.  Despite the naming,
+		The physical start address of primary installed RAM.  "Primary" RAM
-		this may be SDRAM or SRAM or any other RAM technology that support
+		refers to the RAM that you link program code into.  If program code
-		program execution.
+		does not excecute out of RAM but from FLASH, then you may designate
+		any block of RAM as "primary."
 
-config DRAM_VSTART
+config RAM_VSTART
-	hex "DRAM start virtual address"
+	hex "Primary RAM start address (virtual)"
 	default 0x0
 	depends on ARCH_HAVE_MMU
 	help
-		The virtual start address of installed RAM.  Despite the naming,
+		The virtual start address of installed primary RAM. "Primary" RAM
-		this may be SDRAM or SRAM or any other RAM technology that support
+                refers to the RAM that you link program code into.  If program code
-		program execution.
+                does not excecute out of RAM but from FLASH, then you may designate
+                any block of RAM as "primary."
 
-config DRAM_SIZE
+config RAM_SIZE
-	int "DRAM size"
+	int "Primary RAM size"
 	default 0
 	help
-		The size in bytes of the installed RAM.  Despite the naming,
+		The size in bytes of the installed primary RAM. "Primary" RAM
-		this may be SDRAM or SRAM or any other RAM technology that support
+                refers to the RAM that you link program code into.  If program code
-		program execution.
+                does not excecute out of RAM but from FLASH, then you may designate
+                any block of RAM as "primary."
 
 config ARCH_HAVE_INTERRUPTSTACK
 	bool

arch/arm/src/arm/up_head.S

@@ -128,11 +128,11 @@
    * beginning of RAM.
    */
 
-#  if !defined(CONFIG_DRAM_START) || !defined(CONFIG_DRAM_VSTART)
+#  if !defined(CONFIG_RAM_START) || !defined(CONFIG_RAM_VSTART)
-#    error "CONFIG_DRAM_START or CONFIG_DRAM_VSTART is not defined"
+#    error "CONFIG_RAM_START or CONFIG_RAM_VSTART is not defined"
 #  endif
 
-#  if CONFIG_DRAM_START == CONFIG_DRAM_VSTART
+#  if CONFIG_RAM_START == CONFIG_RAM_VSTART
 #    define CONFIG_IDENTITY_TEXTMAP 1
 #  endif
 
@@ -162,13 +162,13 @@
  ****************************************************************************/
 
 /* RX_NSECTIONS determines the number of 1Mb sections to map for the
- * Read/eXecute address region.  This is based on CONFIG_DRAM_SIZE.  For most
+ * Read/eXecute address region.  This is based on CONFIG_RAM_SIZE.  For most
- * ARM9 architectures, CONFIG_DRAM_SIZE describes the size of installed SDRAM.
+ * ARM9 architectures, CONFIG_RAM_SIZE describes the size of installed SDRAM.
  * But for other architectures, this might refer to the size of FLASH or
  * SRAM regions. (bad choice of naming).
  */
 
-#define RX_NSECTIONS ((CONFIG_DRAM_SIZE+0x000fffff) >> 20)
+#define RX_NSECTIONS ((CONFIG_RAM_SIZE+0x000fffff) >> 20)
 
 /****************************************************************************
  * Assembly Macros

arch/arm/src/armv7-a/arm_head.S

@@ -129,11 +129,11 @@
    * beginning of RAM.
    */
 
-#  if !defined(CONFIG_DRAM_START) || !defined(CONFIG_DRAM_VSTART)
+#  if !defined(CONFIG_RAM_START) || !defined(CONFIG_RAM_VSTART)
-#    error "CONFIG_DRAM_START or CONFIG_DRAM_VSTART is not defined"
+#    error "CONFIG_RAM_START or CONFIG_RAM_VSTART is not defined"
 #  endif
 
-#  if CONFIG_DRAM_START == CONFIG_DRAM_VSTART
+#  if CONFIG_RAM_START == CONFIG_RAM_VSTART
 #    define CONFIG_IDENTITY_TEXTMAP 1
 #  endif
 
@@ -163,13 +163,10 @@
  ****************************************************************************/
 
 /* RX_NSECTIONS determines the number of 1Mb sections to map for the
- * Read/eXecute address region.  This is based on CONFIG_DRAM_SIZE.  For most
+ * Read/eXecute address region.  This is based on CONFIG_RAM_SIZE.
- * ARMv7-A architectures, CONFIG_DRAM_SIZE describes the size of installed SDRAM.
- * But for other architectures, this might refer to the size of FLASH or
- * SRAM regions. (bad choice of naming).
  */
 
-#define RX_NSECTIONS ((CONFIG_DRAM_SIZE+0x000fffff) >> 20)
+#define RX_NSECTIONS ((CONFIG_RAM_SIZE+0x000fffff) >> 20)
 
 /****************************************************************************
  * Assembly Macros

arch/arm/src/common/up_allocateheap.c

@@ -111,10 +111,10 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Return the user-space heap settings */
 
@@ -127,7 +127,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size  = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size  = CONFIG_RAM_END - g_idle_topstack;
 #endif
 }
 
@@ -151,10 +151,10 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Return the kernel heap settings (i.e., the part of the heap region
    * that was not dedicated to the user heap).

arch/arm/src/common/up_internal.h

@@ -194,7 +194,7 @@ extern volatile uint32_t *current_regs;
 /* This is the beginning of heap as provided from up_head.S.
  * This is the first address in DRAM after the loaded
  * program+bss+idle stack.  The end of the heap is
- * CONFIG_DRAM_END
+ * CONFIG_RAM_END
  */
 
 extern const uint32_t g_idle_topstack;

arch/arm/src/dm320/dm320_allocateheap.c

@@ -86,5 +86,5 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size  = (DM320_SDRAM_VADDR + CONFIG_DRAM_SIZE) - g_idle_topstack;
+  *heap_size  = (DM320_SDRAM_VADDR + CONFIG_RAM_SIZE) - g_idle_topstack;
 }

arch/arm/src/dm320/dm320_memorymap.h

@@ -137,8 +137,8 @@
 
 /* DM320 Virtual Memory Map */
 
-#if CONFIG_DRAM_VSTART != 0x00000000
+#if CONFIG_RAM_VSTART != 0x00000000
-# error "Invalid setting for CONFIG_DRAM_VSTART"
+# error "Invalid setting for CONFIG_RAM_VSTART"
 #endif
 
 /* Section/Region Name               Virt Address  End        Size  CW */

arch/arm/src/dm320/dm320_restart.S

@@ -121,7 +121,7 @@ up_phyrestart:
 
 	.type	.LCphysrestart, %object
 .LCphysrestart:
-	.long	(up_phyrestart - CONFIG_DRAM_VSTART - CONFIG_DRAM_START)
+	.long	(up_phyrestart - CONFIG_RAM_VSTART - CONFIG_RAM_START)
 .LCbtldrentry:
 	.long	DM320_EXT_MEM_PADDR
 

arch/arm/src/imx/imx_allocateheap.c

@@ -87,7 +87,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size  = (IMX_SDRAM_VSECTION + CONFIG_DRAM_SIZE) - g_idle_topstack;
+  *heap_size  = (IMX_SDRAM_VSECTION + CONFIG_RAM_SIZE) - g_idle_topstack;
 }
 
 /****************************************************************************
@@ -107,8 +107,8 @@ void up_addregion(void)
    */
 
 #if !defined(CONFIG_BOOT_RUNFROMFLASH) && !defined(CONFIG_BOOT_COPYTORAM)
-#  if (CONFIG_DRAM_NUTTXENTRY & 0xffff0000) != CONFIG_DRAM_VSTART
+#  if (CONFIG_DRAM_NUTTXENTRY & 0xffff0000) != CONFIG_RAM_VSTART
-  uint32_t start = CONFIG_DRAM_VSTART + 0x1000;
+  uint32_t start = CONFIG_RAM_VSTART + 0x1000;
   uint32_t end   = (CONFIG_DRAM_NUTTXENTRY & 0xffff0000);
   kmm_addregion((FAR void*)start, end - start);
 #  endif

arch/arm/src/imx/imx_memorymap.h

@@ -65,7 +65,7 @@
 
 /* Mapped sections */
 #define IMX_PERIPHERALS_NSECTIONS 1          /*  1Mb  1 section                     */
-#define IMX_SDRAM0_NSECTIONS      16         /* 16Mb Based on CONFIG_DRAM_SIZE      */
+#define IMX_SDRAM0_NSECTIONS      16         /* 16Mb Based on CONFIG_RAM_SIZE      */
 #define IMX_SDRAM1_NSECTIONS      0          /* 64Mb (Not mapped)                   */
 #define IMX_FLASH_NSECTIONS       32         /* 64Mb Based on CONFIG_FLASH_SIZE     */
 #define IMX_CS1_NSECTIONS         16         /* 16Mb                                */
@@ -116,11 +116,11 @@
 #ifdef CONFIG_BOOT_RUNFROMFLASH
    /* Use the identity mapping */
 
-#  define IMX_SDRAM_VSECTION      0x08000000 /* -(+CONFIG_DRAM_SIZE)                */
+#  define IMX_SDRAM_VSECTION      0x08000000 /* -(+CONFIG_RAM_SIZE)                 */
 #else
    /* Map SDRAM to address zero */
 
-#  define IMX_SDRAM_VSECTION      0x00000000 /* -(+CONFIG_DRAM_SIZE)                */
+#  define IMX_SDRAM_VSECTION      0x00000000 /* -(+CONFIG_RAM_SIZE)                 */
 #endif
 
 /* We use a identity mapping for other regions */

arch/arm/src/kinetis/kinetis_allocateheap.c

@@ -112,21 +112,21 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the user-space heap settings */
 
@@ -143,7 +143,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size  = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size  = CONFIG_RAM_END - g_idle_topstack;
 #endif
 }
 
@@ -166,21 +166,21 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the kernel heap settings (i.e., the part of the heap region
    * that was not dedicated to the user heap).

arch/arm/src/lm/lm_allocateheap.c

@@ -112,21 +112,21 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the user-space heap settings */
 
@@ -143,7 +143,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size  = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size  = CONFIG_RAM_END - g_idle_topstack;
 #endif
 }
 
@@ -166,21 +166,21 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the kernel heap settings (i.e., the part of the heap region
    * that was not dedicated to the user heap).

arch/arm/src/lpc17xx/lpc17_allocateheap.c

@@ -63,24 +63,24 @@
 /* Configuration ************************************************************/
 /* The configured RAM start address must be the beginning of CPU SRAM */
 
-#if CONFIG_DRAM_START != LPC17_SRAM_BASE
+#if CONFIG_RAM_START != LPC17_SRAM_BASE
-#  warning "CONFIG_DRAM_START is not at LPC17_SRAM_BASE"
+#  warning "CONFIG_RAM_START is not at LPC17_SRAM_BASE"
-#  undef CONFIG_DRAM_START
+#  undef CONFIG_RAM_START
-#  undef CONFIG_DRAM_END
+#  undef CONFIG_RAM_END
-#  define CONFIG_DRAM_START LPC17_SRAM_BASE
+#  define CONFIG_RAM_START LPC17_SRAM_BASE
-#  define CONFIG_DRAM_END  (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
+#  define CONFIG_RAM_END  (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
 #endif
 
 /* The configured RAM size must be less then or equal to the CPU SRAM size */
 
-#if CONFIG_DRAM_SIZE > LPC17_CPUSRAM_SIZE
+#if CONFIG_RAM_SIZE > LPC17_CPUSRAM_SIZE
-#  warning "CONFIG_DRAM_SIZE is larger than the size of CPU SRAM"
+#  warning "CONFIG_RAM_SIZE is larger than the size of CPU SRAM"
-#  undef CONFIG_DRAM_SIZE
+#  undef CONFIG_RAM_SIZE
-#  undef CONFIG_DRAM_END
+#  undef CONFIG_RAM_END
-#  define CONFIG_DRAM_SIZE LPC17_CPUSRAM_SIZE
+#  define CONFIG_RAM_SIZE LPC17_CPUSRAM_SIZE
-#  define CONFIG_DRAM_END (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
+#  define CONFIG_RAM_END (LPC17_SRAM_BASE+LPC17_CPUSRAM_SIZE)
-#elif CONFIG_DRAM_SIZE < LPC17_CPUSRAM_SIZE
+#elif CONFIG_RAM_SIZE < LPC17_CPUSRAM_SIZE
-#  warning "CONFIG_DRAM_END is before end of CPU SRAM... not all of CPU SRAM used"
+#  warning "CONFIG_RAM_END is before end of CPU SRAM... not all of CPU SRAM used"
 #endif
 
 /* Figure out how much heap be have in AHB SRAM (if any).  Complications:
@@ -222,21 +222,21 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the user-space heap settings */
 
@@ -253,7 +253,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size  = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size  = CONFIG_RAM_END - g_idle_topstack;
 #endif
 }
 
@@ -276,21 +276,21 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the kernel heap settings (i.e., the part of the heap region
    * that was not dedicated to the user heap).

arch/arm/src/lpc43xx/lpc43_allocateheap.c

@@ -133,10 +133,10 @@
  *
  * The config.h file will define only:
  *
- *    CONFIG_DRAM_START = The start of the data RAM region which may be
+ *    CONFIG_RAM_START = The start of the data RAM region which may be
  *      either local SRAM bank 0 (Configuration A) or 1 (Configuration B).
- *    CONFIG_DRAM_START = The size of the data RAM region.
+ *    CONFIG_RAM_START = The size of the data RAM region.
- *    CONFIG_DRAM_END   = The sum of the above
+ *    CONFIG_RAM_END   = The sum of the above
  */
 
 /* Check for Configuration A. */
@@ -144,16 +144,16 @@
 #ifndef CONFIG_LPC43_BOOT_SRAM
 
 /* Configuration A */
-/* CONFIG_DRAM_START should be set to the base of AHB SRAM, local 0. */
+/* CONFIG_RAM_START should be set to the base of AHB SRAM, local 0. */
 
-#  if CONFIG_DRAM_START != LPC43_LOCSRAM_BANK0_BASE
+#  if CONFIG_RAM_START != LPC43_LOCSRAM_BANK0_BASE
-#    error "CONFIG_DRAM_START must be set to the base address of AHB SRAM Bank 0"
+#    error "CONFIG_RAM_START must be set to the base address of AHB SRAM Bank 0"
 #  endif
 
 /* The configured RAM size should be equal to the size of local SRAM Bank 0 */
 
-#  if CONFIG_DRAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE
+#  if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK0_SIZE
-#    error "CONFIG_DRAM_SIZE must be set to size of AHB SRAM Bank 0"
+#    error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 0"
 #  endif
 
 /* Now we can assign all of the memory regions for configuration A */
@@ -167,16 +167,16 @@
 #else
 
 /* Configuration B */
-/* CONFIG_DRAM_START should be set to the base of local SRAM, bank 1. */
+/* CONFIG_RAM_START should be set to the base of local SRAM, bank 1. */
 
-#  if CONFIG_DRAM_START != LPC43_LOCSRAM_BANK1_BASE
+#  if CONFIG_RAM_START != LPC43_LOCSRAM_BANK1_BASE
-#    error "CONFIG_DRAM_START must be set to the base address of AHB SRAM Bank 0"
+#    error "CONFIG_RAM_START must be set to the base address of AHB SRAM Bank 0"
 #  endif
 
 /* The configured RAM size should be equal to the size of local SRAM Bank 1 */
 
-#  if CONFIG_DRAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE
+#  if CONFIG_RAM_SIZE != LPC43_LOCSRAM_BANK1_SIZE
-#    error "CONFIG_DRAM_SIZE must be set to size of AHB SRAM Bank 0"
+#    error "CONFIG_RAM_SIZE must be set to size of AHB SRAM Bank 0"
 #  endif
 
 /* Now we can assign all of the memory regions for configuration B */
@@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size = CONFIG_RAM_END - g_idle_topstack;
 }
 
 /************************************************************************

arch/arm/src/sam34/sam_allocateheap.c

@@ -149,12 +149,12 @@
 
 /* Check common SRAM0 configuration */
 
-#if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE)
+#if CONFIG_RAM_END > (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE)
-#  error "CONFIG_DRAM_END is beyond the end of SRAM0"
+#  error "CONFIG_RAM_END is beyond the end of SRAM0"
-#  undef CONFIG_DRAM_END
+#  undef CONFIG_RAM_END
-#  define CONFIG_DRAM_END (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE)
+#  define CONFIG_RAM_END (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE)
-#elif CONFIG_DRAM_END < (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE)
+#elif CONFIG_RAM_END < (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE)
-#  warning "CONFIG_DRAM_END is before end of SRAM0... not all of SRAM0 used"
+#  warning "CONFIG_RAM_END is before end of SRAM0... not all of SRAM0 used"
 #endif
 
 /****************************************************************************
@@ -211,21 +211,21 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the user-space heap settings */
 
@@ -242,7 +242,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size  = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size  = CONFIG_RAM_END - g_idle_topstack;
 #endif
 }
 
@@ -265,21 +265,21 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
    */
 
   uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
-  size_t    usize = CONFIG_DRAM_END - ubase;
+  size_t    usize = CONFIG_RAM_END - ubase;
   int       log2;
 
-  DEBUGASSERT(ubase < (uintptr_t)CONFIG_DRAM_END);
+  DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END);
 
   /* Adjust that size to account for MPU alignment requirements.
-   * NOTE that there is an implicit assumption that the CONFIG_DRAM_END
+   * NOTE that there is an implicit assumption that the CONFIG_RAM_END
    * is aligned to the MPU requirement.
    */
 
   log2  = (int)mpu_log2regionfloor(usize);
-  DEBUGASSERT((CONFIG_DRAM_END & ((1 << log2) - 1)) == 0);
+  DEBUGASSERT((CONFIG_RAM_END & ((1 << log2) - 1)) == 0);
 
   usize = (1 << log2);
-  ubase = CONFIG_DRAM_END - usize;
+  ubase = CONFIG_RAM_END - usize;
 
   /* Return the kernel heap settings (i.e., the part of the heap region
    * that was not dedicated to the user heap).

arch/arm/src/sama5/Kconfig

@@ -524,7 +524,7 @@ config SAMA5_ISRAM_HEAP
 
 		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM INTERNAL SRAM!!**
 		In this case, the remaining ISRAM will automatically be added to the
-		heap (using DRAM_END).
+		heap (using RAM_END).
 
 config SAMA5_DDRCS_HEAP
 	bool "Include DDR-SDRAM in heap"
@@ -538,7 +538,7 @@ config SAMA5_DDRCS_HEAP
 
 		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM SDRAM!!**
 		In this case, the remaining SDRAM will automatically be added to the
-		heap (using DRAM_END)
+		heap (using RAM_END)
 
 config SAMA5_EBICS0_HEAP
 	bool "Include SRAM/PSRAM in heap"
@@ -552,7 +552,7 @@ config SAMA5_EBICS0_HEAP
 
 		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS0 SRAM!!**
 		In this case, the remaining SRAM will automatically be added to the
-		heap (using DRAM_END).
+		heap (using RAM_END).
 
 config SAMA5_EBICS1_HEAP
 	bool "Include SRAM/PSRAM in heap"
@@ -566,7 +566,7 @@ config SAMA5_EBICS1_HEAP
 
 		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS1 SRAM!!**
 		In this case, the remaining SRAM will automatically be added to the
-		heap (using DRAM_END).
+		heap (using RAM_END).
 
 config SAMA5_EBICS2_HEAP
 	bool "Include SRAM/PSRAM in heap"
@@ -580,7 +580,7 @@ config SAMA5_EBICS2_HEAP
 
 		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS2 SRAM!!**
 		In this case, the remaining SRAM will automatically be added to the
-		heap (using DRAM_END).
+		heap (using RAM_END).
 
 config SAMA5_EBICS3_HEAP
 	bool "Include SRAM/PSRAM in heap"
@@ -591,7 +591,7 @@ config SAMA5_EBICS3_HEAP
 
 		*** DO NOT SELECT THIS OPTION IF YOU ARE EXECUTING FROM CS3 SRAM!!**
 		In this case, the remaining SRAM will automatically be added to the
-		heap (using DRAM_END).
+		heap (using RAM_END).
 
 endmenu # Heap Configuration
 endif # ARCH_CHIP_SAMA5

arch/arm/src/sama5/sam_allocateheap.c

@@ -62,7 +62,7 @@
  *
  * We cannot add the region if it is if we are executing from it!  In that
  * case, the remainder of the memory will automatically be added to the heap
- * based on g_idle_topstack and CONFIG_DRAM_END
+ * based on g_idle_topstack and CONFIG_RAM_END
  */
 
 #if defined(CONFIG_SAMA5_BOOT_ISRAM)
@@ -108,17 +108,17 @@
  *
  * - Internal SRAM is the "primary" RAM region in the case where we are
  *   executing from internal SRAM.  In that case, g_idle_topstack points
- *   into internal SRAM and CONFIG_DRAM_END is the end of internal SRAM.
+ *   into internal SRAM and CONFIG_RAM_END is the end of internal SRAM.
  */
 
 #if defined(CONFIG_BOOT_RUNFROMISRAM) && defined(PGTABLE_IN_HIGHSRAM) && \
   (!defined(CONFIG_NUTTX_KERNEL)      || !defined(CONFIG_MM_KERNEL_HEAP))
-#  define ADJUSTED_RAM_END (CONFIG_DRAM_END-PGTABLE_SIZE)
+#  define ADJUSTED_RAM_END (CONFIG_RAM_END-PGTABLE_SIZE)
 
 /* Otherwise, the heap extends to the end of the primary RAM */
 
 #else
-#  define ADJUSTED_RAM_END CONFIG_DRAM_END
+#  define ADJUSTED_RAM_END CONFIG_RAM_END
 #endif
 
 /****************************************************************************

arch/arm/src/stm32/stm32_allocateheap.c

@@ -63,7 +63,7 @@
  * following definitions must be provided to specify the size and
  * location of internal(system) SRAM:
  *
- * CONFIG_DRAM_END            : End address (+1) of SRAM (F1 family only, the
+ * CONFIG_RAM_END            : End address (+1) of SRAM (F1 family only, the
  *                            : F4 family uses the a priori end of SRAM)
  *
  * The F4 family also contains internal CCM SRAM.  This SRAM is different
@@ -93,14 +93,14 @@
 #endif
 
 /* The STM32L15xxx family has only internal SRAM.  The heap is in one contiguous
- * block starting at g_idle_topstack and extending through CONFIG_DRAM_END.
+ * block starting at g_idle_topstack and extending through CONFIG_RAM_END.
  */
 
 #if defined(CONFIG_STM32_STM32L15XX)
 
    /* Set the end of system SRAM */
 
-#  define SRAM1_END CONFIG_DRAM_END
+#  define SRAM1_END CONFIG_RAM_END
 
    /* There is no FSMC (Other EnergyLite STM32's do have an FSMC, but not the STM32L15X */
 
@@ -118,7 +118,7 @@
 #  endif
 
 /* For the STM312F10xxx family, all internal SRAM is in one contiguous block
- * starting at g_idle_topstack and extending through CONFIG_DRAM_END (my apologies
+ * starting at g_idle_topstack and extending through CONFIG_RAM_END (my apologies
  * for the bad naming).  In addition, external FSMC SRAM may be available.
  */
 
@@ -126,7 +126,7 @@
 
    /* Set the end of system SRAM */
 
-#  define SRAM1_END CONFIG_DRAM_END
+#  define SRAM1_END CONFIG_RAM_END
 
    /* Check if external FSMC SRAM is provided */
 
@@ -160,7 +160,7 @@
 
    /* Set the end of system SRAM */
 
-#  define SRAM1_END CONFIG_DRAM_END
+#  define SRAM1_END CONFIG_RAM_END
 
    /* Set the range of CCM SRAM as well (although we may not use it) */
 

arch/avr/src/avr/avr_internal.h

@@ -78,7 +78,7 @@ extern volatile uint8_t *current_regs;
 
 /* This is the beginning of heap as provided from up_head.S. This is the first
  * address in DRAM after the loaded program+bss+idle stack.  The end of the
- * heap is CONFIG_DRAM_END
+ * heap is CONFIG_RAM_END
  */
 
 extern uint16_t g_idle_topstack;

arch/avr/src/avr32/avr32_internal.h

@@ -76,7 +76,7 @@ extern volatile uint32_t *current_regs;
 
 /* This is the beginning of heap as provided from up_head.S. This is the first
  * address in DRAM after the loaded program+bss+idle stack.  The end of the
- * heap is CONFIG_DRAM_END
+ * heap is CONFIG_RAM_END
  */
 
 extern uint32_t g_idle_topstack;

arch/avr/src/common/up_allocateheap.c

@@ -83,5 +83,5 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size = CONFIG_RAM_END - g_idle_topstack;
 }

arch/hc/src/common/up_allocateheap.c

@@ -82,5 +82,5 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size = CONFIG_RAM_END - g_idle_topstack;
 }

arch/hc/src/common/up_internal.h

@@ -138,7 +138,7 @@ extern volatile uint8_t *current_regs;
 
 /* This is the beginning of heap as provided from processor-specific logic.
  * This is the first address in RAM after the loaded program+bss+idle stack.
- * The end of the heap is CONFIG_DRAM_END
+ * The end of the heap is CONFIG_RAM_END
  */
 
 extern uint16_t g_idle_topstack;

arch/mips/src/common/up_allocateheap.c

@@ -83,5 +83,5 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size = CONFIG_RAM_END - g_idle_topstack;
 }

arch/mips/src/common/up_internal.h

@@ -135,7 +135,7 @@ extern volatile uint32_t *current_regs;
 
 /* This is the beginning of heap as provided from up_head.S. This is the
  * first address in DRAM after the loaded program+bss+idle stack.  The end
- * of the heap is CONFIG_DRAM_END
+ * of the heap is CONFIG_RAM_END
  */
 
 extern uint32_t g_idle_topstack;

arch/sh/src/common/up_allocateheap.c

@@ -82,5 +82,5 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size = CONFIG_RAM_END - g_idle_topstack;
 }

arch/sh/src/common/up_internal.h

@@ -137,7 +137,7 @@ extern volatile uint32_t *current_regs;
 /* This is the beginning of heap as provided from up_head.S.
  * This is the first address in DRAM after the loaded
  * program+bss+idle stack.  The end of the heap is
- * CONFIG_DRAM_END
+ * CONFIG_RAM_END
  */
 
 extern uint32_t g_idle_topstack;

arch/x86/src/common/up_allocateheap.c

@@ -83,5 +83,5 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
 {
   up_ledon(LED_HEAPALLOCATE);
   *heap_start = (FAR void*)g_idle_topstack;
-  *heap_size = CONFIG_DRAM_END - g_idle_topstack;
+  *heap_size = CONFIG_RAM_END - g_idle_topstack;
 }

arch/x86/src/common/up_internal.h

@@ -137,7 +137,7 @@ extern volatile uint32_t *current_regs;
 
 /* This is the beginning of heap as provided from up_head.S. This is the first
  * address in DRAM after the loaded program+bss+idle stack.  The end of the
- * heap is CONFIG_DRAM_END
+ * heap is CONFIG_RAM_END
  */
 
 extern uint32_t g_idle_topstack;

arch/z80/src/Makefile.sdccl

@@ -122,7 +122,7 @@ $(TOPDIR)/lib/$(SDCCLIB): $(SDCC_LIBDIR)/$(SDCCLIB)
 # IDLE thread stack
 
 asm_mem.h:
-	@echo "	CONFIG_STACK_END == ($(CONFIG_DRAM_SIZE) - 1)" >> asm_mem.h
+	@echo "	CONFIG_STACK_END == ($(CONFIG_RAM_SIZE) - 1)" >> asm_mem.h
 	@echo "	CONFIG_STACK_BASE == (CONFIG_STACK_END - $(CONFIG_IDLETHREAD_STACKSIZE))" >> asm_mem.h
 
 # Combine all objects in this directory into a library

arch/z80/src/Makefile.sdccw

@@ -122,7 +122,7 @@ $(TOPDIR)\lib\$(SDCCLIB): $(SDCC_LIBDIR)\$(SDCCLIB)
 # IDLE thread stack
 
 asm_mem.h:
-	@echo 	CONFIG_STACK_END == ($(CONFIG_DRAM_SIZE) - 1)>>asm_mem.h
+	@echo 	CONFIG_STACK_END == ($(CONFIG_RAM_SIZE) - 1)>>asm_mem.h
 	@echo 	CONFIG_STACK_BASE == (CONFIG_STACK_END - $(CONFIG_IDLETHREAD_STACKSIZE))>>asm_mem.h
 
 # Combine all objects in this directory into a library

arch/z80/src/z180/up_mem.h

@@ -48,7 +48,7 @@
 
 /* Locate the IDLE thread stack at the end of RAM. */
 
-#define CONFIG_STACK_END   CONFIG_DRAM_SIZE
+#define CONFIG_STACK_END   CONFIG_RAM_SIZE
 #define CONFIG_STACK_BASE  (CONFIG_STACK_END - CONFIG_IDLETHREAD_STACKSIZE)
 
 /* The heap then extends from the linker determined beginning of the heap (s__HEAP).

arch/z80/src/z80/up_mem.h

@@ -48,7 +48,7 @@
 
 /* Locate the IDLE thread stack at the end of RAM. */
 
-#define CONFIG_STACK_END   CONFIG_DRAM_SIZE
+#define CONFIG_STACK_END   CONFIG_RAM_SIZE
 #define CONFIG_STACK_BASE  (CONFIG_STACK_END - CONFIG_IDLETHREAD_STACKSIZE)
 
 /* The heap then extends from the linker determined beginning of the heap (s__HEAP).

configs/README.txt

@@ -188,9 +188,9 @@ architecture/board-specific settings).
 
   Some architectures require a description of the RAM configuration:
 
-    CONFIG_DRAM_SIZE - Describes the installed DRAM.
+    CONFIG_RAM_SIZE - Describes the installed DRAM.
-    CONFIG_DRAM_START - The start address of DRAM (physical)
+    CONFIG_RAM_START - The start address of DRAM (physical)
-    CONFIG_DRAM_VSTART - The start address of DRAM (virtual)
+    CONFIG_RAM_VSTART - The start address of DRAM (virtual)
 
   General build options:
 
@@ -630,12 +630,12 @@ architecture/board-specific settings).
       be a value supported by the processor's memory management unit.
     CONFIG_PAGING_NLOCKED - This is the number of locked pages in the
       memory map.  The locked address region will then be from
-      CONFIG_DRAM_VSTART through (CONFIG_DRAM_VSTART +
+      CONFIG_RAM_VSTART through (CONFIG_RAM_VSTART +
       CONFIG_PAGING_PAGESIZE*CONFIG_PAGING_NLOCKED)
     CONFIG_PAGING_LOCKED_PBASE and CONFIG_PAGING_LOCKED_VBASE - These
       may be defined to determine the base address of the locked page
       regions.  If neither are defined, the logic will be set the bases
-      to CONFIG_DRAM_START and CONFIG_DRAM_VSTART (i.e., it assumes
+      to CONFIG_RAM_START and CONFIG_RAM_VSTART (i.e., it assumes
       that the base address of the locked region is at the beginning
       of RAM).
       NOTE:  In some architectures, it may be necessary to take some

configs/amber/README.txt

@@ -411,13 +411,13 @@ Amber Web Server Configuration Options
     CONFIG_ENDIAN_BIG - define if big endian (default is little
        endian)
 
-    CONFIG_DRAM_SIZE - Describes the installed DRAM.  One of:
+    CONFIG_RAM_SIZE - Describes the installed DRAM.  One of:
 
-       CONFIG_DRAM_SIZE=(8*1024) - (8Kb)
+       CONFIG_RAM_SIZE=(8*1024) - (8Kb)
 
-    CONFIG_DRAM_START - The start address of installed SRAM
+    CONFIG_RAM_START - The start address of installed SRAM
 
-       CONFIG_DRAM_START=0x800100
+       CONFIG_RAM_START=0x800100
 
     CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
        have LEDs

configs/amber/hello/defconfig

@@ -43,8 +43,8 @@ CONFIG_ARCH_CHIP_ATMEGA128=y
 CONFIG_ARCH_BOARD="amber"
 CONFIG_ARCH_BOARD_AMBER=y
 CONFIG_BOARD_LOOPSPERMSEC=800
-CONFIG_DRAM_SIZE=4096
+CONFIG_RAM_SIZE=4096
-CONFIG_DRAM_START=0x800100
+CONFIG_RAM_START=0x800100
 CONFIG_ARCH_NOINTC=y
 CONFIG_ARCH_IRQPRIO=n
 CONFIG_ARCH_INTERRUPTSTACK=0

configs/arduino-due/README.txt

@@ -744,13 +744,13 @@ Arduino DUE-specific Configuration Options
   CONFIG_ENDIAN_BIG - define if big endian (default is little
   endian)
 
-  CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
+  CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
 
-    CONFIG_DRAM_SIZE=0x00008000 (32Kb)
+    CONFIG_RAM_SIZE=0x00008000 (32Kb)
 
-  CONFIG_DRAM_START - The start address of installed DRAM
+  CONFIG_RAM_START - The start address of installed DRAM
 
-    CONFIG_DRAM_START=0x20000000
+    CONFIG_RAM_START=0x20000000
 
   CONFIG_ARCH_IRQPRIO - The SAM3UF103Z supports interrupt prioritization
 

configs/arduino-due/nsh/defconfig

@@ -214,8 +214,8 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
 #
 CONFIG_BOARD_LOOPSPERMSEC=6965
 # CONFIG_ARCH_CALIBRATION is not set
-CONFIG_DRAM_START=0x20000000
+CONFIG_RAM_START=0x20000000
-CONFIG_DRAM_SIZE=65536
+CONFIG_RAM_SIZE=65536
 CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
 CONFIG_ARCH_INTERRUPTSTACK=0
 

configs/arduino-due/ostest/defconfig

@@ -214,8 +214,8 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
 #
 CONFIG_BOARD_LOOPSPERMSEC=6965
 # CONFIG_ARCH_CALIBRATION is not set
-CONFIG_DRAM_START=0x20000000
+CONFIG_RAM_START=0x20000000
-CONFIG_DRAM_SIZE=65536
+CONFIG_RAM_SIZE=65536
 CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
 CONFIG_ARCH_INTERRUPTSTACK=0
 

configs/avr32dev1/README.txt

@@ -369,13 +369,13 @@ AVR32DEV1 Configuration Options
     CONFIG_ENDIAN_BIG - define if big endian (default is little
        endian)
 
-    CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
+    CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
 
-       CONFIG_DRAM_SIZE=0x00010000 (64Kb)
+       CONFIG_RAM_SIZE=0x00010000 (64Kb)
 
-    CONFIG_DRAM_START - The start address of installed DRAM
+    CONFIG_RAM_START - The start address of installed DRAM
 
-       CONFIG_DRAM_START=0x20000000
+       CONFIG_RAM_START=0x20000000
 
     CONFIG_ARCH_IRQPRIO - The AT32UC3B0256 supports interrupt prioritization
 

configs/avr32dev1/nsh/defconfig

@@ -44,8 +44,8 @@ CONFIG_ENDIAN_BIG=y
 CONFIG_ARCH_BOARD="avr32dev1"
 CONFIG_ARCH_BOARD_AVR32DEV1=y
 CONFIG_BOARD_LOOPSPERMSEC=1140
-CONFIG_DRAM_SIZE=32768
+CONFIG_RAM_SIZE=32768
-CONFIG_DRAM_START=0x00000000
+CONFIG_RAM_START=0x00000000
 CONFIG_ARCH_NOINTC=y
 CONFIG_ARCH_IRQPRIO=y
 CONFIG_ARCH_INTERRUPTSTACK=0

configs/avr32dev1/ostest/defconfig

@@ -44,8 +44,8 @@ CONFIG_ENDIAN_BIG=y
 CONFIG_ARCH_BOARD="avr32dev1"
 CONFIG_ARCH_BOARD_AVR32DEV1=y
 CONFIG_BOARD_LOOPSPERMSEC=1140
-CONFIG_DRAM_SIZE=32768
+CONFIG_RAM_SIZE=32768
-CONFIG_DRAM_START=0x00000000
+CONFIG_RAM_START=0x00000000
 CONFIG_ARCH_NOINTC=y
 CONFIG_ARCH_IRQPRIO=y
 CONFIG_ARCH_INTERRUPTSTACK=0

configs/c5471evm/httpd/defconfig

@@ -48,8 +48,8 @@ CONFIG_ARCH_LEDS=y
 CONFIG_ARCH_INTERRUPTSTACK=0
 CONFIG_ARCH_STACKDUMP=y
 
-CONFIG_DRAM_START=0
+CONFIG_RAM_START=0
-CONFIG_DRAM_SIZE=285212672
+CONFIG_RAM_SIZE=285212672
 
 #
 # C5471 specific device driver settings

configs/c5471evm/nettest/defconfig

@@ -48,8 +48,8 @@ CONFIG_ARCH_LEDS=y
 CONFIG_ARCH_INTERRUPTSTACK=0
 CONFIG_ARCH_STACKDUMP=y
 
-CONFIG_DRAM_START=0
+CONFIG_RAM_START=0
-CONFIG_DRAM_SIZE=285212672
+CONFIG_RAM_SIZE=285212672
 
 #
 # General build options

configs/c5471evm/nsh/defconfig

@@ -48,8 +48,8 @@ CONFIG_ARCH_LEDS=y
 CONFIG_ARCH_INTERRUPTSTACK=0
 CONFIG_ARCH_STACKDUMP=y
 
-CONFIG_DRAM_START=0
+CONFIG_RAM_START=0
-CONFIG_DRAM_SIZE=285212672
+CONFIG_RAM_SIZE=285212672
 
 #
 # C5471 specific device driver settings

configs/c5471evm/ostest/defconfig

@@ -48,8 +48,8 @@ CONFIG_ARCH_LEDS=y
 CONFIG_ARCH_INTERRUPTSTACK=0
 CONFIG_ARCH_STACKDUMP=y
 
-CONFIG_DRAM_START=0
+CONFIG_RAM_START=0
-CONFIG_DRAM_SIZE=285212672
+CONFIG_RAM_SIZE=285212672
 
 #
 # C5471 specific device driver settings

configs/cloudctrl/README.txt

@@ -493,13 +493,13 @@ Cloudctrl-specific Configuration Options
     CONFIG_ENDIAN_BIG - define if big endian (default is little
        endian)
 
-    CONFIG_DRAM_SIZE - Describes the installed DRAM (SRAM in this case):
+    CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
 
-       CONFIG_DRAM_SIZE=0x00010000 (64Kb)
+       CONFIG_RAM_SIZE=0x00010000 (64Kb)
 
-    CONFIG_DRAM_START - The start address of installed DRAM
+    CONFIG_RAM_START - The start address of installed DRAM
 
-       CONFIG_DRAM_START=0x20000000
+       CONFIG_RAM_START=0x20000000
 
     CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
 

configs/cloudctrl/nsh/defconfig

@@ -214,8 +214,8 @@ CONFIG_ARCH_STACKDUMP=y
 #
 # Board Settings
 #
-CONFIG_DRAM_START=0x20000000
+CONFIG_RAM_START=0x20000000
-CONFIG_DRAM_SIZE=65536
+CONFIG_RAM_SIZE=65536
 CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
 CONFIG_ARCH_INTERRUPTSTACK=0