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SAML21: Add missing support for GCLK8

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This commit is contained in:
Gregory Nutt
2015-05-23 17:02:13 -06:00
parent 9dc2a891fb
commit 6fef2aabd9
1 changed files with 19 additions and 10 deletions
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configs/saml21-xplained/include/board.h
+19 -10
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@@ -166,7 +166,7 @@
* DFLL output frequency (Fdfll) is given by: * DFLL output frequency (Fdfll) is given by:
* *
* Fdfll = DFLLmul * Frefclk * Fdfll = DFLLmul * Frefclk
* = 6 * 8000000 = 48MHz * = 12 * 4000000 = 48MHz
* *
* Where the reference clock is Generic Clock Channel 0 output of GLCK1. * Where the reference clock is Generic Clock Channel 0 output of GLCK1.
* GCLCK1 provides OSC16M, undivided. * GCLCK1 provides OSC16M, undivided.
@@ -224,7 +224,7 @@
#define BOARD_DFLL48M_MAXCOARSESTEP (0x1f / 4) #define BOARD_DFLL48M_MAXCOARSESTEP (0x1f / 4)
#define BOARD_DFLL48M_MAXFINESTEP (0xff / 4) #define BOARD_DFLL48M_MAXFINESTEP (0xff / 4)
#define BOARD_DFLL48M_FREQUENCY (48000000) #define BOARD_DFLL48M_FREQUENCY (BOARD_DFLL48M_MULTIPLIER * BOARD_OSC16M_FREQUENCY)
/* Fractional Digital Phase Locked Loop configuration. /* Fractional Digital Phase Locked Loop configuration.
* *
@@ -248,18 +248,18 @@
#undef BOARD_FDPLL96M_ENABLE #undef BOARD_FDPLL96M_ENABLE
#undef BOARD_FDPLL96M_RUNINSTDBY #undef BOARD_FDPLL96M_RUNINSTDBY
#define BOARD_FDPLL96M_ONDEMAND 1 #define BOARD_FDPLL96M_ONDEMAND 1
#undef BOARD_FDPLL96M_LBYPASS #undef BOARD_FDPLL96M_LBYPASS
#undef BOARD_FDPLL96M_WUF #undef BOARD_FDPLL96M_WUF
#undef BOARD_FDPLL96M_LPEN #undef BOARD_FDPLL96M_LPEN
#define BOARD_FDPLL96M_FILTER OSCCTRL_DPLLCTRLB_FILTER_DEFAULT #define BOARD_FDPLL96M_FILTER OSCCTRL_DPLLCTRLB_FILTER_DEFAULT
#define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K #define BOARD_FDPLL96M_REFCLK OSCCTRL_DPLLCTRLB_REFLCK_XOSCK32K
#define BOARD_FDPLL96M_REFCLK_CLKGEN 1 #define BOARD_FDPLL96M_REFCLK_CLKGEN 1
#undef BOARD_FDPLL96M_LOCKTIME_ENABLE #undef BOARD_FDPLL96M_LOCKTIME_ENABLE
#define BOARD_FDPLL96M_LOCKTIME OSCCTRL_DPLLCTRLB_LTIME_NONE #define BOARD_FDPLL96M_LOCKTIME OSCCTRL_DPLLCTRLB_LTIME_NONE
#define BOARD_FDPLL96M_LOCKTIME_CLKGEN 1 #define BOARD_FDPLL96M_LOCKTIME_CLKGEN 1
#define BOARD_FDPLL96M_REFDIV 1 #define BOARD_FDPLL96M_REFDIV 1
#define BOARD_FDPLL96M_PRESCALER OSCCTRL_DPLLPRESC_DIV1 #define BOARD_FDPLL96M_PRESCALER OSCCTRL_DPLLPRESC_DIV1
#define BOARD_FDPLL96M_REFFREQ 32768 #define BOARD_FDPLL96M_REFFREQ 32768
#define BOARD_FDPLL96M_FREQUENCY 48000000 #define BOARD_FDPLL96M_FREQUENCY 48000000
@@ -353,6 +353,15 @@
#undef BOARD_GCLK7_OUTPUT_ENABLE #undef BOARD_GCLK7_OUTPUT_ENABLE
#define BOARD_GCLK7_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK7_PRESCALER) #define BOARD_GCLK7_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK7_PRESCALER)
/* Configure GCLK generator 8 */
#undef BOARD_GCLK8_ENABLE
#undef BOARD_GCLK8_RUN_IN_STANDBY
#define BOARD_GCLK8_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#define BOARD_GCLK8_PRESCALER 1
#undef BOARD_GCLK8_OUTPUT_ENABLE
#define BOARD_GCLK8_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK8_PRESCALER)
/* The source of the main clock is always GCLK_MAIN. Also called GCLKGEN[0], this is /* The source of the main clock is always GCLK_MAIN. Also called GCLKGEN[0], this is
* the clock feeding the Power Manager. The Power Manager, in turn, generates main * the clock feeding the Power Manager. The Power Manager, in turn, generates main
* clock which is divided down to produce the CPU, AHB, and APB clocks. * clock which is divided down to produce the CPU, AHB, and APB clocks.