Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-05 15:58:59 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

SAML21-Xlplained: Add options to enable XOSC32K and to use it as the DFLL source; NSH configure now uses DFLL with OSC16M source

Browse Source
This commit is contained in:
Gregory Nutt
2015-05-26 10:39:38 -06:00
parent 6b680686ce
commit 6ec71f792f
3 changed files with 75 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
configs/saml21-xplained/Kconfig
+18 -2
View File
@@ -25,12 +25,29 @@ config SAML21_XPLAINED_OSC16M_16MHZ
endchoice # OSC16M Frequency endchoice # OSC16M Frequency
config SAM21_XPLAINED_XOSC32K
bool "Enable XOSC32K"
default n
config SAML21_XPLAINED_DFLL config SAML21_XPLAINED_DFLL
bool "Use DFLL" bool "Use DFLL"
default n default n
choice choice
prompt "DLL Operating Mode" prompt "DFLL Clock Source"
default SAML21_XPLAINED_DFLL_OSC16MSRC
config SAML21_XPLAINED_DFLL_OSC16MSRC
bool "OSC16M"
config SAML21_XPLAINED_DFLL_XOSC32KSRC
bool "XOSCK32K"
select SAM21_XPLAINED_XOSC32K
endchoice # DFLL Clock Source
choice
prompt "DFLL Operating Mode"
default SAML21_XPLAINED_DFLL_OPENLOOP default SAML21_XPLAINED_DFLL_OPENLOOP
config SAML21_XPLAINED_DFLL_OPENLOOP config SAML21_XPLAINED_DFLL_OPENLOOP
@@ -38,7 +55,6 @@ config SAML21_XPLAINED_DFLL_OPENLOOP
config SAML21_XPLAINED_DFLL_CLOSEDLOOP config SAML21_XPLAINED_DFLL_CLOSEDLOOP
bool "DFLL Closed Loop Mode" bool "DFLL Closed Loop Mode"
depends on EXPERIMENTAL
config SAML21_XPLAINED_DFLL_RECOVERY config SAML21_XPLAINED_DFLL_RECOVERY
bool "DFLL USB Recovery Mode" bool "DFLL USB Recovery Mode"
configs/saml21-xplained/include/board.h
+50 -21
View File
@@ -113,16 +113,18 @@
* BOARD_XOSC32K_WRITELOCK - Boolean (defined / not defined) * BOARD_XOSC32K_WRITELOCK - Boolean (defined / not defined)
*/ */
#undef BOARD_XOSC32K_ENABLE #undef BOARD_XOSC32K_ENABLE
#define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */ #ifdef CONFIG_SAM21_XPLAINED_XOSC32K
#define BOARD_XOSC32K_STARTUPTIME SYSCTRL_XOSC32K_STARTUP_2S # define BOARD_XOSC32K_ENABLE 1
#define BOARD_XOSC32K_ISCRYSTAL 1 # define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */
#define BOARD_XOSC32K_AAMPEN 1 # define BOARD_XOSC32K_STARTUPTIME OSC32KCTRL_XOSC32K_STARTUP_100MS
#undef BOARD_XOSC32K_EN1KHZ # define BOARD_XOSC32K_ISCRYSTAL 1
#define BOARD_XOSC32K_EN32KHZ 1 # undef BOARD_XOSC32K_EN1KHZ
#define BOARD_XOSC32K_ONDEMAND 1 # define BOARD_XOSC32K_EN32KHZ 1
#undef BOARD_XOSC32K_RUNINSTANDBY # define BOARD_XOSC32K_ONDEMAND 1
#undef BOARD_XOSC32K_WRITELOCK # undef BOARD_XOSC32K_RUNINSTANDBY
# undef BOARD_XOSC32K_WRITELOCK
#endif
/* OSC32 Configuration -- not used /* OSC32 Configuration -- not used
* *
@@ -231,16 +233,28 @@
#ifdef CONFIG_SAML21_XPLAINED_DFLL #ifdef CONFIG_SAML21_XPLAINED_DFLL
# define BOARD_DFLL48M_ENABLE 1 /* Using the DFLL48M */ # define BOARD_DFLL48M_ENABLE 1 /* Using the DFLL48M */
# if defined(SAML21_XPLAINED_DFLL_OPENLOOP /* DFLL mode of operation */
# if defined(CONFIG_SAML21_XPLAINED_DFLL_OPENLOOP)
# define BOARD_DFLL48M_OPENLOOP 1 /* In open loop mode */ # define BOARD_DFLL48M_OPENLOOP 1 /* In open loop mode */
# elif defined(SAML21_XPLAINED_DFLL_CLOSEDLOOP # elif defined(CONFIG_SAML21_XPLAINED_DFLL_CLOSEDLOOP)
# define BOARD_DFLL48M_CLOSEDLOOP 1 /* In closed loop mode */ # define BOARD_DFLL48M_CLOSEDLOOP 1 /* In closed loop mode */
# elif defined(SAML21_XPLAINED_DFLL_RECOVERY # elif defined(CONFIG_SAML21_XPLAINED_DFLL_RECOVERY)
# define BOARD_DFLL48M_RECOVERY 1 /* In USB recover mode */ # define BOARD_DFLL48M_RECOVERY 1 /* In USB recover mode */
# else # else
# error DFLL mode not provided # error DFLL mode not provided
# endif # endif
/* DFLL source clock selection */
# if defined(CONFIG_SAML21_XPLAINED_DFLL_OSC16MSRC)
# define BOARD_DFLL_SRC_FREQUENCY BOARD_OSC16M_FREQUENCY
# elif defined(CONFIG_SAML21_XPLAINED_DFLL_XOSC32KSRC)
# define BOARD_DFLL_SRC_FREQUENCY BOARD_XOSC32K_FREQUENCY
# else
# error DFLL clock source not provided
# endif
/* Mode-independent options */ /* Mode-independent options */
# undef BOARD_DFLL48M_RUNINSTDBY # undef BOARD_DFLL48M_RUNINSTDBY
@@ -254,7 +268,7 @@
/* DFLL closed loop mode configuration */ /* DFLL closed loop mode configuration */
# define BOARD_DFLL48M_REFCLK_CLKGEN 1 # define BOARD_DFLL48M_REFCLK_CLKGEN 1
# define BOARD_DFLL48M_MULTIPLIER (48000000 / BOARD_OSC16M_FREQUENCY) # define BOARD_DFLL48M_MULTIPLIER (48000000 / BOARD_DFLL_SRC_FREQUENCY)
# define BOARD_DFLL48M_QUICKLOCK 1 # define BOARD_DFLL48M_QUICKLOCK 1
# define BOARD_DFLL48M_TRACKAFTERFINELOCK 1 # define BOARD_DFLL48M_TRACKAFTERFINELOCK 1
# define BOARD_DFLL48M_KEEPLOCKONWAKEUP 1 # define BOARD_DFLL48M_KEEPLOCKONWAKEUP 1
@@ -262,7 +276,11 @@
# define BOARD_DFLL48M_MAXCOARSESTEP (0x1f / 4) # define BOARD_DFLL48M_MAXCOARSESTEP (0x1f / 4)
# define BOARD_DFLL48M_MAXFINESTEP (0xff / 4) # define BOARD_DFLL48M_MAXFINESTEP (0xff / 4)
# define BOARD_DFLL48M_FREQUENCY (BOARD_DFLL48M_MULTIPLIER * BOARD_OSC16M_FREQUENCY) # ifdef CONFIG_SAML21_XPLAINED_DFLL_OPENLOOP
# define BOARD_DFLL48M_FREQUENCY (13720000) /* REVISIT: Needs to be measured */
# else
# define BOARD_DFLL48M_FREQUENCY (BOARD_DFLL48M_MULTIPLIER * BOARD_DFLL_SRC_FREQUENCY)
# endif
#endif #endif
/* Fractional Digital Phase Locked Loop configuration. /* Fractional Digital Phase Locked Loop configuration.
@@ -339,12 +357,23 @@
/* Configure GCLK generator 1 - Drives the DFLL */ /* Configure GCLK generator 1 - Drives the DFLL */
#define BOARD_GCLK1_ENABLE 1 #if defined(CONFIG_SAML21_XPLAINED_DFLL_OSC16MSRC)
#undef BOARD_GCLK1_RUN_IN_STANDBY # define BOARD_GCLK1_ENABLE 1
#define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M # undef BOARD_GCLK1_RUN_IN_STANDBY
#define BOARD_GCLK1_PRESCALER 1 # define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC16M
#undef BOARD_GCLK1_OUTPUT_ENABLE # define BOARD_GCLK1_PRESCALER 1
#define BOARD_GCLK1_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK1_PRESCALER) # undef BOARD_GCLK1_OUTPUT_ENABLE
# define BOARD_GCLK1_FREQUENCY (BOARD_OSC16M_FREQUENCY / BOARD_GCLK1_PRESCALER)
#elif defined(CONFIG_SAML21_XPLAINED_DFLL_XOSC32KSRC)
# define BOARD_GCLK1_ENABLE 1
# undef BOARD_GCLK1_RUN_IN_STANDBY
# define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_XOSC32K
# define BOARD_GCLK1_PRESCALER 1
# undef BOARD_GCLK1_OUTPUT_ENABLE
# define BOARD_GCLK1_FREQUENCY (BOARD_XOSC32K_FREQUENCY / BOARD_GCLK1_PRESCALER)
#else
# error DFLL clock source not provided
#endif
/* Configure GCLK generator 2 (RTC) */ /* Configure GCLK generator 2 (RTC) */
configs/saml21-xplained/nsh/defconfig
+7 -3
View File
@@ -261,12 +261,16 @@ CONFIG_NSH_MMCSDMINOR=0
# #
# CPU Clock Configuration # CPU Clock Configuration
# #
# CONFIG_SAML21_XPLAINED_OSC16M_4MHZ is not set CONFIG_SAML21_XPLAINED_OSC16M_4MHZ=y
# CONFIG_SAML21_XPLAINED_OSC16M_8MHZ is not set # CONFIG_SAML21_XPLAINED_OSC16M_8MHZ is not set
# CONFIG_SAML21_XPLAINED_OSC16M_12MHZ is not set # CONFIG_SAML21_XPLAINED_OSC16M_12MHZ is not set
CONFIG_SAML21_XPLAINED_OSC16M_16MHZ=y # CONFIG_SAML21_XPLAINED_OSC16M_16MHZ is not set
# CONFIG_SAM21_XPLAINED_XOSC32K is not set
# CONFIG_SAML21_XPLAINED_DFLL is not set # CONFIG_SAML21_XPLAINED_DFLL is not set
CONFIG_SAML21_XPLAINED_DFLL_OPENLOOP=y CONFIG_SAML21_XPLAINED_DFLL_OSC16MSRC=y
# CONFIG_SAML21_XPLAINED_DFLL_XOSC32KSRC is not set
# CONFIG_SAML21_XPLAINED_DFLL_OPENLOOP is not set
CONFIG_SAML21_XPLAINED_DFLL_CLOSEDLOOP=y
# #
# SAML21 Xplained Pro Modules # SAML21 Xplained Pro Modules