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https://github.com/apache/nuttx.git
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arch/risc-v/src/mpfs: Add CorePWM driver
Add a driver for CorePWM block, which can be instantiated on PolarFire SOC FPGA This supports 2 CorePWM blocks on the FPGA. One CorePWM block provides 8 PWM output signals
This commit is contained in:
Antti Vähälummukka
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
bed0f50182
commit
6eb73ced51
@@ -66,6 +66,7 @@ config ARCH_CHIP_MPFS
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select ARCH_RV64GC
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select ARCH_HAVE_MPU
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select ARCH_HAVE_RESET
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select ARCH_HAVE_PWM_MULTICHAN
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---help---
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MicroChip Polarfire processor (RISC-V 64bit core with GCVX extensions).
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@@ -103,6 +103,70 @@ config MPFS_I2C1
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select ARCH_HAVE_I2CRESET
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default n
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comment "CorePWM Options"
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config MPFS_HAVE_COREPWM
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bool "CorePWM FPGA IP block configured"
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default n
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config MPFS_COREPWM0
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bool "CorePWM0 FPGA IP block configured"
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default n
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select PWM_MULTICHAN
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depends on MPFS_HAVE_COREPWM
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config MPFS_COREPWM0_BASE
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hex "Base address for the instance"
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default 0x44000000
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depends on MPFS_COREPWM0
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config MPFS_COREPWM0_PWMCLK
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int "Clock frequency of the CorePWM0 block (Hz)"
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default 25000000
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range 1000000 100000000
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depends on MPFS_COREPWM0
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config MPFS_COREPWM0_REGWIDTH
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int "Width of the PWM register (8, 16 or 32 bits)"
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default 32
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range 8 32
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depends on MPFS_COREPWM0
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config MPFS_COREPWM0_NCHANNELS
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int "Number of Output Channels for CorePWM0"
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default 8
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range 1 16
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depends on MPFS_COREPWM0
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config MPFS_COREPWM1
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bool "CorePWM1 FPGA IP block configured"
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default n
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select PWM_MULTICHAN
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depends on MPFS_HAVE_COREPWM
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config MPFS_COREPWM1_BASE
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hex "Base address for the instance"
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default 0x45000000
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depends on MPFS_COREPWM1
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config MPFS_COREPWM1_PWMCLK
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int "Clock frequency of the CorePWM1 block (Hz)"
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default 25000000
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range 1000000 100000000
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depends on MPFS_COREPWM1
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config MPFS_COREPWM1_REGWIDTH
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int "Width of the PWM register (8, 16 or 32 bits)"
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default 32
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range 8 32
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depends on MPFS_COREPWM1
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config MPFS_COREPWM1_NCHANNELS
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int "Number of Output Channels for CorePWM1"
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default 2
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range 1 16
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depends on MPFS_COREPWM1
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endmenu
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config MPFS_DMA
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@@ -73,3 +73,7 @@ endif
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ifeq ($(CONFIG_I2C),y)
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CHIP_CSRCS += mpfs_i2c.c
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endif
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ifeq (${CONFIG_MPFS_HAVE_COREPWM},y)
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CHIP_CSRCS += mpfs_corepwm.c
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endif
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@@ -0,0 +1,98 @@
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/****************************************************************************
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* arch/risc-v/src/mpfs/hardware/mpfs_corepwm.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_COREPWM_H
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#define __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_COREPWM_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* CorePWM features *********************************************************/
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#define MPFS_MAX_PWM_CHANNELS 16
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/* Register Base Address ****************************************************/
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#define MPFS_COREPWM0_BASE (CONFIG_MPFS_COREPWM0_BASE)
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#define MPFS_COREPWM1_BASE (CONFIG_MPFS_COREPWM1_BASE)
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/* Register offsets *********************************************************/
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#define MPFS_COREPWM_PRESCALE_OFFSET (0x00)
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#define MPFS_COREPWM_PERIOD_OFFSET (0x04)
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#define MPFS_COREPWM_PWM_ENABLE_0_7_OFFSET (0x08)
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#define MPFS_COREPWM_PWM_ENABLE_8_15_OFFSET (0x0C)
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#define MPFS_COREPWM_PWM1_POS_EDGE_OFFSET (0x10)
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#define MPFS_COREPWM_PWM1_NEG_EDGE_OFFSET (0x14)
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#define MPFS_COREPWM_PWM2_POS_EDGE_OFFSET (0x18)
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#define MPFS_COREPWM_PWM2_NEG_EDGE_OFFSET (0x1C)
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#define MPFS_COREPWM_PWM3_POS_EDGE_OFFSET (0x20)
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#define MPFS_COREPWM_PWM3_NEG_EDGE_OFFSET (0x24)
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#define MPFS_COREPWM_PWM4_POS_EDGE_OFFSET (0x28)
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#define MPFS_COREPWM_PWM4_NEG_EDGE_OFFSET (0x2C)
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#define MPFS_COREPWM_PWM5_POS_EDGE_OFFSET (0x30)
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#define MPFS_COREPWM_PWM5_NEG_EDGE_OFFSET (0x34)
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#define MPFS_COREPWM_PWM6_POS_EDGE_OFFSET (0x38)
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#define MPFS_COREPWM_PWM6_NEG_EDGE_OFFSET (0x3C)
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#define MPFS_COREPWM_PWM7_POS_EDGE_OFFSET (0x40)
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#define MPFS_COREPWM_PWM7_NEG_EDGE_OFFSET (0x44)
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#define MPFS_COREPWM_PWM8_POS_EDGE_OFFSET (0x48)
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#define MPFS_COREPWM_PWM8_NEG_EDGE_OFFSET (0x4C)
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#define MPFS_COREPWM_PWM9_POS_EDGE_OFFSET (0x50)
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#define MPFS_COREPWM_PWM9_NEG_EDGE_OFFSET (0x54)
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#define MPFS_COREPWM_PWM10_POS_EDGE_OFFSET (0x58)
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#define MPFS_COREPWM_PWM10_NEG_EDGE_OFFSET (0x5C)
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#define MPFS_COREPWM_PWM11_POS_EDGE_OFFSET (0x60)
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#define MPFS_COREPWM_PWM11_NEG_EDGE_OFFSET (0x64)
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#define MPFS_COREPWM_PWM12_POS_EDGE_OFFSET (0x68)
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#define MPFS_COREPWM_PWM12_NEG_EDGE_OFFSET (0x6C)
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#define MPFS_COREPWM_PWM13_POS_EDGE_OFFSET (0x70)
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#define MPFS_COREPWM_PWM13_NEG_EDGE_OFFSET (0x74)
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#define MPFS_COREPWM_PWM14_POS_EDGE_OFFSET (0x78)
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#define MPFS_COREPWM_PWM14_NEG_EDGE_OFFSET (0x7C)
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#define MPFS_COREPWM_PWM15_POS_EDGE_OFFSET (0x80)
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#define MPFS_COREPWM_PWM15_NEG_EDGE_OFFSET (0x84)
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#define MPFS_COREPWM_PWM16_POS_EDGE_OFFSET (0x88)
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#define MPFS_COREPWM_PWM16_NEG_EDGE_OFFSET (0x8C)
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#define MPFS_COREPWM_STRETCH_OFFSET (0x90)
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#define MPFS_COREPWM_TACHPRESCALE_OFFSET (0x94)
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#define MPFS_COREPWM_TACHSTATUS_OFFSET (0x98)
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#define MPFS_COREPWM_TACHIRQMASK_OFFSET (0x9C)
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#define MPFS_COREPWM_TACHMODE_OFFSET (0xA0)
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#define MPFS_COREPWM_TACHPULSEDUR_0_OFFSET (0xA4)
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#define MPFS_COREPWM_TACHPULSEDUR_1_OFFSET (0xA8)
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#define MPFS_COREPWM_TACHPULSEDUR_2_OFFSET (0xAC)
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#define MPFS_COREPWM_TACHPULSEDUR_3_OFFSET (0xB0)
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#define MPFS_COREPWM_TACHPULSEDUR_4_OFFSET (0xB4)
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#define MPFS_COREPWM_TACHPULSEDUR_5_OFFSET (0xB8)
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#define MPFS_COREPWM_TACHPULSEDUR_6_OFFSET (0xBC)
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#define MPFS_COREPWM_TACHPULSEDUR_7_OFFSET (0xC0)
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#define MPFS_COREPWM_TACHPULSEDUR_8_OFFSET (0xC4)
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#define MPFS_COREPWM_TACHPULSEDUR_9_OFFSET (0xC8)
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#define MPFS_COREPWM_TACHPULSEDUR_10_OFFSET (0xCC)
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#define MPFS_COREPWM_TACHPULSEDUR_11_OFFSET (0xD0)
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#define MPFS_COREPWM_TACHPULSEDUR_12_OFFSET (0xD4)
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#define MPFS_COREPWM_TACHPULSEDUR_13_OFFSET (0xD8)
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#define MPFS_COREPWM_TACHPULSEDUR_14_OFFSET (0xDC)
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#define MPFS_COREPWM_TACHPULSEDUR_15_OFFSET (0xE0)
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#define MPFS_COREPWM_SYNC_UPDATE_OFFSET (0xE4)
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#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_COREPWM_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,100 @@
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/****************************************************************************
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* arch/risc-v/src/mpfs/mpfs_corepwm.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRCMPFS_MPFS_MPFS_COREPWM_H
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#define __ARCH_RISCV_SRCMPFS_MPFS_MPFS_COREPWM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Check if PWM support for any channel is enabled. */
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#ifdef CONFIG_MPFS_HAVE_COREPWM
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/board/board.h>
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#include "mpfs_hal/mss_hal.h"
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#include "hardware/mpfs_corepwm.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: mpfs_corepwm_init
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*
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* Description:
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* Initialize a CorePWM block.
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*
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* Input Parameters:
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* pwmid - A number identifying the pwm block. The number of valid
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* IDs varies depending on the configuration of the FPGA.
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*
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* Returned Value:
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* On success, a pointer to the MPFS CorePWM lower half PWM driver is
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* returned. NULL is returned on any failure.
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*
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****************************************************************************/
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FAR struct pwm_lowerhalf_s *mpfs_corepwm_init(int pwmid);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_MPFS_HAVE_COREPWM */
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#endif /* __ARCH_RISCV_SRCMPFS_MPFS_MPFS_COREPWM_H */
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@@ -42,4 +42,8 @@ ifeq ($(CONFIG_SPI),y)
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CSRCS += mpfs_board_spi.c
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endif
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ifeq ($(CONFIG_MPFS_HAVE_COREPWM),y)
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CSRCS += mpfs_pwm.c
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endif
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include $(TOPDIR)/boards/Board.mk
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@@ -34,6 +34,7 @@
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#include <nuttx/drivers/ramdisk.h>
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#include "mpfsicicle.h"
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#include "mpfs_corepwm.h"
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#include "mpfs.h"
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/****************************************************************************
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@@ -80,5 +81,16 @@ int mpfs_bringup(void)
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}
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#endif
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#ifdef CONFIG_MPFS_HAVE_COREPWM
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/* Configure PWM peripheral interfaces */
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ret = mpfs_pwm_setup();
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if (ret < 0)
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{
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syslog(LOG_ERR, "Failed to initialize CorePWM driver: %d\n", ret);
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}
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#endif
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return ret;
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}
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@@ -0,0 +1,90 @@
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/****************************************************************************
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* boards/risc-v/mpfs/icicle/src/mpfs_pwm.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <errno.h>
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#include <stddef.h>
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#include <debug.h>
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#include <string.h>
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#include <limits.h>
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#include <nuttx/timers/pwm.h>
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#include <arch/board/board.h>
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#include "mpfs_corepwm.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: mpfs_pwm_setup
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*
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* Description:
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*
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* Initialize PWM and register PWM devices
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*
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****************************************************************************/
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int mpfs_pwm_setup(void)
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{
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struct pwm_lowerhalf_s *lower_half = NULL; /* lower-half handle */
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/* The underlying CorePWM driver "knows" there are up to 16 channels
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* available for each timer device, so we don't have to do anything
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* special here.
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*/
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#ifdef CONFIG_MPFS_COREPWM0
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lower_half = mpfs_corepwm_init(0);
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/* If we can't get the lower-half handle, skip and keep going. */
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if (lower_half)
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{
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/* Translate the peripheral number to a device name. */
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pwm_register("/dev/corepwm0", lower_half);
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}
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#endif
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#ifdef CONFIG_MPFS_COREPWM1
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lower_half = mpfs_corepwm_init(1);
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/* If we can't get the lower-half handle, skip and keep going. */
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if (lower_half)
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{
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/* Translate the peripheral number to a device name. */
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pwm_register("/dev/corepwm1", lower_half);
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}
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#endif
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return 0;
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}
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@@ -44,5 +44,6 @@
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int mpfs_bringup(void);
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int mpfs_board_spi_init(void);
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int mpfs_board_i2c_init(void);
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int mpfs_pwm_setup(void);
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#endif /* __BOARDS_RISCV_ICICLE_MPFS_SRC_MPFSICICLE_H */
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