diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h
index a06a57f276f..c869ac90f56 100644
--- a/arch/risc-v/include/irq.h
+++ b/arch/risc-v/include/irq.h
@@ -691,7 +691,6 @@ EXTERN volatile bool g_interrupt_context[CONFIG_SMP_NCPUS];
 
 irqstate_t up_irq_enable(void);
 
-#ifdef CONFIG_ARCH_RV_CPUID_MAP
 /****************************************************************************
  * Name: up_cpu_index
  *
@@ -700,7 +699,16 @@ irqstate_t up_irq_enable(void);
  *
  ****************************************************************************/
 
+#ifdef CONFIG_ARCH_HAVE_MULTICPU
+#ifdef CONFIG_ARCH_USE_S_MODE
 int up_cpu_index(void) noinstrument_function;
+#else
+noinstrument_function static inline int up_cpu_index(void)
+{
+  return READ_CSR(CSR_MHARTID);
+}
+#endif /* CONFIG_ARCH_USE_S_MODE */
+#endif /* CONFIG_ARCH_HAVE_MULTICPU */
 
 /****************************************************************************
  * Name: up_this_cpu
@@ -711,13 +719,9 @@ int up_cpu_index(void) noinstrument_function;
  *
  ****************************************************************************/
 
+#ifdef CONFIG_ARCH_RV_CPUID_MAP
 int up_this_cpu(void);
 #else
-noinstrument_function static inline int up_cpu_index(void)
-{
-  return READ_CSR(CSR_MHARTID);
-}
-
 #define up_this_cpu() up_cpu_index()
 #endif /* CONFIG_ARCH_RV_CPUID_MAP */
 
diff --git a/arch/risc-v/src/common/CMakeLists.txt b/arch/risc-v/src/common/CMakeLists.txt
index 8044dd5d97f..14aa1f726d6 100644
--- a/arch/risc-v/src/common/CMakeLists.txt
+++ b/arch/risc-v/src/common/CMakeLists.txt
@@ -49,8 +49,14 @@ if(CONFIG_SMP)
   list(APPEND SRCS riscv_smpcall.c riscv_cpustart.c)
 endif()
 
+if(CONFIG_ARCH_HAVE_MULTICPU)
+  if(CONFIG_ARCH_USE_S_MODE)
+    list(APPEND SRCS riscv_cpuindex.c)
+  endif()
+endif()
+
 if(CONFIG_ARCH_RV_CPUID_MAP)
-  list(APPEND SRCS riscv_cpuindex.c)
+  list(APPEND SRCS riscv_cpuidmap.c)
 endif()
 
 if(CONFIG_RISCV_MISALIGNED_HANDLER)
diff --git a/arch/risc-v/src/common/Make.defs b/arch/risc-v/src/common/Make.defs
index a812ecd4017..3446c748e91 100644
--- a/arch/risc-v/src/common/Make.defs
+++ b/arch/risc-v/src/common/Make.defs
@@ -52,9 +52,15 @@ ifeq ($(CONFIG_SMP),y)
 CMN_CSRCS += riscv_smpcall.c riscv_cpustart.c
 endif
 
-ifeq ($(CONFIG_ARCH_RV_CPUID_MAP),y)
+ifeq ($(CONFIG_ARCH_HAVE_MULTICPU),y)
+ifeq ($(CONFIG_ARCH_USE_S_MODE),y)
 CMN_CSRCS += riscv_cpuindex.c
 endif
+endif
+
+ifeq ($(CONFIG_ARCH_RV_CPUID_MAP),y)
+CMN_CSRCS += riscv_cpuidmap.c
+endif
 
 ifeq ($(CONFIG_RISCV_MISALIGNED_HANDLER),y)
 CMN_CSRCS += riscv_misaligned.c
diff --git a/arch/risc-v/src/common/riscv_cpuidmap.c b/arch/risc-v/src/common/riscv_cpuidmap.c
new file mode 100644
index 00000000000..e56860c383d
--- /dev/null
+++ b/arch/risc-v/src/common/riscv_cpuidmap.c
@@ -0,0 +1,86 @@
+/****************************************************************************
+ * arch/risc-v/src/common/riscv_cpuidmap.c
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include "riscv_internal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_this_cpu
+ *
+ * Description:
+ *   Return the logical core number. Default implementation is 1:1 mapping,
+ *   i.e. physical=logical.
+ *
+ ****************************************************************************/
+
+int up_this_cpu(void)
+{
+  return riscv_hartid_to_cpuid((int)riscv_mhartid());
+}
+
+/****************************************************************************
+ * Name: riscv_hartid_to_cpuid
+ *
+ * Description:
+ *   Convert physical core number to logical core number. Default
+ *   implementation is 1:1 mapping, i.e. physical=logical.
+ *
+ ****************************************************************************/
+
+int weak_function riscv_hartid_to_cpuid(int hart)
+{
+#ifdef CONFIG_SMP
+  return hart - CONFIG_ARCH_RV_HARTID_BASE;
+#else
+  return 0;
+#endif
+}
+
+/****************************************************************************
+ * Name: riscv_cpuid_to_hartid
+ *
+ * Description:
+ *   Convert logical core number to physical core number. Default
+ *   implementation is 1:1 mapping, i.e. physical=logical.
+ *
+ ****************************************************************************/
+
+int weak_function riscv_cpuid_to_hartid(int cpu)
+{
+#ifdef CONFIG_SMP
+  return cpu + CONFIG_ARCH_RV_HARTID_BASE;
+#else
+  return (int)riscv_mhartid();
+#endif
+}
diff --git a/arch/risc-v/src/common/riscv_cpuindex.c b/arch/risc-v/src/common/riscv_cpuindex.c
index fc6f51b0172..6e35ede46d6 100644
--- a/arch/risc-v/src/common/riscv_cpuindex.c
+++ b/arch/risc-v/src/common/riscv_cpuindex.c
@@ -47,53 +47,3 @@ int up_cpu_index(void)
 {
   return (int)riscv_mhartid();
 }
-
-/****************************************************************************
- * Name: up_this_cpu
- *
- * Description:
- *   Return the logical core number. Default implementation is 1:1 mapping,
- *   i.e. physical=logical.
- *
- ****************************************************************************/
-
-int up_this_cpu(void)
-{
-  return riscv_hartid_to_cpuid((int)riscv_mhartid());
-}
-
-/****************************************************************************
- * Name: riscv_hartid_to_cpuid
- *
- * Description:
- *   Convert physical core number to logical core number. Default
- *   implementation is 1:1 mapping, i.e. physical=logical.
- *
- ****************************************************************************/
-
-int weak_function riscv_hartid_to_cpuid(int hart)
-{
-#ifdef CONFIG_SMP
-  return hart - CONFIG_ARCH_RV_HARTID_BASE;
-#else
-  return 0;
-#endif
-}
-
-/****************************************************************************
- * Name: riscv_cpuid_to_hartid
- *
- * Description:
- *   Convert logical core number to physical core number. Default
- *   implementation is 1:1 mapping, i.e. physical=logical.
- *
- ****************************************************************************/
-
-int weak_function riscv_cpuid_to_hartid(int cpu)
-{
-#ifdef CONFIG_SMP
-  return cpu + CONFIG_ARCH_RV_HARTID_BASE;
-#else
-  return (int)riscv_mhartid();
-#endif
-}