Fix LPC43xx clocking bugs; LPC43xx now runs at 204MHz

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4946 42af7a65-404d-4744-a932-0658087f49c3

configs/lpc4330-xplorer/include/board.h

@@ -69,10 +69,6 @@
 #define BOARD_RTCCLK_FREQUENCY      (32768)     /* RTC oscillator frequency (Y1) */
 #define BOARD_INTRCOSC_FREQUENCY    (4000000)   /* Internal RC oscillator frequency */
 
-/* TODO:  The LPC43xx is capable of running at much higher frequencies, but requires
- * a ramp-up in several stages.
- */
-
 /* Integer and direct modes are supported:
  *
  * In integer mode (Fclkout < 156000000):
@@ -85,12 +81,66 @@
  *    Fcco    = Fclkout
  */
 
-#undef  BOARD_PLL1_DIRECT                       /* Integer mode */
+#ifdef CONFIG_LPC43_72MHz
-#define BOARD_PLL_MSEL              (6)         /* Msel = 6 */
+
-#define BOARD_PLL_NSEL              (1)         /* Nsel = 1 */
+/* NOTE:  At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
-#define BOARD_PLL_PSEL              (2)         /* Psel = 2 */
+ * determined to be:
-#define BOARD_FCLKOUT_FREQUENCY     (72000000)  /* 6 * 12,000,000 / 1 */
+ *
-#define BOARD_FCCO_FREQUENCY        (244000000) /* 2 * 2 * 72,000,000 */
+ *    CONFIG_BOARD_LOOPSPERMSEC=7191
+ *
+ * executing from SRAM.
+ */
+
+/* Final clocking (Integer mode with no ramp-up)
+ *
+ *    Fclkout = 6 * 12MHz / 1  = 72MHz
+ *    Fcco    = 2 * 2 * 72MHz = 216MHz
+ */
+
+#  define BOARD_PLL_MSEL            (6)         /* Msel = 6 */
+#  define BOARD_PLL_NSEL            (1)         /* Nsel = 1 */
+#  define BOARD_PLL_PSEL            (2)         /* Psel = 2 */
+
+#  define BOARD_FCLKOUT_FREQUENCY   (72000000)  /* 6 * 12,000,000 / 1 */
+#  define BOARD_FCCO_FREQUENCY      (244000000) /* 2 * 2 * Fclkout */
+ 
+#else
+
+/* NOTE:  At 72MHz, the calibrated value of CONFIG_BOARD_LOOPSPERMSEC was
+ * determined to be:
+ *
+ *    CONFIG_BOARD_LOOPSPERMSEC=18535
+ *
+ * executing from SRAM.
+ */
+
+/* Intermediate ramp-up clocking (Integer mode). If BOARD_PLL_RAMP_MSEL
+ * is not defined, there will be no ramp-up.  
+ *
+ *    Fclkout = 9 * 12MHz / 1  = 108MHz
+ *    Fcco    = 2 * 1 * 108MHz = 216MHz
+ */
+
+#  define BOARD_PLL_RAMP_MSEL       (9)         /* Msel = 9 */
+#  define BOARD_PLL_RAMP_NSEL       (1)         /* Nsel = 1 */
+#  define BOARD_PLL_RAMP_PSEL       (1)         /* Psel = 1 */
+
+#  define BOARD_RAMP_FCLKOUT        (108000000) /* 9 * 12,000,000 / 1 */
+#  define BOARD_RAMP_FCCO           (216000000) /* 2 * 1 * Fclkout */
+
+/* Final clocking (Direct mode). 
+ *
+ *    Fclkout = 17 * 12MHz / 1 = 204MHz
+ *    Fcco    = Fclockout      = 204MHz
+ */
+
+#  define BOARD_PLL_MSEL            (17)        /* Msel = 17 */
+#  define BOARD_PLL_NSEL            (1)         /* Nsel = 1 */
+
+#  define BOARD_FCLKOUT_FREQUENCY   (204000000) /* 17 * 12,000,000 / 1 */
+#  define BOARD_FCCO_FREQUENCY      (204000000) /* Fclockout */
+
+#endif
 
 /* This is the clock setup we configure for:
  *

configs/lpc4330-xplorer/nsh/defconfig

@@ -81,7 +81,7 @@ CONFIG_ARCH_CHIP=lpc43xx
 CONFIG_ARCH_CHIP_LPC4330FET100=y
 CONFIG_ARCH_BOARD=lpc4330-xplorer
 CONFIG_ARCH_BOARD_LPC4330_XPLORER=y
-CONFIG_BOARD_LOOPSPERMSEC=7191
+CONFIG_BOARD_LOOPSPERMSEC=18535
 CONFIG_DRAM_SIZE=(72*1024)
 CONFIG_DRAM_START=0x10080000
 CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)

configs/lpc4330-xplorer/ostest/defconfig

@@ -81,7 +81,7 @@ CONFIG_ARCH_CHIP=lpc43xx
 CONFIG_ARCH_CHIP_LPC4330FET100=y
 CONFIG_ARCH_BOARD=lpc4330-xplorer
 CONFIG_ARCH_BOARD_LPC4330_XPLORER=y
-CONFIG_BOARD_LOOPSPERMSEC=7191
+CONFIG_BOARD_LOOPSPERMSEC=18535
 CONFIG_DRAM_SIZE=(72*1024)
 CONFIG_DRAM_START=0x10080000
 CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)