arch/arm/src/lpc2378/Kconfig: Create Kconfig for the platform; Adjust configuration names for compatibility, configs/olimex-lpc2378/nsh: Convert to use the kconfig-frontends tools

ChangeLog

@@ -6743,4 +6743,6 @@
 	  kconfig-frontends tools (2014-3-2).
 	* configs/mirtoo/nxffs: Configuration converted to use the kconfig-frontends
 	  tools (2014-3-1).
+	* configs/olimex-lpc2378/nsh: Configuration converted to use the
+	  kconfig-frontends tools (2014-3-2)
 

arch/arm/src/lpc214x/Kconfig

@@ -37,7 +37,7 @@ config DEFAULT_MODE
 endchoice
 
 config CODE_BASE
-	hex "Execuation Base Address"
+	hex "Execution Base Address"
 	default 0x00000000
 	---help---
 		This must match the expected address for the selected "Memory
@@ -45,7 +45,7 @@ config CODE_BASE
 
 		EXTMEM_MODE:  0x8000:0000
 		RAM_MODE:     0x4000:0000
-		DEFAULT)MODE: 0x0000:0000
+		DEFAULT_MODE: 0x0000:0000
 
 config PLL_SETUP
 	bool "Configure the PLL"

arch/arm/src/lpc2378/Kconfig

@@ -4,3 +4,163 @@
 #
 
 comment "LPC2378 Configuration Options"
+
+choice
+	prompt "Memory Execution Mode"
+	default LPC2378_DEFAULT_MODE
+
+config LPC2378_EXTMEM_MODE
+	bool "External Memory Mode"
+	depends on EXPERIMENTAL # Not used
+	---help---
+		Code executes from external memory starting at address 0x8000:0000.
+
+config LPC2378_RAM_MODE
+	bool "RAM Memory Mode"
+	depends on EXPERIMENTAL # Not used
+	---help---
+		Code executes from on-chip RAM at address 0x4000:0000.
+
+config LPC2378_DEFAULT_MODE
+	bool "Default Memory Mode"
+	---help---
+		Executes from 0x0000:0000.  In non-default modes, the MEMAP register
+		is set override the settings of the CPU configuration pins.
+
+endchoice
+
+config LPC2378_CODE_BASE
+	hex "Execution Base Address"
+	default 0x00000000
+	---help---
+		This must match the expected address for the selected "Memory
+		Execution Address":
+
+		LPC2378_EXTMEM_MODE:  0x8000:0000
+		LPC2378_RAM_MODE:     0x4000:0000
+		LPC2378_DEFAULT_MODE: 0x0000:0000
+
+config LPC2378_PLL_SETUP
+	bool "Configure the PLL"
+	default y
+
+config LPC2378_PLL_CLKSRC
+	int "PLL clock source"
+	default 1
+	range 0 2
+	depends on LPC2378_PLL_SETUP
+	---help---
+		PLL clock source
+
+config LPC2378_MAM_SETUP
+	bool "Configure the Memory Accelerator Module (MAM)"
+	default y
+
+config LPC2378_LPC2378_MAMCR_VALUE
+	int "Memory accelerator mode"
+	default 1
+	range 0 2
+	---help---
+		Memory accelerator mode:
+
+		OFF		0
+		PART	1
+		FULL	2
+
+config LPC2378_LPC2378_MAMTIM_VALUE
+	int "Memory accelerator timing value"
+	default 3
+	---help---
+		Memory accelerator timing value
+
+config LPC2378_APBDIV_SETUP
+	bool "Configure the APB Divider"
+	default y
+	depends on EXPERIMENTAL # Not used
+
+config LPC2378_APBDIV_VALUE
+	int "APB Divisor"
+	default 1
+	depends on EXPERIMENTAL # Not used
+
+config LPC2378_EMC_SETUP
+	bool "Configure EMC"
+	default n
+	depends on EXPERIMENTAL # Not used
+
+config LPC2378_BCFG0_SETUP
+	bool "Configure BCFG0"
+	default n
+	depends on EXPERIMENTAL # Not used
+
+config LPC2378_BCFG1_SETUP
+	bool "Configure BCFG1"
+	default n
+	depends on EXPERIMENTAL # Not used
+
+config LPC2378_BCFG2_SETUP
+	bool "Configure BCFG2"
+	default n
+	depends on EXPERIMENTAL # Not used
+
+config BCFG3_SETUP
+	bool "Configure BCFG3"
+	default n
+	depends on EXPERIMENTAL # Not used
+
+config LPC2378_ADC_SETUP
+	bool "Configure ADC"
+	default y
+	depends on EXPERIMENTAL # Not used
+
+menu "LPC2378 Peripheral Support"
+
+config LPC2378_UART0
+	bool "UART0"
+	default y
+	select ARCH_HAVE_UART0
+
+config LPC2378_UART1
+	bool "UART1"
+	default y
+	select ARCH_HAVE_UART1
+
+config LPC2378_UART2
+	bool "UART2"
+	default y
+	select ARCH_HAVE_UART2
+
+config LPC2378_USBDEV
+	bool "USB Device"
+	default y
+	depends on USBDEV
+
+endmenu
+
+if LPC2378_USBDEV
+menu "LPC2378 USB Device Configuration"
+
+config LPC2378_USBDEV_DMA
+	bool "USB Device DMA Support"
+	default n
+
+config LPC2378_USBDEV_NDMADESCRIPTORS
+	int "Number of USB DMA Descriptors"
+	default 8
+	depends on LPC2378_USBDEV_DMA
+
+config LPC2378_USBDEV_EPFAST_INTERRUPT
+	bool "USB Device Fast Endpoint Interrupts"
+	default n
+
+config LPC2378_USBDEV_FRAME_INTERRUPT
+	bool "USB Device Frame Interrupts"
+	default n
+
+config LPC2378_USBDEV_REGDEBUG
+	bool "USB Device Register-Level Debug Output"
+	default n
+	depends on DEBUG
+
+endmenu
+endif

arch/arm/src/lpc2378/lpc23xx_head.S

@@ -6,7 +6,7 @@
  *
  * This file is part of the NuttX RTOS and based on the lpc2148 port:
  *
- *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2012, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -59,6 +59,7 @@
 /* Print a character on the UART to show boot status. This macro will
  * modify r0, r1, r2 and r14
  */
+
 #ifdef CONFIG_DEBUG
 	.macro	showprogress, code
 	mov	r0, #\code
@@ -80,7 +81,7 @@
  *
  * Description:
  *   Interrrupt vector table.  This must be located at the beginning
- *   of the memory space (at CONFIG_CODE_BASE).  The first entry in
+ *   of the memory space (at CONFIG_LPC2378_CODE_BASE).  The first entry in
  *   the vector table is the reset vector and this is the code that
  *   will execute whn the processor is reset.
  *
@@ -136,6 +137,7 @@ _vector_table:
 __start:
 
 	/* Call lowlevel init C-function */
+
 	.extern ConfigurePLL
 	ldr	r0, =ConfigurePLL
 	mov	lr, pc
@@ -153,7 +155,6 @@ __start:
 	
 	showprogress 'A'
 
-
 	/* Setup system stack (and get the BSS range) */
 
 	adr	r0, LC0
@@ -231,4 +232,3 @@ g_idle_topstack:
 	.size	g_idle_topstack, .-g_idle_topstack
 	
 	.end
-

arch/arm/src/lpc2378/lpc23xx_pllsetup.c

@@ -6,7 +6,7 @@
  *
  * This file is part of the NuttX RTOS:
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -46,13 +46,13 @@
  *   MEMAP register is set override the settings of the CPU configuration
  *   pins.
  *
- *  CONFIG_EXTMEM_MODE: Code executes from external memory starting at
+ *  CONFIG_LPC2378_EXTMEM_MODE: Code executes from external memory starting at
  *    address 0x8000:0000.
  *
- *  CONFIG_RAM_MODE: Code executes from on-chip RAM at address
+ *  CONFIG_LPC2378_RAM_MODE: Code executes from on-chip RAM at address
  *     0x4000:0000.
  *
- * Starupt Code must be linked to run at the correct address
+ * Start-up Code must be linked to run at the correct address
  * corresponding to the selected mode.
  */
 
@@ -70,10 +70,10 @@
 #include "lpc23xx_pinsel.h"
 #include "lpc23xx_scb.h"
 
-extern void IO_Init(void);
+void IO_Init(void);
 
 /***********************************************************************
- * Definitions
+ * Pre-processor Definitions
  **********************************************************************/
 
 #if ((FOSC < 32000) || (FOSC > 50000000))
@@ -105,8 +105,8 @@ extern void IO_Init(void);
  * RTC                  2
  */
 
-#ifdef CONFIG_PLL_CLKSRC
+#ifdef CONFIG_LPC2378_PLL_CLKSRC
-#       if ( (CONFIG_PLL_CLKSRC < 0) || (CONFIG_PLL_CLKSRC > 2) )
+#       if ( (CONFIG_LPC2378_PLL_CLKSRC < 0) || (CONFIG_LPC2378_PLL_CLKSRC > 2) )
 #               error "PLL clock source not valid, check configuration "
 #       endif
 #else
@@ -138,13 +138,13 @@ extern void IO_Init(void);
 
 /* LPC2378 Rev. '-' errata MAM may not work if fully enabled */
 
-#ifdef CONFIG_MAM_SETUP
+#ifdef CONFIG_LPC2378_MAM_SETUP
-#  ifndef CONFIG_MAMCR_VALUE    /* Can be selected from config file */
+#  ifndef CONFIG_LPC2378_MAMCR_VALUE    /* Can be selected from config file */
-#    define CONFIG_MAMCR_VALUE  (MAMCR_PART)
+#    define CONFIG_LPC2378_MAMCR_VALUE  (MAMCR_PART)
 #  endif
 
-#  ifndef CONFIG_MAMTIM_VALUE   /* Can be selected from config file */
+#  ifndef CONFIG_LPC2378_MAMTIM_VALUE   /* Can be selected from config file */
-#    define CONFIG_MAMTIM_VALUE (0x00000003)
+#    define CONFIG_LPC2378_MAMTIM_VALUE (0x00000003)
 #  endif
 #endif
 
@@ -171,12 +171,15 @@ void ConfigurePLL(void)
   uint32_t MSel, NSel;
 
   /* LPC2378 Rev.'-' errata Enable the Ethernet block to enable 16k EnetRAM */
+
   SCB_PCONP |= PCENET;
 
   /* Vectors are remapped to Flash */
+
   SCB_MEMMAP = MEMMAP2FLASH;
 
   /* Enable PLL, disconnected */
+
   if (SCB_PLLSTAT & (1 << 25))
     {
       SCB_PLLCON = 0x01;
@@ -184,37 +187,48 @@ void ConfigurePLL(void)
     }
 
   /* Disable PLL, disconnected */
+
   SCB_PLLCON = 0;
   up_scbpllfeed();
 
   /* Enable main OSC */
+
   SCB_SCS |= 0x20;
 
   /* Wait until main OSC is usable */
+
   while (!(SCB_SCS & 0x40));
 
   /* select main OSC, 12MHz, as the PLL clock source */
-  SCB_CLKSRCSEL = CONFIG_PLL_CLKSRC;
+
+  SCB_CLKSRCSEL = CONFIG_LPC2378_PLL_CLKSRC;
 
   /* Reconfigure PLL */
+
   SCB_PLLCFG = PLL;
   up_scbpllfeed();
 
   /* Enable PLL */
+
   SCB_PLLCON = 0x01;
   up_scbpllfeed();
 
   /* Set clock divider */
+
   SCB_CCLKCFG = CCLK_DIV;
 
 #ifdef CONFIG_USBDEV
   /* usbclk = 288 MHz/6 = 48 MHz */
+
   SCB_USBCLKCFG = USBCLK_DIV;
+
   /* Turn On USB PCLK */
+
   SCB_PCONP |= PCUSB;
 #endif
 
   /* Wait for PLL to lock */
+
   while ((SCB_PLLSTAT & (1 << 26)) == 0);
 
   MSel = SCB_PLLSTAT & 0x00007FFF;
@@ -222,18 +236,22 @@ void ConfigurePLL(void)
   while ((MSel != PLL_M) && (NSel != PLL_N));
 
   /* Enable and connect */
+
   SCB_PLLCON = 0x03;
   up_scbpllfeed();
 
   /* Check connect bit status */
+
   while ((SCB_PLLSTAT & (1 << 25)) == 0);
 
   /* Set memory accelerater module */
+
   SCB_MAMCR = 0;
-  SCB_MAMTIM = CONFIG_MAMTIM_VALUE;
+  SCB_MAMTIM = CONFIG_LPC2378_MAMTIM_VALUE;
-  SCB_MAMCR = CONFIG_MAMCR_VALUE;
+  SCB_MAMCR = CONFIG_LPC2378_MAMCR_VALUE;
 
   /* Enable FastIO on P0:P1 */
+
   SCB_SCS |= 0x01;
 
   IO_Init();

arch/arm/src/lpc2378/lpc23xx_scb.h

@@ -6,7 +6,7 @@
  *
  * This file is part of the NuttX RTOS and based on the lpc2148 port:
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -49,17 +49,20 @@
 #include "lpc23xx_vic.h"
 
 /****************************************************************************************************
- * Definitions
+ * Pre-processor Definitions
  ****************************************************************************************************/
+
 #define scb_getreg(o)    getreg32(LPC23XX_SCB_BASE + (o))
 #define scb_putreg(v,o)  putreg32((v),LPC23XX_SCB_BASE + (o))
 
 /* Memory Accelerator Mode */
+
 #define MAMCR_OFF     0
 #define MAMCR_PART    1
 #define MAMCR_FULL    2
 
 /* Memory Mapping */
+
 #define MEMMAP2BBLK   0 /* Interrupt Vectors in Boot Block */
 #define MEMMAP2FLASH  1 /* Interrupt Vectors in FLASH */
 #define MEMMAP2SRAM   2 /* Interrupt Vectors in RAM */
@@ -73,14 +76,13 @@
 
 /* PLL Configuration Register Bit Settings */
 
-#define PLLCFG_MSEL		(0x0000FFFF << 0)  /* PLL Multiplier (minus 1) */
+#define PLLCFG_MSEL   (0x0000ffff << 0)  /* PLL Multiplier (minus 1) */
-#define PLLCFG_NSEL		(0x000000FF << 16) /* PLL Divider */
+#define PLLCFG_NSEL   (0x000000ff << 16) /* PLL Divider */
-
 
 /* PLL Status Register Bit Settings */
 
-#define PLLSTAT_MSEL	(0x7FFF << 0)  /* PLL Multiplier Readback */
+#define PLLSTAT_MSEL  (0x7fff << 0)  /* PLL Multiplier Readback */
-#define PLLSTAT_NSEL	(0xFF << 16)   /* PLL Divider Readback */
+#define PLLSTAT_NSEL  (0xff << 16)   /* PLL Divider Readback */
 #define PLLSTAT_PLLE  (1 << 24)      /* PLL Enable Readback */
 #define PLLSTAT_PLLC  (1 << 25)      /* PLL Connect Readback */
 #define PLLSTAT_PLOCK (1 << 26)      /* PLL Lock Status */
@@ -90,7 +92,6 @@
 #define PLLFEED1      0xaa
 #define PLLFEED2      0x55
 
-
 /* Peripheral Power Control (PCONP) Register 0xE01FC0C4 */
 
 #define PCTIM0        (1 << 1)  /* Timer/Counter 0 */
@@ -104,8 +105,9 @@
 #define PCRTC         (1 << 9)  /* Real Time Clock*/
 #define PCSSP1        (1 << 10) /* SSP1 */
 #define PCEMC         (1 << 11) /* External Memory Controller */
-#define PCAD		(1 << 12)	/* A/D converter (ADC) Note: Clear the PDN bit in the AD0CR before
+#define PCAD          (1 << 12) /* A/D converter (ADC) Note: Clear the PDN
-											clearing this bit, and set this bit before setting PDN */
+                                 * bit in the AD0CR before clearing this bit,
+                                 * and set this bit before setting PDN */
 #define PCAN1         (1 << 13) /* CAN Controller 1 */
 #define PCAN2         (1 << 14) /* CAN Controller 2 */
 #define PCI2C1        (1 << 19) /* The I2C1 interface power/clock control bit */
@@ -120,6 +122,7 @@
 #define PCGPDMA       (1 << 29) /* GP DMA function */
 #define PCENET        (1 << 30) /* Ethernet block */
 #define PCUSB         (1 << 31) /* USB interface */
+
 /****************************************************************************************************
  * Inline Functions
  ****************************************************************************************************/

arch/arm/src/lpc2378/lpc23xx_serial.c

@@ -136,7 +136,7 @@ static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
 
 /* This describes the state of the LPC214X uart0 port. */
 
-#ifdef CONFIG_UART0
+#ifdef CONFIG_LPC2378_UART0
 static struct up_dev_s g_uart0priv =
 {
   .uartbase  = UART0_BASE_ADDR,
@@ -164,7 +164,7 @@ static uart_dev_t g_uart0port =
 };
 #endif
 
-#ifdef CONFIG_UART2
+#ifdef CONFIG_LPC2378_UART2
 
 /* This describes the state of the LPC23XX uart2 port. */
 

configs/olimex-lpc2378/nsh/appconfig

@@ -1,44 +0,0 @@
-############################################################################
-# configs/olimex-lpc2378/nsh/appconfig
-#
-#   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
-#   Author: Gregory Nutt <gnutt@nuttx.org>
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-#    notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-#    notice, this list of conditions and the following disclaimer in
-#    the documentation and/or other materials provided with the
-#    distribution.
-# 3. Neither the name NuttX nor the names of its contributors may be
-#    used to endorse or promote products derived from this software
-#    without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-# Path to example in apps/examples containing the user_start entry point
-
-CONFIGURED_APPS += examples/nsh
-
-# The NSH library
-
-CONFIGURED_APPS += system/readline
-CONFIGURED_APPS += nshlib
-

configs/olimex-lpc2378/src/up_leds.c

@@ -6,7 +6,7 @@
  *
  * This is part of the NuttX RTOS and based on the LPC2148 port:
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2010, 2014 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,34 +48,25 @@
 #include "chip.h"
 #include "up_arch.h"
 #include "up_internal.h"
-//~ #define LPC23XX_FIO_BASE    0x3fffc000  /* Fast I/O 0 base address */
 
 /****************************************************************************
- * Definitions
+ * Pre-processor Definitions
  ****************************************************************************/
 
 /* P3.0 : P0.7 PINSEL6 LEDS 1-8 */
+
 #define LEDBIT(led)     (0x01 << (led))
-#define ALL_LEDS	(0xFF)
+#define ALL_LEDS        (0xff)
 #define STATLED         (0x08)
-//~ #ifdef CONFIG_LPC23XX_FIO
-#  define putled8(v,o)  putreg8((v), (LPC23XX_FIO_BASE+(o)))
-#  define putled32(v,r) putreg32((v),(LPC23XX_FIO_BASE+(r)))
-#  define CLRLEDS   putled(ALL_LEDS,FIO3CLR0_OFFSET)
 
-#  define LED_SET_OFFSET FIO3SET0_OFFSET
+#define putled8(v,o)    putreg8((v), (LPC23XX_FIO_BASE+(o)))
-#  define LED_CLR_OFFSET FIO3CLR0_OFFSET
+#define putled32(v,r)   putreg32((v),(LPC23XX_FIO_BASE+(r)))
-#  define LED_DIR_OFFSET FIO3DIR0_OFFSET
+#define CLRLEDS         putled(ALL_LEDS,FIO3CLR0_OFFSET)
-#  define LED_MASK_OFFSET FIO3MASK0_OFFSET
 
-//~ #else
+#define LED_SET_OFFSET  FIO3SET0_OFFSET
-//~ #  define putled(v,r)    putreg32((v),(LPC23XX_GPIO1_BASE+(r)))
+#define LED_CLR_OFFSET  FIO3CLR0_OFFSET
-//~ #  define CLRLEDS        putled(STATLED,LPC23XX_GPIO1_SET_OFFSET)
+#define LED_DIR_OFFSET  FIO3DIR0_OFFSET
-//~ 
+#define LED_MASK_OFFSET FIO3MASK0_OFFSET
-//~ #  define LED_SET_OFFSET LPC23XX_GPIO_SET_OFFSET
-//~ #  define LED_CLR_OFFSET LPC23XX_GPIO_CLR_OFFSET
-//~ #  define LED_DIR_OFFSET LPC23XX_GPIO_DIR_OFFSET
-//~ #endif
 
 /****************************************************************************
  * Private Data
@@ -86,7 +77,7 @@
  ****************************************************************************/
 
 /****************************************************************************
- * Public Funtions
+ * Public Functions
  ****************************************************************************/
 
 /****************************************************************************
@@ -96,7 +87,7 @@
 #ifdef CONFIG_ARCH_LEDS
 void board_led_initialize(void)
 {
-  /* Initilize GIOs P1.16-P1.23 */
+  /* Initialize GIOs P1.16-P1.23 */
 
   putled8(ALL_LEDS, LED_DIR_OFFSET);
   putled8(ALL_LEDS, LED_CLR_OFFSET);