mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 08:36:24 +08:00
Added: MT29F2G Nand Flash block driver for sam4s-xplained-pro.
Fixed: SDIO Interface hanging after inserted SD Card. Disabled the CONFIG_SYSTEMTICK_EXTCLK, using nxsig_usleep instead of usleep
This commit is contained in:
yjdwbj
Brennan Ashton
@@ -20,4 +20,43 @@ config SAM4S_XPLAINED_PRO_CPULOAD_TIMER_DEVPATH
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default "/dev/tc0"
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depends on TIMER && SCHED_CPULOAD && SCHED_CPULOAD_EXTCLK
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config SAM34_NAND_BLOCKMOUNT
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bool "NAND FLASH auto-mount"
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default n
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depends on NSH_ARCHINIT && SAM34_EXTNAND
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---help---
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Automatically initialize the NAND FLASH driver when NSH starts.
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choice
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prompt "NAND FLASH configuration"
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default SAM34_NAND_NXFFS
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depends on SAM34_NAND_BLOCKMOUNT
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config SAM34_NAND_FTL
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bool "Create NAND FLASH block driver"
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depends on MTD && MTD_NAND
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---help---
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Create the MTD driver for the NAND and "wrap" the NAND as a standard
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block driver that could then, for example, be mounted using FAT or
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any other file system. Any file system may be used, but there will
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be no wear-leveling.
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NOTE: This options is not currently recommended. There is not now
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NuttX file system that can handle the NAND back blocks or performs
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wear-leveling other than NXFFS and NXFFS does not use a block driver
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but, rather, operates directly upon the NAND MTD device.
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config SAM34_NAND_NXFFS
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bool "Create NAND FLASH NXFFS file system"
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depends on MTD && MTD_NAND && FS_NXFFS && NXFFS_NAND
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---help---
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Create the MTD driver for the NAND and mount the NAND device as
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a wear-leveling, NuttX FLASH file system (NXFFS). The downside of
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NXFFS is that it can be very slow.
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NOTE: NXFFS is recommended because (1) it can handle the NAND back
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blocks and (1) performs wear-leveling.
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endchoice # NAND FLASH configuration
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endif
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@@ -0,0 +1,101 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_ARCH_RAMFUNCS is not set
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# CONFIG_MTD_NAND_BLOCKCHECK is not set
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# CONFIG_MTD_NAND_SWECC is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="sam4s-xplained-pro"
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CONFIG_ARCH_BOARD_SAM4S_XPLAINED_PRO=y
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CONFIG_ARCH_CHIP="sam34"
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CONFIG_ARCH_CHIP_ATSAM4SD32C=y
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CONFIG_ARCH_CHIP_SAM34=y
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CONFIG_ARCH_CHIP_SAM4S=y
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CONFIG_ARCH_INTERRUPTSTACK=1024
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_USEBASEPRI=y
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CONFIG_ARM_MPU=y
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CONFIG_BOARDCTL_USBDEVCTRL=y
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CONFIG_BOARD_LATE_INITIALIZE=y
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CONFIG_BOARD_LOOPSPERMSEC=11401
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CONFIG_BUILTIN=y
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CONFIG_CDCACM=y
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CONFIG_CDCACM_BULKIN_REQLEN=250
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CONFIG_CDCACM_RXBUFSIZE=1024
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CONFIG_CDCACM_TXBUFSIZE=1024
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEV_ZERO=y
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CONFIG_FS_FAT=y
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CONFIG_FS_PROCFS=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_IDLETHREAD_STACKSIZE=2048
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CONFIG_INTELHEX_BINARY=y
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CONFIG_JULIAN_TIME=y
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CONFIG_LIBC_STRERROR=y
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CONFIG_LIBC_STRERROR_SHORT=y
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CONFIG_MAX_TASKS=16
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CONFIG_MMCSD_SDIO=y
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CONFIG_MTD=y
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CONFIG_MTD_NAND=y
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CONFIG_MTD_NAND_EMBEDDEDECC=y
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CONFIG_MTD_NAND_MAXNUMBLOCKS=2048
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CONFIG_MTD_NAND_MAXNUMPAGESPERBLOCK=64
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CONFIG_MTD_NAND_MAXPAGEDATASIZE=2048
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CONFIG_MTD_NAND_MAXPAGESPARESIZE=64
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CONFIG_MTD_NAND_MAXSPAREECCBYTES=64
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFCONFIG=y
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CONFIG_NSH_DISABLE_LOSETUP=y
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CONFIG_NSH_FILEIOSIZE=2048
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CONFIG_NSH_READLINE=y
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CONFIG_NSH_STRERROR=y
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CONFIG_PIPES=y
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CONFIG_PREALLOC_MQ_MSGS=8
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_PTHREAD_STACK_DEFAULT=4096
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CONFIG_PTHREAD_STACK_MIN=512
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CONFIG_RAM_SIZE=163840
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CONFIG_RAM_START=0x20000000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=50
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CONFIG_RTC=y
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CONFIG_RTC_ALARM=y
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CONFIG_RTC_FREQUENCY=32768
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CONFIG_RTC_HIRES=y
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CONFIG_SAM34_EXTNAND=y
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CONFIG_SAM34_EXTNANDSIZE=268435456
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CONFIG_SAM34_GPIOC_IRQ=y
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CONFIG_SAM34_GPIO_IRQ=y
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CONFIG_SAM34_HSMCI=y
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CONFIG_SAM34_NAND_BLOCKMOUNT=y
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CONFIG_SAM34_PDCA=y
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CONFIG_SAM34_RTC=y
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CONFIG_SAM34_RTT=y
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CONFIG_SAM34_SMC=y
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CONFIG_SAM34_TC0=y
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CONFIG_SAM34_TC1=y
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CONFIG_SAM34_UART1=y
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CONFIG_SAM34_UDP=y
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CONFIG_SAM34_USART1=y
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CONFIG_SAM34_WDT=y
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SDCLONE_DISABLE=y
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CONFIG_SDIO_BLOCKSETUP=y
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CONFIG_STDIO_BUFFER_SIZE=256
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CONFIG_SYSTEM_NSH=y
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CONFIG_TASK_NAME_SIZE=15
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CONFIG_UART1_SERIAL_CONSOLE=y
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CONFIG_USBDEV=y
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CONFIG_USERMAIN_STACKSIZE=4096
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CONFIG_USER_ENTRYPOINT="nsh_main"
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CONFIG_WATCHDOG=y
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CONFIG_WDT_ENABLED_ON_RESET=y
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CONFIG_WDT_THREAD_STACKSIZE=512
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@@ -15,12 +15,11 @@ CONFIG_ARCH_CHIP_SAM34=y
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CONFIG_ARCH_CHIP_SAM4S=y
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CONFIG_ARCH_INTERRUPTSTACK=1024
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
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CONFIG_ARMV7M_USEBASEPRI=y
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CONFIG_ARM_MPU=y
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CONFIG_BOARDCTL_USBDEVCTRL=y
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CONFIG_BOARD_LATE_INITIALIZE=y
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CONFIG_BOARD_LOOPSPERMSEC=9186
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CONFIG_BOARD_LOOPSPERMSEC=11401
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CONFIG_BUILTIN=y
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CONFIG_CDCACM=y
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CONFIG_CDCACM_BULKIN_REQLEN=250
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@@ -29,7 +28,6 @@ CONFIG_CDCACM_TXBUFSIZE=1024
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CONFIG_DEBUG_FULLOPT=y
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CONFIG_DEBUG_SYMBOLS=y
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CONFIG_DEV_ZERO=y
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CONFIG_DISABLE_ENVIRON=y
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CONFIG_EXAMPLES_CPUHOG=y
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CONFIG_EXAMPLES_SERIALBLASTER=y
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CONFIG_EXAMPLES_SERIALRX=y
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@@ -81,15 +79,11 @@ CONFIG_SAM34_UART1=y
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CONFIG_SAM34_UDP=y
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CONFIG_SAM34_USART1=y
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CONFIG_SAM34_WDT=y
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CONFIG_SCHED_CPULOAD=y
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CONFIG_SCHED_CPULOAD_EXTCLK=y
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CONFIG_SCHED_CPULOAD_TICKSPERSEC=222
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_SDCLONE_DISABLE=y
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CONFIG_SDIO_BLOCKSETUP=y
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CONFIG_STDIO_BUFFER_SIZE=256
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CONFIG_SYSTEMTICK_EXTCLK=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_TASK_NAME_SIZE=15
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CONFIG_UART1_SERIAL_CONSOLE=y
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@@ -261,4 +261,20 @@
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#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
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/* NAND *********************************************************************/
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#define GPIO_SMC_RB (GPIO_INPUT | GPIO_SMC_NWAIT)
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/* Address for transferring command bytes to the nandflash, CLE A22 */
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#define BOARD_NCS0_NAND_CMDADDR 0x60400000
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/* Address for transferring address bytes to the nandflash, ALE A21 */
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#define BOARD_NCS0_NAND_ADDRADDR 0x60200000
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/* Address for transferring data bytes to the nandflash. */
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#define BOARD_NCS0_NAND_DATAADDR 0x60000000
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#endif /* __BOARDS_ARM_SAM34_SAM4S_XPLAINED_PRO_INCLUDE_BOARD_H */
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@@ -37,10 +37,20 @@ include $(TOPDIR)/Make.defs
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CSRCS = sam_boot.c
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ifeq ($(CONFIG_MMCSD_SPI),y)
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CSRCS += sam_spi.c
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endif
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ifeq ($(CONFIG_LIB_BOARDCTL),y)
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CSRCS += sam_appinit.c
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endif
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ifeq ($(CONFIG_SAM34_EXTNAND),y)
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ifeq ($(CONFIG_MTD_NAND),y)
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CSRCS += sam_nandflash.c
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endif
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endif
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ifeq ($(CONFIG_SAM34_HSMCI),y)
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CSRCS += sam_hsmci.c
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endif
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@@ -60,8 +60,16 @@
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#define HAVE_HSMCI 1
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#define HAVE_PROC 1
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#define HAVE_USBDEV 1
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#if defined(CONFIG_MTD_NAND) && defined(CONFIG_SAM34_EXTNAND)
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#define HAVE_NAND 1
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#endif
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#undef HAVE_USBMONITOR
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#if defined(CONFIG_MMCSD_SPI)
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# define HAVE_MMCSD_SPI 1
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#endif
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/* HSMCI */
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/* Can't support MMC/SD if the card interface is not enabled */
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@@ -93,6 +101,16 @@
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# undef HAVE_HSMCI
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#endif
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/* MMC/SD minor numbers */
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#ifndef CONFIG_NSH_MMCSDMINOR
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# define CONFIG_NSH_MMCSDMINOR 0
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#endif
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#ifndef CONFIG_NSH_MMCSDSLOTNO
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# define CONFIG_NSH_MMCSDSLOTNO 0
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#endif
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/* USB Device */
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/* CONFIG_SAM34_UDP and CONFIG_USBDEV must be defined, or there is no USB
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@@ -173,11 +191,24 @@
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* Public data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* SPI0 */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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#ifdef HAVE_MMCSD_SPI
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#define GPIO_SPISD_NPCS0 (GPIO_OUTPUT | GPIO_CFG_PULLUP | GPIO_OUTPUT_SET | \
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GPIO_PORT_PIOA | GPIO_PIN11)
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#define SPISD_PORT SPI0_CS0
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#define GPIO_SPI_CD (GPIO_INPUT | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN19)
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#define SD_SPI_IRQ SAM_IRQ_PC19
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#endif /* HAVE_MMCSD_SPI */
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/* NAND */
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#ifdef HAVE_NAND
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# define NAND_MINOR 0
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# define SAM_SMC_CS0 0 /* GPIO_SMC_NCS0 connect SAM_SMC_CS0_BASE */
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int sam_nand_automount(int minor);
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#endif /* HAVE_NAND */
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/****************************************************************************
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* Name: sam_hsmci_initialize
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@@ -193,6 +224,8 @@ int sam_hsmci_initialize(void);
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# define sam_hsmci_initialize()
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#endif
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int sam_sdinitialize(int port, int minor);
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/****************************************************************************
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* Name: sam_cardinserted
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*
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@@ -235,5 +268,4 @@ bool sam_writeprotected(int slotno);
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int sam_watchdog_initialize(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_SAM34_SAM4S_XPLAINED_SRC_SAM4S_XPLAINED_H */
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@@ -114,6 +114,17 @@ int board_app_initialize(uintptr_t arg)
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}
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#endif
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#ifdef HAVE_NAND
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ret = sam_nand_automount(SAM_SMC_CS0);
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if (ret < 0)
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{
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syslog(LOG_ERR,
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"ERROR: Failed to initialize the NAND: %d (%d)\n",
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ret, errno);
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return ret;
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}
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#endif
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#ifdef HAVE_HSMCI
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/* Initialize the HSMCI driver */
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@@ -157,6 +168,18 @@ int board_app_initialize(uintptr_t arg)
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}
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#endif
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/* SPI */
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#ifdef HAVE_MMCSD_SPI
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ret = sam_sdinitialize(0, 0);
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if (ret < 0)
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{
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syslog(LOG_ERR, "ERROR: Failed to initialize MMC/SD slot: %d\n",
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ret);
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return ret;
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}
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#endif
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#ifdef HAVE_USBMONITOR
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/* Start the USB Monitor */
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|
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|
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@@ -0,0 +1,245 @@
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/****************************************************************************
|
||||
* boards/arm/sam34/sam4s-xplained-pro/src/sam_nandflash.c
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||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
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#include <nuttx/config.h>
|
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|
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#include <sys/mount.h>
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#include <stdbool.h>
|
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#include <stdint.h>
|
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#include <errno.h>
|
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#include <debug.h>
|
||||
|
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#include <nuttx/mtd/mtd.h>
|
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#include <nuttx/fs/nxffs.h>
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#include <arch/board/board.h>
|
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|
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#include "arm_arch.h"
|
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#include "sam_periphclks.h"
|
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#include "sam4s_nand.h"
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#include "hardware/sam_smc.h"
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#include "hardware/sam4s_pinmap.h"
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#include "hardware/sam_matrix.h"
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#include "sam4s-xplained-pro.h"
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#ifdef HAVE_NAND
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|
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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static const gpio_pinset_t g_nandpins[] =
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{
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GPIO_SMC_NCS0, GPIO_SMC_NANDALE, GPIO_SMC_NANDCLE,
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GPIO_SMC_NANDOE, GPIO_SMC_NANDWE, GPIO_SMC_RB,
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GPIO_SMC_D0, GPIO_SMC_D1, GPIO_SMC_D2, GPIO_SMC_D3,
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GPIO_SMC_D4, GPIO_SMC_D5, GPIO_SMC_D6, GPIO_SMC_D7
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};
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#define NAND_NPINS (sizeof(g_nandpins) / sizeof(gpio_pinset_t))
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|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_nandflash_config
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*
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* Description:
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* If CONFIG_SAM34_EXTNAND is defined, then NAND FLASH support is
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* enabled. This function provides the board-specific implementation of
|
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* the logic to reprogram the SMC to support NAND FLASH on the specified
|
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* CS.
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*
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* Input Parameters:
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* cs - Chip select number (in the event that multiple NAND devices
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* are connected on-board).
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*
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* Returned Value:
|
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* OK if the HSMC was successfully configured for this CS. A negated
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* errno value is returned on a failure. This would fail with -ENODEV,
|
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* for example, if the board does not support NAND FLASH on the requested
|
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* CS.
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*
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****************************************************************************/
|
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|
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int board_nandflash_config(int cs)
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{
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/* The Embest and Ronetix CM boards and one Hynix NAND HY27UF(08/16)2G2B
|
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* Series NAND (MT29F2G08ABAEAWP).
|
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* This part has a capacity of 256Mx8bit () with spare 8Mx8 bit capacity.
|
||||
* The device contains 2048 blocks, composed by 64 x 2112 byte pages.
|
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* The effective size is approximately 256MiB.
|
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*
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* NAND is available on NCS0.
|
||||
*/
|
||||
|
||||
int i;
|
||||
|
||||
/* Configure GPIO pins (leaving SRAM in the disabled state) */
|
||||
|
||||
for (i = 0; i < NAND_NPINS; i++)
|
||||
{
|
||||
sam_configgpio(g_nandpins[i]);
|
||||
}
|
||||
|
||||
/* SMC NAND Flash Chip Select Configuration Register */
|
||||
|
||||
putreg32(MATRIX_CCFG_SMCNFCS_SMC_NFCS(cs), SAM_MATRIX_CCFG_SMCNFCS);
|
||||
|
||||
/* below from sam4s-xplained */
|
||||
|
||||
sam_smc_enableclk();
|
||||
|
||||
/* Configure SMC setup timing */
|
||||
|
||||
putreg32(SMCCS_SETUP_NWESETUP(3) | SMCCS_SETUP_NCSWRSETUP(1) |
|
||||
SMCCS_SETUP_NRDSETUP(2) | SMCCS_SETUP_NCSRDSETUP(1),
|
||||
SAM_SMCCS_SETUP(cs));
|
||||
|
||||
/* Configure the SMC pulse timing */
|
||||
|
||||
putreg32(SMCCS_PULSE_NWEPULSE(5) | SMCCS_PULSE_NCSWRPULSE(5) |
|
||||
SMCCS_PULSE_NRDPULSE(5) | SMCCS_PULSE_NCSRDPULSE(5),
|
||||
SAM_SMCCS_PULSE(cs));
|
||||
|
||||
/* Configure the SMC cycle timing */
|
||||
|
||||
/**
|
||||
* Select 0. Chip Select 0 has been programmed with:
|
||||
* NRD_HOLD = 4; READ_MODE = 1 (NRD controlled)
|
||||
* NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled)
|
||||
* TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
|
||||
*/
|
||||
|
||||
putreg32(SMCCS_CYCLE_NWECYCLE(12) | SMCCS_CYCLE_NRDCYCLE(11),
|
||||
SAM_SMCCS_CYCLE(cs));
|
||||
|
||||
/* Configure the SMC mode */
|
||||
|
||||
/**
|
||||
*
|
||||
* READ_MODE:
|
||||
* 0: The read operation is controlled by the NCS signal.
|
||||
* 1: The read operation is controlled by the NRD signal.
|
||||
*
|
||||
**/
|
||||
|
||||
putreg32(SMCCS_MODE_TDFCYCLES(6) | SMCCS_MODE_TDFMODE |
|
||||
SMCCS_MODE_WRITEMODE | SMCCS_MODE_READMODE,
|
||||
SAM_SMCCS_MODE(cs));
|
||||
|
||||
/* Configure NAND PIO pins
|
||||
*
|
||||
* NAND Interface NAND DESC
|
||||
*
|
||||
* NCS0 CE - Dedicated pin; no configuration needed
|
||||
* NANDCLE CLE - Dedicated pin; no configuration needed
|
||||
* NANDALE ALE - Dedicated pin; no configuration needed
|
||||
* NANDOE RE - Dedicated pin; no configuration needed
|
||||
* NANDWE WE - Dedicated pin; no configuration needed
|
||||
* NAND_RB RB - PC13
|
||||
* IO_D0-7 IO0-7 - Dedicated pins; no configuration needed
|
||||
*/
|
||||
|
||||
sam_configgpio(GPIO_SMC_NANDALE);
|
||||
sam_configgpio(GPIO_SMC_NANDCLE);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_nand_automount
|
||||
*
|
||||
* Description:
|
||||
* Initialize and configure the NAND on CS3
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int sam_nand_automount(int minor)
|
||||
{
|
||||
FAR struct mtd_dev_s *mtd;
|
||||
static bool initialized = false;
|
||||
|
||||
/* Have we already initialized? */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
/* Create and initialize an NAND MATD device */
|
||||
|
||||
mtd = sam_nand_initialize(SAM_SMC_CS0);
|
||||
|
||||
if (!mtd)
|
||||
{
|
||||
ferr("ERROR: Failed to create the NAND driver on CS%d\n",
|
||||
SAM_SMC_CS0);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SAM34_NAND_FTL)
|
||||
/* Use the FTL layer to wrap the MTD driver as a block driver */
|
||||
|
||||
int ret = OK;
|
||||
ret = ftl_initialize(NAND_MINOR, mtd);
|
||||
if (ret < 0)
|
||||
{
|
||||
ferr("ERROR: Failed to initialize the FTL layer: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_SAM34_NAND_NXFFS)
|
||||
/* Initialize to provide NXFFS on the MTD interface */
|
||||
|
||||
int ret = OK;
|
||||
ret = nxffs_initialize(mtd);
|
||||
if (ret < 0)
|
||||
{
|
||||
ferr("ERROR: NXFFS initialization failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Mount the file system at /mnt/nand */
|
||||
|
||||
ret = mount(NULL, "/mnt/nand", "nxffs", 0, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
ferr("ERROR: Failed to mount the NXFFS volume: %d\n", errno);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Now we are initialized */
|
||||
|
||||
initialized = true;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* HAVE_NAND */
|
||||
@@ -0,0 +1,195 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/sam34/sam4s-xplained-pro/src/sam_spi.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
#include "chip.h"
|
||||
#include "sam_gpio.h"
|
||||
#include "sam_spi.h"
|
||||
#include "sam4s-xplained-pro.h"
|
||||
|
||||
#if defined(CONFIG_SAM34_SPI0)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spidev_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select PIO pins for the SAM4S-Xplained-Pro
|
||||
* board.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function sam_spidev_initialize(void)
|
||||
{
|
||||
#ifdef CONFIG_SAM34_SPI0
|
||||
sam_configgpio(GPIO_SPI0_NPCS0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
|
||||
*
|
||||
* Description:
|
||||
* These external functions must be provided by board-specific logic.
|
||||
* They include:
|
||||
*
|
||||
* o sam_spi[0|1]select is a functions tomanage the board-specific chip
|
||||
* selects
|
||||
* o sam_spi[0|1]status and sam_spi[0|1]cmddata:
|
||||
* Implementations of the status and cmddata methods of the SPI interface
|
||||
* defined by struct spi_ops_(see include/nuttx/spi/spi.h).
|
||||
* All other methods including sam_spibus_initialize()) are provided by
|
||||
* common SAM3/4 logic.
|
||||
*
|
||||
* To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in sam_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in
|
||||
* your board-specific logic.
|
||||
* These functions will perform chip selection and status operations
|
||||
* using PIOs in the way your board is configured.
|
||||
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
|
||||
* sam_spi[0|1]cmddata() functions in your board-specific logic. This
|
||||
* function will perform cmd/data selection operations using PIOs in
|
||||
* the way your board is configured.
|
||||
* 3. Add a call to sam_spibus_initialize() in your low level application
|
||||
* initialization logic
|
||||
* 4. The handle returned by sam_spibus_initialize() may then be used to
|
||||
* bind the SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]select
|
||||
*
|
||||
* Description:
|
||||
* PIO chip select pins may be programmed by the board specific logic in
|
||||
* one of two different ways. First, the pins may be programmed as SPI
|
||||
* peripherals. In that case, the pins are completely controlled by the
|
||||
* SPI driver. This method still needs to be provided, but it may be only
|
||||
* a stub.
|
||||
*
|
||||
* An alternative way to program the PIO chip select pins is as a normal
|
||||
* PIO output. In that case, the automatic control of the CS pins is
|
||||
* bypassed and this function must provide control of the chip select.
|
||||
* NOTE: In this case, the PIO output pin does *not* have to be the
|
||||
* same as the NPCS pin normal associated with the chip select number.
|
||||
*
|
||||
* Input Parameters:
|
||||
* devid - Identifies the (logical) device
|
||||
* selected - TRUE:Select the device, FALSE:De-select the device
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_SPI0
|
||||
void sam_spi0select(uint32_t devid, bool selected)
|
||||
{
|
||||
#ifdef CONFIG_MMCSD_SPI
|
||||
/* The AT25 serial FLASH connects using NPCS0 */
|
||||
|
||||
if (devid == SPIDEV_MMCSD(0))
|
||||
{
|
||||
sam_gpiowrite(GPIO_SPI0_NPCS0, !selected);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]status
|
||||
*
|
||||
* Description:
|
||||
* Return status information associated with the SPI device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Value:
|
||||
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAM34_SPI0
|
||||
uint8_t sam_spi0status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif
|
||||
|
||||
int sam_sdinitialize(int port, int minor)
|
||||
{
|
||||
FAR struct spi_dev_s *spi;
|
||||
int ret;
|
||||
|
||||
/* Get the SPI driver instance for the SD chip select */
|
||||
|
||||
finfo("Initializing SERCOM SPI%d\n", port);
|
||||
|
||||
spi = sam_spibus_initialize(port);
|
||||
if (!spi)
|
||||
{
|
||||
ferr("ERROR: Failed to initialize SPI%d\n", port);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
finfo("Successfully initialized SPI%d\n", port);
|
||||
|
||||
/* Bind the SPI device for the chip select to the slot */
|
||||
|
||||
finfo("Binding SPI%d to MMC/SD slot %d\n", port, 0);
|
||||
|
||||
ret = mmcsd_spislotinitialize(minor, 0, spi);
|
||||
if (ret < 0)
|
||||
{
|
||||
ferr("ERROR: Failed to bind SPI%d to MMC/SD slot %d: %d\n",
|
||||
port, 0, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
finfo("Successfully bound SPI%d to MMC/SD slot %d\n",
|
||||
port, 0);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SAM34_SPI0 */
|
||||
Reference in New Issue
Block a user